[coreboot] New patch to review for coreboot: 02eb12b baskingridge: rename graysreef to baskingridge

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Mar 12 22:51:14 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2672

-gerrit

commit 02eb12b52773a2c5aeefedf8b82c456761711dce
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Mar 12 14:32:26 2013 -0700

    baskingridge: rename graysreef to baskingridge
    
    The Grays Reef CRB is deprecated by order of Intel. Basking Ridge
    is the new hotness. Therefore, rename graysreef to basking ridge.
    
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649
---
 src/mainboard/intel/Kconfig                        |   6 +-
 src/mainboard/intel/baskingridge/Kconfig           |  45 +++
 src/mainboard/intel/baskingridge/Makefile.inc      |  23 ++
 src/mainboard/intel/baskingridge/acpi/chromeos.asl |  24 ++
 src/mainboard/intel/baskingridge/acpi/ec.asl       |   0
 .../intel/baskingridge/acpi/haswell_pci_irqs.asl   |  69 +++++
 .../intel/baskingridge/acpi/mainboard.asl          |  28 ++
 src/mainboard/intel/baskingridge/acpi/platform.asl |  86 ++++++
 src/mainboard/intel/baskingridge/acpi/superio.asl  |  35 +++
 src/mainboard/intel/baskingridge/acpi/thermal.asl  | 275 ++++++++++++++++++
 src/mainboard/intel/baskingridge/acpi/video.asl    |  43 +++
 src/mainboard/intel/baskingridge/acpi_tables.c     | 285 ++++++++++++++++++
 src/mainboard/intel/baskingridge/chromeos.c        | 122 ++++++++
 src/mainboard/intel/baskingridge/cmos.layout       | 135 +++++++++
 src/mainboard/intel/baskingridge/devicetree.cb     |  84 ++++++
 src/mainboard/intel/baskingridge/dsdt.asl          |  56 ++++
 src/mainboard/intel/baskingridge/fadt.c            | 156 ++++++++++
 src/mainboard/intel/baskingridge/gpio.h            | 247 ++++++++++++++++
 src/mainboard/intel/baskingridge/hda_verb.h        |  99 +++++++
 src/mainboard/intel/baskingridge/mainboard.c       | 244 ++++++++++++++++
 src/mainboard/intel/baskingridge/mainboard_smi.c   |  97 +++++++
 src/mainboard/intel/baskingridge/onboard.h         |  37 +++
 src/mainboard/intel/baskingridge/romstage.c        | 318 +++++++++++++++++++++
 src/mainboard/intel/baskingridge/thermal.h         |  57 ++++
 src/mainboard/intel/graysreef/Kconfig              |  45 ---
 src/mainboard/intel/graysreef/Makefile.inc         |  23 --
 src/mainboard/intel/graysreef/acpi/chromeos.asl    |  24 --
 src/mainboard/intel/graysreef/acpi/ec.asl          |   0
 .../intel/graysreef/acpi/haswell_pci_irqs.asl      |  69 -----
 src/mainboard/intel/graysreef/acpi/mainboard.asl   |  28 --
 src/mainboard/intel/graysreef/acpi/platform.asl    |  86 ------
 src/mainboard/intel/graysreef/acpi/superio.asl     |  35 ---
 src/mainboard/intel/graysreef/acpi/thermal.asl     | 275 ------------------
 src/mainboard/intel/graysreef/acpi/video.asl       |  43 ---
 src/mainboard/intel/graysreef/acpi_tables.c        | 285 ------------------
 src/mainboard/intel/graysreef/chromeos.c           | 122 --------
 src/mainboard/intel/graysreef/cmos.layout          | 135 ---------
 src/mainboard/intel/graysreef/devicetree.cb        |  84 ------
 src/mainboard/intel/graysreef/dsdt.asl             |  56 ----
 src/mainboard/intel/graysreef/fadt.c               | 156 ----------
 src/mainboard/intel/graysreef/gpio.h               | 247 ----------------
 src/mainboard/intel/graysreef/hda_verb.h           |  99 -------
 src/mainboard/intel/graysreef/mainboard.c          | 244 ----------------
 src/mainboard/intel/graysreef/mainboard_smi.c      |  97 -------
 src/mainboard/intel/graysreef/onboard.h            |  37 ---
 src/mainboard/intel/graysreef/romstage.c           | 318 ---------------------
 src/mainboard/intel/graysreef/thermal.h            |  57 ----
 47 files changed, 2568 insertions(+), 2568 deletions(-)

diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig
index 9426242..fff6594 100644
--- a/src/mainboard/intel/Kconfig
+++ b/src/mainboard/intel/Kconfig
@@ -19,8 +19,8 @@ config BOARD_INTEL_TRUXTON
 	bool "EP80579 devkit (Truxton)"
 config BOARD_INTEL_XE7501DEVKIT
 	bool "XE7501devkit"
-config BOARD_INTEL_GRAYSREEF
-	bool "Grays Reef CRB"
+config BOARD_INTEL_BASKING_RIDGE
+	bool "Basking Ridge CRB"
 
 endchoice
 
@@ -28,7 +28,7 @@ source "src/mainboard/intel/d810e2cb/Kconfig"
 source "src/mainboard/intel/d945gclf/Kconfig"
 source "src/mainboard/intel/eagleheights/Kconfig"
 source "src/mainboard/intel/emeraldlake2/Kconfig"
-source "src/mainboard/intel/graysreef/Kconfig"
+source "src/mainboard/intel/baskingridge/Kconfig"
 source "src/mainboard/intel/jarrell/Kconfig"
 source "src/mainboard/intel/mtarvon/Kconfig"
 source "src/mainboard/intel/truxton/Kconfig"
diff --git a/src/mainboard/intel/baskingridge/Kconfig b/src/mainboard/intel/baskingridge/Kconfig
new file mode 100644
index 0000000..a8478a8
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_INTEL_BASKING_RIDGE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_HASWELL
+	select SOUTHBRIDGE_INTEL_LYNXPOINT
+	select BOARD_ROMSIZE_KB_8192
+	select BOARD_HAS_FADT
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select HAVE_MAINBOARD_RESOURCES
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select GFXUMA
+	select CHROMEOS
+	select EXTERNAL_MRC_BLOB
+
+config MAINBOARD_DIR
+	string
+	default intel/baskingridge
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "BASKING RIDGE"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 16
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0166.rom"
+
+endif # BOARD_INTEL_BASKING_RIDGE
diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc
new file mode 100644
index 0000000..80385d6
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl
new file mode 100644
index 0000000..307e2e2
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/chromeos.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+	Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
+	Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
+	Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/intel/baskingridge/acpi/ec.asl b/src/mainboard/intel/baskingridge/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl
new file mode 100644
index 0000000..6f2d3e9
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/intel/baskingridge/acpi/mainboard.asl b/src/mainboard/intel/baskingridge/acpi/mainboard.asl
new file mode 100644
index 0000000..6b15331
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x05})
+}
diff --git a/src/mainboard/intel/baskingridge/acpi/platform.asl b/src/mainboard/intel/baskingridge/acpi/platform.asl
new file mode 100644
index 0000000..fea92d0
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/platform.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// NVS has a flag to determine USB policy in S3
+	if (S3U0) {
+		Store (One, GP47)   // Enable USB0
+	} Else {
+		Store (Zero, GP47)  // Disable USB0
+	}
+
+	// NVS has a flag to determine USB policy in S3
+	if (S3U1) {
+		Store (One, GP56)   // Enable USB1
+	} Else {
+		Store (Zero, GP56)  // Disable USB1
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl
new file mode 100644
index 0000000..a50c4b3
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/superio.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0           // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_INFR           // pnp 2e.a: Disable Consumer IR
+
+#define SIO_ENABLE_PS2K          // pnp 2e.5: Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // pnp 2e.6: Enable PS/2 Mouse
+#define SIO_ENABLE_COM1          // pnp 2e.1: Enable Serial Port 1
+#define SIO_ENABLE_ENVC          // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0      0x700  // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1      0x710  // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO	  	 // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
+
+#include "superio/smsc/sio1007/acpi/superio.asl"
diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl
new file mode 100644
index 0000000..f8e9d97
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 0 seconds
+		Name (_TZP, 0)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			// FIXME: figure out how to read temp on this board.
+			Store (30, Local0)
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (\F2ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (0, \FLVL)
+				Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
+
diff --git a/src/mainboard/intel/baskingridge/acpi/video.asl b/src/mainboard/intel/baskingridge/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c
new file mode 100644
index 0000000..823abcf
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/acpi_tables.c
@@ -0,0 +1,285 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->f4of = FAN4_THRESHOLD_OFF;
+	gnvs->f4on = FAN4_THRESHOLD_ON;
+	gnvs->f4pw = FAN4_PWM;
+
+	gnvs->f3of = FAN3_THRESHOLD_OFF;
+	gnvs->f3on = FAN3_THRESHOLD_ON;
+	gnvs->f3pw = FAN3_PWM;
+
+	gnvs->f2of = FAN2_THRESHOLD_OFF;
+	gnvs->f2on = FAN2_THRESHOLD_ON;
+	gnvs->f2pw = FAN2_PWM;
+
+	gnvs->f1of = FAN1_THRESHOLD_OFF;
+	gnvs->f1on = FAN1_THRESHOLD_ON;
+	gnvs->f1pw = FAN1_PWM;
+
+	gnvs->f0of = FAN0_THRESHOLD_OFF;
+	gnvs->f0on = FAN0_THRESHOLD_ON;
+	gnvs->f0pw = FAN0_PWM;
+
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/*
+	 * Enable Front USB ports in S5 by default
+	 * to be consistent with back port behavior
+	 */
+	gnvs->s5u0 = 1;
+	gnvs->s5u1 = 1;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+	// TODO(reinauer) this could move elsewhere?
+	chromeos_init_vboot(&(gnvs->chromeos));
+	/* Emerald Lake has no EC (?) */
+	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+#endif
+
+	acpi_update_thermal_table(gnvs);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			acpi_save_gnvs(current);
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
new file mode 100644
index 0000000..4ee9d62
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <southbridge/intel/lynxpoint/pch.h>
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT	6
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+	if (!gpio_base)
+		return;
+
+	u32 gp_lvl = inl(gpio_base + 0x0c);
+	u32 gp_lvl2 = inl(gpio_base + 0x38);
+	/* u32 gp_lvl3 = inl(gpio_base + 0x48); */
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	/* Write Protect: GPIO48 */
+	gpios->gpios[0].port = 48;
+	gpios->gpios[0].polarity = ACTIVE_LOW;
+	gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1;
+	strncpy((char *)gpios->gpios[0].name,"write protect",
+							GPIO_MAX_NAME_LENGTH);
+
+	/* Recovery: GPIO22 */
+	gpios->gpios[1].port = 22;
+	gpios->gpios[1].polarity = ACTIVE_LOW;
+	gpios->gpios[1].value = (gp_lvl >> 22) & 1;
+	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+	/* Developer: GPIO57 */
+	gpios->gpios[2].port = 57;
+	gpios->gpios[2].polarity = ACTIVE_LOW;
+	gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1;
+	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+	/* Hard code the lid switch GPIO to open. */
+	gpios->gpios[3].port = -1;
+	gpios->gpios[3].polarity = ACTIVE_HIGH;
+	gpios->gpios[3].value = 1;
+	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+	/* Power Button */
+	gpios->gpios[4].port = -1;
+	gpios->gpios[4].polarity = ACTIVE_HIGH;
+	gpios->gpios[4].value = 0;
+	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+	/* Did we load the VGA option ROM? */
+	gpios->gpios[5].port = -1;
+	gpios->gpios[5].polarity = ACTIVE_HIGH;
+	gpios->gpios[5].value = oprom_is_loaded;
+	strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 0);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+	u32 gp_lvl2 = inl(gpio_base + 0x38);
+
+	/* Developer: GPIO17, active high */
+	return (gp_lvl2 >> (57-32)) & 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 0);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+	u32 gp_lvl = inl(gpio_base + 0x0c);
+
+	/* Recovery: GPIO22, active low */
+	return !((gp_lvl >> 22) & 1);
+}
+
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
new file mode 100644
index 0000000..e8a088d
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/cmos.layout
@@ -0,0 +1,135 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
new file mode 100644
index 0000000..737de1c
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -0,0 +1,84 @@
+chip northbridge/intel/haswell
+
+	# Enable DisplayPort 1 Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable DisplayPort 0 Hotplug with 6ms pulse
+	register "gpu_dp_c_hotplug" = "0x06"
+
+	# Enable DVI Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "0x06"
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/haswell
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi1_routing" = "1"
+			register "gpi14_routing" = "2"
+			register "alt_gp_smi_en" = "0x0002"
+			register "gpe0_en" = "0x4000"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x3f"
+
+			# SuperIO range is 0x700-0x73f
+			register "gen2_dec" = "0x003c0701"
+
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1 (WLAN)
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 on end # PCIe Port #3 (Debug)
+			device pci 1c.3 on end # PCIe Port #4 (LAN)
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on end # LPC bridge
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 on end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
new file mode 100644
index 0000000..79bb8f3
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	#include "acpi/thermal.asl"
+
+	#include "../../../cpu/intel/haswell/acpi/cpu.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+		}
+	}
+
+	#include "acpi/chromeos.asl"
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/baskingridge/fadt.c b/src/mainboard/intel/baskingridge/fadt.c
new file mode 100644
index 0000000..315cb58
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/fadt.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_DESKTOP;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h
new file mode 100644
index 0000000..13126bf
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/gpio.h
@@ -0,0 +1,247 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BASKING_RIDGE_GPIO_H
+#define BASKING_RIDGE_GPIO_H
+
+#include "southbridge/intel/lynxpoint/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,    /* PCH_GPIO0_R -> S_GPIO -> J9F5 */
+	.gpio1 = GPIO_MODE_GPIO,    /* SMC_EXTSMI_N */
+	.gpio2 = GPIO_MODE_GPIO,    /* TP_RSVD_TESTMODE  - float */
+	.gpio3 = GPIO_MODE_NATIVE,  /* PCH_PCI_IRQ_N -> SIO GPIO12/SMI# */
+	.gpio4 = GPIO_MODE_GPIO,    /* EXTTS_SNI_DRV0_PCH  - float */
+	.gpio5 = GPIO_MODE_GPIO,    /* EXTTS_SNI_DRV1_PCH  - float */
+	.gpio6 = GPIO_MODE_GPIO,    /* DGPU_HPD_INTR_N */
+	.gpio7 = GPIO_MODE_GPIO,    /* SMC_RUNTIME_SCI_N */
+	.gpio8 = GPIO_MODE_GPIO,    /* PCH_GPIO8 -> DDR Voltage Select Bit 0 */
+	.gpio9  = GPIO_MODE_NATIVE, /* USB_OC_10_11_R_N */
+	.gpio10 = GPIO_MODE_NATIVE, /* USB_OC_12_13_R_N */
+	.gpio11 = GPIO_MODE_GPIO,   /* PCH_GPIO11 -> HOST_ALERT2_N -> PCIE_RSVD_2_N (3GIO_X1) slot 4 */
+	.gpio12 = GPIO_MODE_GPIO,   /* PM_LANPHY_ENABLE */
+	.gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST_N */
+	.gpio14 = GPIO_MODE_GPIO,   /* SMC_WAKE_SCI_N (not stuffed) & USB_8_9_PWR */
+	.gpio15 = GPIO_MODE_GPIO,   /* Always GPIO: HOST_ALERT1_R_N -> PCIE_RSV_1_N */
+	.gpio16 = GPIO_MODE_NATIVE, /* SATA_DET4_R_N */
+	.gpio17 = GPIO_MODE_GPIO,   /* DGPU_PWROK */
+	.gpio18 = GPIO_MODE_NATIVE, /* CK_SLOT1_OE_N_R */
+	.gpio19 = GPIO_MODE_GPIO,   /* BBS_BIT0_R - STRAP */
+	.gpio20 = GPIO_MODE_NATIVE, /* CK_SLOT2_OE_N_R */
+	.gpio21 = GPIO_MODE_GPIO,   /* SATA_DET0_R_N -> J9H4 */
+	.gpio22 = GPIO_MODE_GPIO,   /* BIOS_REC -> J8G1 */
+	.gpio23 = GPIO_MODE_NATIVE, /* PCH_DRQ1_N */
+	.gpio24 = GPIO_MODE_GPIO,   /* Always GPIO: PCH_GPIO24_R1 -> DDR Voltage Select Bit 2 */
+	.gpio25 = GPIO_MODE_NATIVE, /* CK_SLOT3_OE_N */
+	.gpio26 = GPIO_MODE_NATIVE, /* CK_SLOT4_OE_N */
+	.gpio27 = GPIO_MODE_GPIO,   /* Always GPIO: PCH_GPIO_27 -> SMC_WAKE_SCI_N & LANWAKE_N */
+	.gpio28 = GPIO_MODE_GPIO,   /* Always GPIO: PLL_ODVR_EN -> PCH_AUDIO_PWR_N */
+	.gpio29 = GPIO_MODE_NATIVE, /* PCH_SLP_WLAN_N */
+	.gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK_R */
+	.gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT_R */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_OUTPUT,
+	/* .gpio3 NATIVE */
+	.gpio4 = GPIO_DIR_OUTPUT,
+	.gpio5 = GPIO_DIR_OUTPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	/* .gpio10  NATIVE */
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	/* .gpio13  NATIVE */
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	/* .gpio16  NATIVE */
+	.gpio17 = GPIO_DIR_INPUT,
+	/* .gpio18  NATIVE */
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	/* .gpio23  NATIVE */
+	.gpio24 = GPIO_DIR_OUTPUT,
+	/* .gpio25  NATIVE */
+	/* .gpio26  NATIVE */
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	/* .gpio29  NATIVE */
+	/* .gpio30  NATIVE */
+	/* .gpio31  NATIVE */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio2 = GPIO_LEVEL_HIGH,
+	.gpio4 = GPIO_LEVEL_HIGH,
+	.gpio5 = GPIO_LEVEL_HIGH,
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE, /* Always GPIO on desktop. Mobile Native. PM_CLKRUN_N */
+	.gpio33 = GPIO_MODE_NATIVE, /* HDADOCKEN_R_N */
+	.gpio34 = GPIO_MODE_GPIO,   /* PCH_GPIO34 -> SATA_PWR_EN0_N */
+	.gpio35 = GPIO_MODE_GPIO,   /* SATA_PWR_EN1_R_N  */
+	.gpio36 = GPIO_MODE_NATIVE, /* SATA_ODD_PRSNT_R_N */
+	.gpio37 = GPIO_MODE_NATIVE, /* SATA_ODD_DA_N_R */
+	.gpio38 = GPIO_MODE_GPIO,   /* MFG_MODE */
+	.gpio39 = GPIO_MODE_GPIO,   /* GFX_CRB_DET */
+	.gpio40 = GPIO_MODE_NATIVE, /* USB_OC_2_5_R_N */
+	.gpio41 = GPIO_MODE_GPIO,   /* USB_0_1_PWR */
+	.gpio42 = GPIO_MODE_NATIVE, /* USB_OC_6_7_R_N */
+	.gpio43 = GPIO_MODE_NATIVE, /* USB_OSC_8_9_R_N */
+	.gpio44 = GPIO_MODE_NATIVE, /* CK_SLOT5_OE_N */
+	.gpio45 = GPIO_MODE_NATIVE, /* CK_PCIE_LAN_REQ_N */
+	.gpio46 = GPIO_MODE_GPIO,   /* PCH_GPIO46_R -> DDR Voltage Select Bit 1 */
+	.gpio47 = GPIO_MODE_NATIVE, /* PEGA_CKREQ_N */
+	.gpio48 = GPIO_MODE_GPIO,   /* BIOS_RESP -> J8E6 */
+	.gpio49 = GPIO_MODE_GPIO,   /* PCH_GP_49 -> CRIT_TEMP_REP_N */
+	.gpio50 = GPIO_MODE_GPIO,   /* DGPU_HOLD_RST_N */
+	.gpio51 = GPIO_MODE_GPIO,   /* BBS_BIT1 Strap */
+	.gpio52 = GPIO_MODE_GPIO,   /* DGPU_SELECT_N */
+	.gpio53 = GPIO_MODE_GPIO,   /* DGPU_PWM_SELECT_N -> PEG_JTAG5 */
+	.gpio54 = GPIO_MODE_GPIO,   /* DGPU_PWR_EN_N -> PEG_RSVD5 */
+	.gpio55 = GPIO_MODE_GPIO,   /* STP_A16OVR Strap */
+	.gpio56 = GPIO_MODE_NATIVE, /* MC_CKREQ_N */
+	.gpio57 = GPIO_MODE_GPIO,   /* Always GPIO. NFC_IRQ_R */
+	.gpio58 = GPIO_MODE_NATIVE, /* SML1_CK */
+	.gpio59 = GPIO_MODE_NATIVE, /* USB_OC_0_1_R_N */
+	.gpio60 = GPIO_MODE_GPIO,   /* DRAMRST_CNTRL_PCH */
+	.gpio61 = GPIO_MODE_NATIVE, /* PM_SUS_STAT_N */
+	.gpio62 = GPIO_MODE_NATIVE, /* SUS_CK */
+	.gpio63 = GPIO_MODE_NATIVE, /* SLP_S5_R_N */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	/* .gpio32  NATIVE */
+	/* .gpio33  NATIVE */
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	/* .gpio36  NATIVE */
+	/* .gpio37  NATIVE */
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	/* .gpio40  NATIVE */
+	.gpio41 = GPIO_DIR_OUTPUT,
+	/* .gpio42  NATIVE */
+	/* .gpio43  NATIVE */
+	/* .gpio44  NATIVE */
+	/* .gpio45  NATIVE */
+	.gpio46 = GPIO_DIR_OUTPUT,
+	/* .gpio47  NATIVE */
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio50 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_OUTPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	/* .gpio56  NATIVE */
+	.gpio57 = GPIO_DIR_INPUT,
+	/* .gpio58  NATIVE */
+	/* .gpio59  NATIVE */
+	.gpio60 = GPIO_DIR_OUTPUT,
+	/* .gpio61  NATIVE */
+	/* .gpio62  NATIVE */
+	/* .gpio63  NATIVE */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio41 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_HIGH,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio52 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_LOW,
+	.gpio54 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE, /* CK_PCH_SIO_DOCK_R -> TP_CK_PCI_SIO_DOCK */
+	.gpio65 = GPIO_MODE_NATIVE, /* CK_FLEX1 */
+	.gpio66 = GPIO_MODE_GPIO,   /* CK_FLEX2 */
+	.gpio67 = GPIO_MODE_GPIO,   /* DGPU_PRSNT_N -> PEG_RSVD3 */
+	.gpio68 = GPIO_MODE_GPIO,   /* SATA_ODD_PWRGT */
+	.gpio69 = GPIO_MODE_GPIO,   /* SV_DET -> J8E5 */
+	.gpio70 = GPIO_MODE_GPIO,   /* USB3_DET_P2_N */
+	.gpio71 = GPIO_MODE_GPIO,   /* USB3_DET_P3_N */
+	.gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW_R_N */
+	.gpio73 = GPIO_MODE_NATIVE, /* CK_REQ_DOCK_N */
+	.gpio74 = GPIO_MODE_NATIVE, /* PCH_GPIO74_R -> AMB_THM2_R_N (PCHHOT) */
+	.gpio75 = GPIO_MODE_NATIVE, /* SM1_DATA */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_OUTPUT,
+	/* .gpio65  NATIVE */
+	.gpio66 = GPIO_DIR_OUTPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_OUTPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	/* .gpio72  NATIVE */
+	/* .gpio73  NATIVE */
+	/* .gpio74  NATIVE */
+	/* .gpio75  NATIVE */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_LOW,
+	.gpio68 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+		.invert    = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+
+#endif
diff --git a/src/mainboard/intel/baskingridge/hda_verb.h b/src/mainboard/intel/baskingridge/hda_verb.h
new file mode 100644
index 0000000..9a4a740
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/hda_verb.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10134210,	// Codec Vendor / Device ID: Cirrus Logic CS4210
+	0x10134210,	// Subsystem ID
+	0x00000007,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
+	0x00172010,
+	0x00172142,
+	0x00172213,
+	0x00172310,
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x05)     1/8   Gray  HP Out at Ext Front */
+	0x00571cf0,
+	0x00571d20,
+	0x00571e21,
+	0x00571f02,
+
+	/* Pin Complex (NID 0x06)  Analog Unknown  Speaker at Int N/A */
+	0x00671c10,
+	0x00671d00,
+	0x00671e17,
+	0x00671f90,
+
+	/* Pin Complex (NID 0x07)     1/8    Grey  Line In at Ext Front */
+	0x00771cf0,
+	0x00771d20,
+	0x00771ea1,
+	0x00771f02,
+
+	/* Pin Complex (NID 0x08)  Analog Unknown  Mic at Oth Mobile-In */
+	0x00871c37,
+	0x00871d00,
+	0x00871ea7,
+	0x00871f77,
+
+	/* Pin Complex (NID 0x09) Digital Unknown  Mic at Oth Mobile-In */
+	0x00971c3e,
+	0x00971d00,
+	0x00971ea6,
+	0x00971f77,
+
+	/* Pin Complex (NID 0x0a) Optical   Black  SPDIF Out at Ext N/A */
+	0x00a71cf0,
+	0x00a71d10,
+	0x00a71e45,
+	0x00a71f43,
+
+	/* coreboot specific header */
+	0x80862805,	// Codec Vendor / Device ID: Intel CougarPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	0x00172001,
+	0x00172101,
+	0x00172286,
+	0x00172380,
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	0x30571c10,
+	0x30571d00,
+	0x30571e56,
+	0x30571f18,
+
+	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+	0x30671c20,
+	0x30671d00,
+	0x30671e56,
+	0x30671f18,
+
+	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+	0x30771c30,
+	0x30771d00,
+	0x30771e56,
+	0x30771f18
+};
+
diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c
new file mode 100644
index 0000000..8ac538b
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/mainboard.c
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+			__func__, regs->eax & 0xffff);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffffff00;
+		regs->ecx |= 0x01;
+		res = 0;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP) *
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP) *
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0000;
+		res = 0;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0003;
+		res = 0;
+		break;
+	case 0x5f70:
+		switch ((regs->ecx >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((regs->ecx >> 8) & 0xff));
+			return 0;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0001;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP) *
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP) *
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 3;
+		break;
+	case 0x5f70:
+		/* Unknown */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0;
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+			M.x86.R_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+	verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Compal Link ChromeBox")
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c
new file mode 100644
index 0000000..ecfc385
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/mainboard_smi.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/lynxpoint/nvs.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/lynxpoint/me.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <cpu/intel/haswell/haswell.h>
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		smm_get_gnvs()->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+/*
+ * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
+ * The IO address is hardcoded as we don't have device path in SMM.
+ */
+#define SIO_GPIO_BASE_SET4	(0x730 + 3)
+#define SIO_GPIO_BLINK_GPIO45	0x25
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	u8 reg8;
+
+	switch (slp_typ) {
+	case SLP_TYP_S3:
+	case SLP_TYP_S4:
+		break;
+
+	case SLP_TYP_S5:
+		/* Turn off LED */
+		reg8 = inb(SIO_GPIO_BASE_SET4);
+		reg8 |= (1 << 5);
+		outb(reg8, SIO_GPIO_BASE_SET4);
+		break;
+	}
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	switch (apmc) {
+	case APMC_FINALIZE:
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+			return 0;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_northbridge_haswell_finalize_smm();
+		intel_cpu_haswell_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	}
+	return 0;
+}
diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h
new file mode 100644
index 0000000..52f53e0
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/onboard.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_ONBOARD_H
+#define LUMPY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define LUMPY_LIGHTSENSOR_NAME      "lightsensor"
+#define LUMPY_LIGHTSENSOR_I2C_ADDR  0x44
+#define LUMPY_LIGHTSENSOR_GSI       20
+#define LUMPY_LIGHTSENSOR_IRQ       14
+#define LUMPY_LIGHTSENSOR_IRQ_MODE  (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
+
+#define LUMPY_TRACKPAD_NAME         "trackpad"
+#define LUMPY_TRACKPAD_I2C_ADDR     0x67
+#define LUMPY_TRACKPAD_GSI          21
+#define LUMPY_TRACKPAD_IRQ          15
+#define LUMPY_TRACKPAD_IRQ_MODE     (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
+
+#endif
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
new file mode 100644
index 0000000..2a8e910
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -0,0 +1,318 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/haswell/haswell.h"
+#include "northbridge/intel/haswell/raminit.h"
+#include "southbridge/intel/lynxpoint/pch.h"
+#include "southbridge/intel/lynxpoint/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
+static void pch_enable_lpc(void)
+{
+	device_t dev = PCH_LPC_DEV;
+
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+
+	/* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */
+	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN;
+	pci_write_config16(dev, LPC_EN, lpc_config);
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA16(OIC) = 0x0100;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA16(OIC);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	RCBA32(FD) = reg32;
+}
+
+// FIXME, this function is generic code that should go to sb/... or
+// nb/../early_init.c
+static void early_pch_init(void)
+{
+	u8 reg8;
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+	struct pei_data pei_data = {
+		pei_version: PEI_VERSION,
+		mchbar: DEFAULT_MCHBAR,
+		dmibar: DEFAULT_DMIBAR,
+		epbar: DEFAULT_EPBAR,
+		pciexbar: DEFAULT_PCIEXBAR,
+		smbusbar: SMBUS_IO_BASE,
+		wdbbar: 0x4000000,
+		wdbsize: 0x1000,
+		hpet_address: HPET_ADDR,
+		rcba: DEFAULT_RCBA,
+		pmbase: DEFAULT_PMBASE,
+		gpiobase: DEFAULT_GPIOBASE,
+		temp_mmio_base: 0xfed08000,
+		system_type: 0, // 0 Mobile, 1 Desktop/Server
+		tseg_size: CONFIG_SMM_TSEG_SIZE,
+		spd_addresses: { 0xa0, 0xa2, 0xa4, 0xa6 },
+		ec_present: 0,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		dimm_channel0_disabled: 0,
+		dimm_channel1_disabled: 0,
+		max_ddr3_freq: 1600,
+		usb_port_config: {
+			{ 1, 0, 0x0040 }, /* P0: Back USB3 port  (OC0) */
+			{ 1, 0, 0x0040 }, /* P1: Back USB3 port  (OC0) */
+			{ 1, 1, 0x0040 }, /* P2: Flex Port on bottom (OC1) */
+			{ 1, 8, 0x0040 }, /* P3: Docking connector (no OC) */
+			{ 1, 8, 0x0040 }, /* P4: Mini PCIE (no OC) */
+			{ 1, 1, 0x0040 }, /* P5: USB eSATA header (OC1) */
+			{ 1, 3, 0x0040 }, /* P6: Front Header J8H2 (OC3) */
+			{ 1, 3, 0x0040 }, /* P7: Front Header J8H2 (OC3) */
+			{ 1, 4, 0x0040 }, /* P8: USB/LAN Jack (OC4) */
+			{ 1, 4, 0x0040 }, /* P9: USB/LAN Jack (OC4) */
+			{ 1, 5, 0x0040 }, /* P10: Front Header J7H3 (OC5) */
+			{ 1, 5, 0x0040 }, /* P11: Front Header J7H3 (OC5) */
+			{ 1, 6, 0x0040 }, /* P12: USB/DP Jack (OC6) */
+			{ 1, 6, 0x0040 }, /* P13: USB/DP Jack (OC6) */
+		},
+	};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&mainboard_gpio_map);
+
+	/* Early Console setup */
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	/*
+	 * FIXME: MCHBAR isn't setup yet. It's setup in
+	 * haswell_early_initialization().
+	 */
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		while (1) {
+			hlt();
+		}
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	haswell_early_initialization(HASWELL_MOBILE);
+	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2)
+		enable_usb_bar();
+
+	post_code(0x3a);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3b);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3c);
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+	post_code(0x3d);
+
+	quick_ram_check();
+	post_code(0x3e);
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+	cbmem_was_initted = !cbmem_initialize();
+#else
+	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+						     - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		while (1) {
+			hlt();
+		}
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_CHROMEOS
+	init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/intel/baskingridge/thermal.h b/src/mainboard/intel/baskingridge/thermal.h
new file mode 100644
index 0000000..d8c0025
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/thermal.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BASKING_RIDGE_THERMAL_H
+#define BASKING_RIDGE_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF	0
+#define FAN4_THRESHOLD_ON	0
+#define FAN4_PWM		0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	48
+#define FAN3_THRESHOLD_ON	55
+#define FAN3_PWM		0x40
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	52
+#define FAN2_THRESHOLD_ON	64
+#define FAN2_PWM		0x80
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	60
+#define FAN1_THRESHOLD_ON	68
+#define FAN1_PWM		0xb0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	66
+#define FAN0_THRESHOLD_ON	78
+#define FAN0_PWM		0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		100
+
+#endif
diff --git a/src/mainboard/intel/graysreef/Kconfig b/src/mainboard/intel/graysreef/Kconfig
deleted file mode 100644
index 52f859d..0000000
--- a/src/mainboard/intel/graysreef/Kconfig
+++ /dev/null
@@ -1,45 +0,0 @@
-if BOARD_INTEL_GRAYSREEF
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select ARCH_X86
-	select CPU_INTEL_SOCKET_RPGA989
-	select NORTHBRIDGE_INTEL_HASWELL
-	select SOUTHBRIDGE_INTEL_LYNXPOINT
-	select BOARD_ROMSIZE_KB_8192
-	select BOARD_HAS_FADT
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_RESUME
-	select HAVE_MAINBOARD_RESOURCES
-	select MMCONF_SUPPORT
-	select HAVE_SMI_HANDLER
-	select GFXUMA
-	select CHROMEOS
-	select EXTERNAL_MRC_BLOB
-
-config MAINBOARD_DIR
-	string
-	default intel/graysreef
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "GRAYS REEF"
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xf0000000
-
-config IRQ_SLOT_COUNT
-	int
-	default 18
-
-config MAX_CPUS
-	int
-	default 16
-
-config VGA_BIOS_FILE
-	string
-	default "pci8086,0166.rom"
-
-endif # BOARD_INTEL_GRAYSREEF
diff --git a/src/mainboard/intel/graysreef/Makefile.inc b/src/mainboard/intel/graysreef/Makefile.inc
deleted file mode 100644
index 80385d6..0000000
--- a/src/mainboard/intel/graysreef/Makefile.inc
+++ /dev/null
@@ -1,23 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-romstage-$(CONFIG_CHROMEOS) += chromeos.c
-ramstage-$(CONFIG_CHROMEOS) += chromeos.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/intel/graysreef/acpi/chromeos.asl b/src/mainboard/intel/graysreef/acpi/chromeos.asl
deleted file mode 100644
index 307e2e2..0000000
--- a/src/mainboard/intel/graysreef/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
-	Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
-	Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/graysreef/acpi/ec.asl b/src/mainboard/intel/graysreef/acpi/ec.asl
deleted file mode 100644
index e69de29..0000000
diff --git a/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl
deleted file mode 100644
index 6f2d3e9..0000000
--- a/src/mainboard/intel/graysreef/acpi/haswell_pci_irqs.asl
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* This is board specific information: IRQ routing for IvyBridge */
-
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 22 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 17 },
-			Package() { 0x001cffff, 1, 0, 18 },
-			Package() { 0x001cffff, 2, 0, 19 },
-			Package() { 0x001cffff, 3, 0, 20 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, 0, 19 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, 0, 20 },
-			// LPC devices			0:1f.0
-			Package() { 0x001fffff, 0, 0, 21 },
-			Package() { 0x001fffff, 1, 0, 22 },
-			Package() { 0x001fffff, 2, 0, 23 },
-			Package() { 0x001fffff, 3, 0, 16 },
-		})
-	} Else {
-		Return (Package() {
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
-			// EHCI	#1			0:1d.0
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			// EHCI	#2			0:1a.0
-			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
-		})
-	}
-}
-
diff --git a/src/mainboard/intel/graysreef/acpi/mainboard.asl b/src/mainboard/intel/graysreef/acpi/mainboard.asl
deleted file mode 100644
index 6b15331..0000000
--- a/src/mainboard/intel/graysreef/acpi/mainboard.asl
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-
-	// Wake
-	Name(_PRW, Package(){0x1d, 0x05})
-}
diff --git a/src/mainboard/intel/graysreef/acpi/platform.asl b/src/mainboard/intel/graysreef/acpi/platform.asl
deleted file mode 100644
index fea92d0..0000000
--- a/src/mainboard/intel/graysreef/acpi/platform.asl
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* The APM port can be used for generating software SMIs */
-
-OperationRegion (APMP, SystemIO, 0xb2, 2)
-Field (APMP, ByteAcc, NoLock, Preserve)
-{
-	APMC, 8,	// APM command
-	APMS, 8		// APM status
-}
-
-/* Port 80 POST */
-
-OperationRegion (POST, SystemIO, 0x80, 1)
-Field (POST, ByteAcc, Lock, Preserve)
-{
-	DBG0, 8
-}
-
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
-	Store (Arg0, SMIF)	// SMI Function
-	Store (0, TRP0)		// Generate trap
-	Return (SMIF)		// Return value of SMI handler
-}
-
-/* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
-Method(_PIC, 1)
-{
-	// Remember the OS' IRQ routing choice.
-	Store(Arg0, PICM)
-}
-
-/* The _PTS method (Prepare To Sleep) is called before the OS is
- * entering a sleep state. The sleep state number is passed in Arg0
- */
-
-Method(_PTS,1)
-{
-	// NVS has a flag to determine USB policy in S3
-	if (S3U0) {
-		Store (One, GP47)   // Enable USB0
-	} Else {
-		Store (Zero, GP47)  // Disable USB0
-	}
-
-	// NVS has a flag to determine USB policy in S3
-	if (S3U1) {
-		Store (One, GP56)   // Enable USB1
-	} Else {
-		Store (Zero, GP56)  // Disable USB1
-	}
-}
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
-
diff --git a/src/mainboard/intel/graysreef/acpi/superio.asl b/src/mainboard/intel/graysreef/acpi/superio.asl
deleted file mode 100644
index a50c4b3..0000000
--- a/src/mainboard/intel/graysreef/acpi/superio.asl
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Values should match those defined in devicetree.cb */
-
-#undef SIO_ENABLE_FDC0           // pnp 2e.0: Disable Floppy Controller
-#undef SIO_ENABLE_INFR           // pnp 2e.a: Disable Consumer IR
-
-#define SIO_ENABLE_PS2K          // pnp 2e.5: Enable PS/2 Keyboard
-#define SIO_ENABLE_PS2M          // pnp 2e.6: Enable PS/2 Mouse
-#define SIO_ENABLE_COM1          // pnp 2e.1: Enable Serial Port 1
-#define SIO_ENABLE_ENVC          // pnp 2e.4: Enable Environmental Controller
-#define SIO_ENVC_IO0      0x700  // pnp 2e.4: io 0x60
-#define SIO_ENVC_IO1      0x710  // pnp 2e.4: io 0x62
-#define SIO_ENABLE_GPIO	  	 // pnp 2e.7: Enable GPIO
-#define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
-#define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
-
-#include "superio/smsc/sio1007/acpi/superio.asl"
diff --git a/src/mainboard/intel/graysreef/acpi/thermal.asl b/src/mainboard/intel/graysreef/acpi/thermal.asl
deleted file mode 100644
index f8e9d97..0000000
--- a/src/mainboard/intel/graysreef/acpi/thermal.asl
+++ /dev/null
@@ -1,275 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// Thermal Zone
-
-Scope (\_TZ)
-{
-	ThermalZone (THRM)
-	{
-		Name (_TC1, 0x02)
-		Name (_TC2, 0x05)
-
-		// Thermal zone polling frequency: 0 seconds
-		Name (_TZP, 0)
-
-		// Thermal sampling period for passive cooling: 2 seconds
-		Name (_TSP, 20)
-
-		// Convert from Degrees C to 1/10 Kelvin for ACPI
-		Method (CTOK, 1) {
-			// 10th of Degrees C
-			Multiply (Arg0, 10, Local0)
-
-			// Convert to Kelvin
-			Add (Local0, 2732, Local0)
-
-			Return (Local0)
-		}
-
-		// Threshold for OS to shutdown
-		Method (_CRT, 0, Serialized)
-		{
-			Return (CTOK (\TCRT))
-		}
-
-		// Threshold for passive cooling
-		Method (_PSV, 0, Serialized)
-		{
-			Return (CTOK (\TPSV))
-		}
-
-		// Processors used for passive cooling
-		Method (_PSL, 0, Serialized)
-		{
-			Return (\PPKG ())
-		}
-
-		Method (_TMP, 0, Serialized)
-		{
-			// Get CPU Temperature from PECI via SuperIO TMPIN3
-			// FIXME: figure out how to read temp on this board.
-			Store (30, Local0)
-
-			// Check for invalid readings
-			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
-				Return (CTOK (\F2ON))
-			}
-
-			// PECI raw value is an offset from Tj_max
-			Subtract (255, Local0, Local1)
-
-			// Handle values greater than Tj_max
-			If (LGreaterEqual (Local1, \TMAX)) {
-				Return (CTOK (\TMAX))
-			}
-
-			// Subtract from Tj_max to get temperature
-			Subtract (\TMAX, Local1, Local0)
-			Return (CTOK (Local0))
-		}
-
-		Method (_AC0) {
-			If (LLessEqual (\FLVL, 0)) {
-				Return (CTOK (\F0OF))
-			} Else {
-				Return (CTOK (\F0ON))
-			}
-		}
-
-		Method (_AC1) {
-			If (LLessEqual (\FLVL, 1)) {
-				Return (CTOK (\F1OF))
-			} Else {
-				Return (CTOK (\F1ON))
-			}
-		}
-
-		Method (_AC2) {
-			If (LLessEqual (\FLVL, 2)) {
-				Return (CTOK (\F2OF))
-			} Else {
-				Return (CTOK (\F2ON))
-			}
-		}
-
-		Method (_AC3) {
-			If (LLessEqual (\FLVL, 3)) {
-				Return (CTOK (\F3OF))
-			} Else {
-				Return (CTOK (\F3ON))
-			}
-		}
-
-		Method (_AC4) {
-			If (LLessEqual (\FLVL, 4)) {
-				Return (CTOK (\F4OF))
-			} Else {
-				Return (CTOK (\F4ON))
-			}
-		}
-
-		Name (_AL0, Package () { FAN0 })
-		Name (_AL1, Package () { FAN1 })
-		Name (_AL2, Package () { FAN2 })
-		Name (_AL3, Package () { FAN3 })
-		Name (_AL4, Package () { FAN4 })
-
-		PowerResource (FNP0, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 0)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (0, \FLVL)
-				Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (1, \FLVL)
-				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP1, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 1)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (1, \FLVL)
-				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (2, \FLVL)
-				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP2, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 2)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (2, \FLVL)
-				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (3, \FLVL)
-				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP3, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 3)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (3, \FLVL)
-				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (4, \FLVL)
-				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		PowerResource (FNP4, 0, 0)
-		{
-			Method (_STA) {
-				If (LLessEqual (\FLVL, 4)) {
-					Return (One)
-				} Else {
-					Return (Zero)
-				}
-			}
-			Method (_ON)  {
-				Store (4, \FLVL)
-				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-			Method (_OFF) {
-				Store (4, \FLVL)
-				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
-				Notify (\_TZ.THRM, 0x81)
-			}
-		}
-
-		Device (FAN0)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 0)
-			Name (_PR0, Package () { FNP0 })
-		}
-
-		Device (FAN1)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 1)
-			Name (_PR0, Package () { FNP1 })
-		}
-
-		Device (FAN2)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 2)
-			Name (_PR0, Package () { FNP2 })
-		}
-
-		Device (FAN3)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 3)
-			Name (_PR0, Package () { FNP3 })
-		}
-
-		Device (FAN4)
-		{
-			Name (_HID, EISAID ("PNP0C0B"))
-			Name (_UID, 4)
-			Name (_PR0, Package () { FNP4 })
-		}
-	}
-}
-
diff --git a/src/mainboard/intel/graysreef/acpi/video.asl b/src/mainboard/intel/graysreef/acpi/video.asl
deleted file mode 100644
index 3ececa9..0000000
--- a/src/mainboard/intel/graysreef/acpi/video.asl
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-// Brightness write
-Method (BRTW, 1, Serialized)
-{
-	// TODO
-}
-
-// Hot Key Display Switch
-Method (HKDS, 1, Serialized)
-{
-	// TODO
-}
-
-// Lid Switch Display Switch
-Method (LSDS, 1, Serialized)
-{
-	// TODO
-}
-
-// Brightness Notification
-Method(BRTN,1,Serialized)
-{
-	// TODO (no displays defined yet)
-}
-
diff --git a/src/mainboard/intel/graysreef/acpi_tables.c b/src/mainboard/intel/graysreef/acpi_tables.c
deleted file mode 100644
index 823abcf..0000000
--- a/src/mainboard/intel/graysreef/acpi_tables.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-extern const unsigned char AmlCode[];
-#if CONFIG_HAVE_ACPI_SLIC
-unsigned long acpi_create_slic(unsigned long current);
-#endif
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include "thermal.h"
-
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
-	gnvs->f4of = FAN4_THRESHOLD_OFF;
-	gnvs->f4on = FAN4_THRESHOLD_ON;
-	gnvs->f4pw = FAN4_PWM;
-
-	gnvs->f3of = FAN3_THRESHOLD_OFF;
-	gnvs->f3on = FAN3_THRESHOLD_ON;
-	gnvs->f3pw = FAN3_PWM;
-
-	gnvs->f2of = FAN2_THRESHOLD_OFF;
-	gnvs->f2on = FAN2_THRESHOLD_ON;
-	gnvs->f2pw = FAN2_PWM;
-
-	gnvs->f1of = FAN1_THRESHOLD_OFF;
-	gnvs->f1on = FAN1_THRESHOLD_ON;
-	gnvs->f1pw = FAN1_PWM;
-
-	gnvs->f0of = FAN0_THRESHOLD_OFF;
-	gnvs->f0on = FAN0_THRESHOLD_ON;
-	gnvs->f0pw = FAN0_PWM;
-
-	gnvs->tcrt = CRITICAL_TEMPERATURE;
-	gnvs->tpsv = PASSIVE_TEMPERATURE;
-	gnvs->tmax = MAX_TEMPERATURE;
-}
-
-static void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	memset((void *)gnvs, 0, sizeof(*gnvs));
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
-
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/*
-	 * Enable Front USB ports in S5 by default
-	 * to be consistent with back port behavior
-	 */
-	gnvs->s5u0 = 1;
-	gnvs->s5u1 = 1;
-
-	/* CBMEM TOC */
-	gnvs->cmem = (u32)get_cbmem_toc();
-
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
-#if CONFIG_CHROMEOS
-	// TODO(reinauer) this could move elsewhere?
-	chromeos_init_vboot(&(gnvs->chromeos));
-	/* Emerald Lake has no EC (?) */
-	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
-#endif
-
-	acpi_update_thermal_table(gnvs);
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
-
-unsigned long acpi_fill_ssdt_generator(unsigned long current,
-					const char *oem_table_id)
-{
-	generate_cpu_entries();
-	return (unsigned long) (acpigen_get_current());
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
-	// Not implemented
-	return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
-	/* No NUMA, no SRAT */
-	return current;
-}
-
-#define ALIGN_CURRENT current = (ALIGN(current, 16))
-unsigned long write_acpi_tables(unsigned long start)
-{
-	unsigned long current;
-	int i;
-	acpi_rsdp_t *rsdp;
-	acpi_rsdt_t *rsdt;
-	acpi_xsdt_t *xsdt;
-	acpi_hpet_t *hpet;
-	acpi_madt_t *madt;
-	acpi_mcfg_t *mcfg;
-	acpi_fadt_t *fadt;
-	acpi_facs_t *facs;
-#if CONFIG_HAVE_ACPI_SLIC
-	acpi_header_t *slic;
-#endif
-	acpi_header_t *ssdt;
-	acpi_header_t *dsdt;
-
-	current = start;
-
-	/* Align ACPI tables to 16byte */
-	ALIGN_CURRENT;
-
-	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
-
-	/* We need at least an RSDP and an RSDT Table */
-	rsdp = (acpi_rsdp_t *) current;
-	current += sizeof(acpi_rsdp_t);
-	ALIGN_CURRENT;
-	rsdt = (acpi_rsdt_t *) current;
-	current += sizeof(acpi_rsdt_t);
-	ALIGN_CURRENT;
-	xsdt = (acpi_xsdt_t *) current;
-	current += sizeof(acpi_xsdt_t);
-	ALIGN_CURRENT;
-
-	/* clear all table memory */
-	memset((void *) start, 0, current - start);
-
-	acpi_write_rsdp(rsdp, rsdt, xsdt);
-	acpi_write_rsdt(rsdt);
-	acpi_write_xsdt(xsdt);
-
-	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
-	facs = (acpi_facs_t *) current;
-	current += sizeof(acpi_facs_t);
-	ALIGN_CURRENT;
-	acpi_create_facs(facs);
-
-	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *) current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-	ALIGN_CURRENT;
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
-
-	/*
-	 * We explicitly add these tables later on:
-	 */
-	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
-
-	hpet = (acpi_hpet_t *) current;
-	current += sizeof(acpi_hpet_t);
-	ALIGN_CURRENT;
-	acpi_create_intel_hpet(hpet);
-	acpi_add_table(rsdp, hpet);
-
-	/* If we want to use HPET Timers Linux wants an MADT */
-	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
-
-	madt = (acpi_madt_t *) current;
-	acpi_create_madt(madt);
-	current += madt->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, madt);
-
-	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
-	mcfg = (acpi_mcfg_t *) current;
-	acpi_create_mcfg(mcfg);
-	current += mcfg->header.length;
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, mcfg);
-
-	/* Pack GNVS into the ACPI table area */
-	for (i=0; i < dsdt->length; i++) {
-		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
-			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
-			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
-			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
-			acpi_save_gnvs(current);
-			break;
-		}
-	}
-
-	/* And fill it */
-	acpi_create_gnvs((global_nvs_t *)current);
-
-	/* And tell SMI about it */
-	smm_setup_structures((void *)current, NULL, NULL);
-
-	current += sizeof(global_nvs_t);
-	ALIGN_CURRENT;
-
-	/* We patched up the DSDT, so we need to recalculate the checksum */
-	dsdt->checksum = 0;
-	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
-
-	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
-		     dsdt->length);
-
-#if CONFIG_HAVE_ACPI_SLIC
-	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
-	slic = (acpi_header_t *)current;
-	current += acpi_create_slic(current);
-	ALIGN_CURRENT;
-	acpi_add_table(rsdp, slic);
-#endif
-
-	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	current += ssdt->length;
-	acpi_add_table(rsdp, ssdt);
-	ALIGN_CURRENT;
-
-	printk(BIOS_DEBUG, "current = %lx\n", current);
-	printk(BIOS_INFO, "ACPI: done.\n");
-	return current;
-}
diff --git a/src/mainboard/intel/graysreef/chromeos.c b/src/mainboard/intel/graysreef/chromeos.c
deleted file mode 100644
index 4ee9d62..0000000
--- a/src/mainboard/intel/graysreef/chromeos.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
-#include <device/device.h>
-#include <device/pci.h>
-#endif
-#include <southbridge/intel/lynxpoint/pch.h>
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-#include <arch/coreboot_tables.h>
-
-#define GPIO_COUNT	6
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-
-	if (!gpio_base)
-		return;
-
-	u32 gp_lvl = inl(gpio_base + 0x0c);
-	u32 gp_lvl2 = inl(gpio_base + 0x38);
-	/* u32 gp_lvl3 = inl(gpio_base + 0x48); */
-
-	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
-	gpios->count = GPIO_COUNT;
-
-	/* Write Protect: GPIO48 */
-	gpios->gpios[0].port = 48;
-	gpios->gpios[0].polarity = ACTIVE_LOW;
-	gpios->gpios[0].value = (gp_lvl2 >> (48-32)) & 1;
-	strncpy((char *)gpios->gpios[0].name,"write protect",
-							GPIO_MAX_NAME_LENGTH);
-
-	/* Recovery: GPIO22 */
-	gpios->gpios[1].port = 22;
-	gpios->gpios[1].polarity = ACTIVE_LOW;
-	gpios->gpios[1].value = (gp_lvl >> 22) & 1;
-	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
-
-	/* Developer: GPIO57 */
-	gpios->gpios[2].port = 57;
-	gpios->gpios[2].polarity = ACTIVE_LOW;
-	gpios->gpios[2].value = (gp_lvl2 >> (57-32)) & 1;
-	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
-
-	/* Hard code the lid switch GPIO to open. */
-	gpios->gpios[3].port = -1;
-	gpios->gpios[3].polarity = ACTIVE_HIGH;
-	gpios->gpios[3].value = 1;
-	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
-
-	/* Power Button */
-	gpios->gpios[4].port = -1;
-	gpios->gpios[4].polarity = ACTIVE_HIGH;
-	gpios->gpios[4].value = 0;
-	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
-
-	/* Did we load the VGA option ROM? */
-	gpios->gpios[5].port = -1;
-	gpios->gpios[5].polarity = ACTIVE_HIGH;
-	gpios->gpios[5].value = oprom_is_loaded;
-	strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
-}
-#endif
-
-int get_developer_mode_switch(void)
-{
-	device_t dev;
-#ifdef __PRE_RAM__
-	dev = PCI_DEV(0, 0x1f, 0);
-#else
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-	u32 gp_lvl2 = inl(gpio_base + 0x38);
-
-	/* Developer: GPIO17, active high */
-	return (gp_lvl2 >> (57-32)) & 1;
-}
-
-int get_recovery_mode_switch(void)
-{
-	device_t dev;
-#ifdef __PRE_RAM__
-	dev = PCI_DEV(0, 0x1f, 0);
-#else
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
-	u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
-	u32 gp_lvl = inl(gpio_base + 0x0c);
-
-	/* Recovery: GPIO22, active low */
-	return !((gp_lvl >> 22) & 1);
-}
-
diff --git a/src/mainboard/intel/graysreef/cmos.layout b/src/mainboard/intel/graysreef/cmos.layout
deleted file mode 100644
index e8a088d..0000000
--- a/src/mainboard/intel/graysreef/cmos.layout
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-# -----------------------------------------------------------------
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-# -----------------------------------------------------------------
-# Status Register A
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-# -----------------------------------------------------------------
-# Status Register B
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-385          1       e       4        last_boot
-388          4       r       0        reboot_bits
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-392          3       e       5        baud_rate
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# coreboot config options: bootloader
-#Used by ChromeOS:
-416        128       r        0        vbnv
-#544        440       r       0        unused
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-5     0     115200
-5     1     57600
-5     2     38400
-5     3     19200
-5     4     9600
-5     5     4800
-5     6     2400
-5     7     1200
-6     1     Emergency
-6     2     Alert
-6     3     Critical
-6     4     Error
-6     5     Warning
-6     6     Notice
-6     7     Info
-6     8     Debug
-6     9     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
-
-
diff --git a/src/mainboard/intel/graysreef/devicetree.cb b/src/mainboard/intel/graysreef/devicetree.cb
deleted file mode 100644
index 737de1c..0000000
--- a/src/mainboard/intel/graysreef/devicetree.cb
+++ /dev/null
@@ -1,84 +0,0 @@
-chip northbridge/intel/haswell
-
-	# Enable DisplayPort 1 Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Enable DisplayPort 0 Hotplug with 6ms pulse
-	register "gpu_dp_c_hotplug" = "0x06"
-
-	# Enable DVI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	device cpu_cluster 0 on
-		chip cpu/intel/socket_rPGA989
-			device lapic 0 on end
-		end
-		chip cpu/intel/haswell
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
-
-			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-
-		chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
-			register "pirqa_routing" = "0x8b"
-			register "pirqb_routing" = "0x8a"
-			register "pirqc_routing" = "0x8b"
-			register "pirqd_routing" = "0x8b"
-			register "pirqe_routing" = "0x80"
-			register "pirqf_routing" = "0x80"
-			register "pirqg_routing" = "0x80"
-			register "pirqh_routing" = "0x80"
-
-			# GPI routing
-			#  0 No effect (default)
-			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
-			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi1_routing" = "1"
-			register "gpi14_routing" = "2"
-			register "alt_gp_smi_en" = "0x0002"
-			register "gpe0_en" = "0x4000"
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x3f"
-
-			# SuperIO range is 0x700-0x73f
-			register "gen2_dec" = "0x003c0701"
-
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 19.0 off end # Intel Gigabit Ethernet
-			device pci 1a.0 on end # USB2 EHCI #2
-			device pci 1b.0 on end # High Definition Audio
-			device pci 1c.0 on end # PCIe Port #1 (WLAN)
-			device pci 1c.1 off end # PCIe Port #2
-			device pci 1c.2 on end # PCIe Port #3 (Debug)
-			device pci 1c.3 on end # PCIe Port #4 (LAN)
-			device pci 1c.4 off end # PCIe Port #5
-			device pci 1c.5 off end # PCIe Port #6
-			device pci 1c.6 off end # PCIe Port #7
-			device pci 1c.7 off end # PCIe Port #8
-			device pci 1d.0 on end # USB2 EHCI #1
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on end # LPC bridge
-			device pci 1f.2 on end # SATA Controller 1
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # SATA Controller 2
-			device pci 1f.6 on end # Thermal
-		end
-	end
-end
diff --git a/src/mainboard/intel/graysreef/dsdt.asl b/src/mainboard/intel/graysreef/dsdt.asl
deleted file mode 100644
index 79bb8f3..0000000
--- a/src/mainboard/intel/graysreef/dsdt.asl
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0
-	"COREv4",	// OEM id
-	"COREBOOT",     // OEM table id
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-
-	// General Purpose Events
-	//#include "acpi/gpe.asl"
-
-	#include "acpi/thermal.asl"
-
-	#include "../../../cpu/intel/haswell/acpi/cpu.asl"
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/haswell/acpi/haswell.asl>
-			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
-		}
-	}
-
-	#include "acpi/chromeos.asl"
-	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/intel/graysreef/fadt.c b/src/mainboard/intel/graysreef/fadt.c
deleted file mode 100644
index 315cb58..0000000
--- a/src/mainboard/intel/graysreef/fadt.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-#include <cpu/x86/smm.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
-								0x40) & 0xfffe;
-
-	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
-	memcpy(header->signature, "FACP", 4);
-	header->length = sizeof(acpi_fadt_t);
-	header->revision = 3;
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-	header->asl_compiler_revision = 1;
-
-	fadt->firmware_ctrl = (unsigned long) facs;
-	fadt->dsdt = (unsigned long) dsdt;
-	fadt->model = 1;
-	fadt->preferred_pm_profile = PM_DESKTOP;
-
-	fadt->sci_int = 0x9;
-	fadt->smi_cmd = APM_CNT;
-	fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-	fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-	fadt->s4bios_req = 0x0;
-	fadt->pstate_cnt = 0;
-
-	fadt->pm1a_evt_blk = pmbase;
-	fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
-	fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x20;
-	fadt->gpe1_blk = 0;
-
-	fadt->pm1_evt_len = 4;
-	fadt->pm1_cnt_len = 2;
-	fadt->pm2_cnt_len = 1;
-	fadt->pm_tmr_len = 4;
-	fadt->gpe0_blk_len = 16;
-	fadt->gpe1_blk_len = 0;
-	fadt->gpe1_base = 0;
-	fadt->cst_cnt = 0;
-	fadt->p_lvl2_lat = 1;
-	fadt->p_lvl3_lat = 87;
-	fadt->flush_size = 1024;
-	fadt->flush_stride = 16;
-	fadt->duty_offset = 1;
-	fadt->duty_width = 0;
-	fadt->day_alrm = 0xd;
-	fadt->mon_alrm = 0x00;
-	fadt->century = 0x00;
-	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
-
-	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
-			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
-			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
-			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
-	fadt->reset_reg.space_id = 1;
-	fadt->reset_reg.bit_width = 8;
-	fadt->reset_reg.bit_offset = 0;
-	fadt->reset_reg.resv = 0;
-	fadt->reset_reg.addrl = 0xcf9;
-	fadt->reset_reg.addrh = 0;
-
-	fadt->reset_value = 6;
-	fadt->x_firmware_ctl_l = (unsigned long)facs;
-	fadt->x_firmware_ctl_h = 0;
-	fadt->x_dsdt_l = (unsigned long)dsdt;
-	fadt->x_dsdt_h = 0;
-
-	fadt->x_pm1a_evt_blk.space_id = 1;
-	fadt->x_pm1a_evt_blk.bit_width = 32;
-	fadt->x_pm1a_evt_blk.bit_offset = 0;
-	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = pmbase;
-	fadt->x_pm1a_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_evt_blk.space_id = 1;
-	fadt->x_pm1b_evt_blk.bit_width = 0;
-	fadt->x_pm1b_evt_blk.bit_offset = 0;
-	fadt->x_pm1b_evt_blk.resv = 0;
-	fadt->x_pm1b_evt_blk.addrl = 0x0;
-	fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-	fadt->x_pm1a_cnt_blk.space_id = 1;
-	fadt->x_pm1a_cnt_blk.bit_width = 16;
-	fadt->x_pm1a_cnt_blk.bit_offset = 0;
-	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
-	fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm1b_cnt_blk.space_id = 1;
-	fadt->x_pm1b_cnt_blk.bit_width = 0;
-	fadt->x_pm1b_cnt_blk.bit_offset = 0;
-	fadt->x_pm1b_cnt_blk.resv = 0;
-	fadt->x_pm1b_cnt_blk.addrl = 0x0;
-	fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm2_cnt_blk.space_id = 1;
-	fadt->x_pm2_cnt_blk.bit_width = 8;
-	fadt->x_pm2_cnt_blk.bit_offset = 0;
-	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
-	fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-	fadt->x_pm_tmr_blk.space_id = 1;
-	fadt->x_pm_tmr_blk.bit_width = 32;
-	fadt->x_pm_tmr_blk.bit_offset = 0;
-	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
-	fadt->x_pm_tmr_blk.addrh = 0x0;
-
-	fadt->x_gpe0_blk.space_id = 1;
-	fadt->x_gpe0_blk.bit_width = 64;
-	fadt->x_gpe0_blk.bit_offset = 0;
-	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
-	fadt->x_gpe0_blk.addrh = 0x0;
-
-	fadt->x_gpe1_blk.space_id = 1;
-	fadt->x_gpe1_blk.bit_width = 0;
-	fadt->x_gpe1_blk.bit_offset = 0;
-	fadt->x_gpe1_blk.resv = 0;
-	fadt->x_gpe1_blk.addrl = 0x0;
-	fadt->x_gpe1_blk.addrh = 0x0;
-
-	header->checksum =
-	    acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/intel/graysreef/gpio.h b/src/mainboard/intel/graysreef/gpio.h
deleted file mode 100644
index f5ee547..0000000
--- a/src/mainboard/intel/graysreef/gpio.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef GRAYSREEF_GPIO_H
-#define GRAYSREEF_GPIO_H
-
-#include "southbridge/intel/lynxpoint/gpio.h"
-
-const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,    /* PCH_GPIO0_R -> S_GPIO -> J9F5 */
-	.gpio1 = GPIO_MODE_GPIO,    /* SMC_EXTSMI_N */
-	.gpio2 = GPIO_MODE_GPIO,    /* TP_RSVD_TESTMODE  - float */
-	.gpio3 = GPIO_MODE_NATIVE,  /* PCH_PCI_IRQ_N -> SIO GPIO12/SMI# */
-	.gpio4 = GPIO_MODE_GPIO,    /* EXTTS_SNI_DRV0_PCH  - float */
-	.gpio5 = GPIO_MODE_GPIO,    /* EXTTS_SNI_DRV1_PCH  - float */
-	.gpio6 = GPIO_MODE_GPIO,    /* DGPU_HPD_INTR_N */
-	.gpio7 = GPIO_MODE_GPIO,    /* SMC_RUNTIME_SCI_N */
-	.gpio8 = GPIO_MODE_GPIO,    /* PCH_GPIO8 -> DDR Voltage Select Bit 0 */
-	.gpio9  = GPIO_MODE_NATIVE, /* USB_OC_10_11_R_N */
-	.gpio10 = GPIO_MODE_NATIVE, /* USB_OC_12_13_R_N */
-	.gpio11 = GPIO_MODE_GPIO,   /* PCH_GPIO11 -> HOST_ALERT2_N -> PCIE_RSVD_2_N (3GIO_X1) slot 4 */
-	.gpio12 = GPIO_MODE_GPIO,   /* PM_LANPHY_ENABLE */
-	.gpio13 = GPIO_MODE_NATIVE, /* HDA_DOCK_RST_N */
-	.gpio14 = GPIO_MODE_GPIO,   /* SMC_WAKE_SCI_N (not stuffed) & USB_8_9_PWR */
-	.gpio15 = GPIO_MODE_GPIO,   /* Always GPIO: HOST_ALERT1_R_N -> PCIE_RSV_1_N */
-	.gpio16 = GPIO_MODE_NATIVE, /* SATA_DET4_R_N */
-	.gpio17 = GPIO_MODE_GPIO,   /* DGPU_PWROK */
-	.gpio18 = GPIO_MODE_NATIVE, /* CK_SLOT1_OE_N_R */
-	.gpio19 = GPIO_MODE_GPIO,   /* BBS_BIT0_R - STRAP */
-	.gpio20 = GPIO_MODE_NATIVE, /* CK_SLOT2_OE_N_R */
-	.gpio21 = GPIO_MODE_GPIO,   /* SATA_DET0_R_N -> J9H4 */
-	.gpio22 = GPIO_MODE_GPIO,   /* BIOS_REC -> J8G1 */
-	.gpio23 = GPIO_MODE_NATIVE, /* PCH_DRQ1_N */
-	.gpio24 = GPIO_MODE_GPIO,   /* Always GPIO: PCH_GPIO24_R1 -> DDR Voltage Select Bit 2 */
-	.gpio25 = GPIO_MODE_NATIVE, /* CK_SLOT3_OE_N */
-	.gpio26 = GPIO_MODE_NATIVE, /* CK_SLOT4_OE_N */
-	.gpio27 = GPIO_MODE_GPIO,   /* Always GPIO: PCH_GPIO_27 -> SMC_WAKE_SCI_N & LANWAKE_N */
-	.gpio28 = GPIO_MODE_GPIO,   /* Always GPIO: PLL_ODVR_EN -> PCH_AUDIO_PWR_N */
-	.gpio29 = GPIO_MODE_NATIVE, /* PCH_SLP_WLAN_N */
-	.gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK_R */
-	.gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT_R */
-};
-
-const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio1 = GPIO_DIR_INPUT,
-	.gpio2 = GPIO_DIR_OUTPUT,
-	/* .gpio3 NATIVE */
-	.gpio4 = GPIO_DIR_OUTPUT,
-	.gpio5 = GPIO_DIR_OUTPUT,
-	.gpio6 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_OUTPUT,
-	.gpio9 = GPIO_DIR_INPUT,
-	/* .gpio10  NATIVE */
-	.gpio11 = GPIO_DIR_INPUT,
-	.gpio12 = GPIO_DIR_OUTPUT,
-	/* .gpio13  NATIVE */
-	.gpio14 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_INPUT,
-	/* .gpio16  NATIVE */
-	.gpio17 = GPIO_DIR_INPUT,
-	/* .gpio18  NATIVE */
-	.gpio19 = GPIO_DIR_INPUT,
-	.gpio20 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio22 = GPIO_DIR_INPUT,
-	/* .gpio23  NATIVE */
-	.gpio24 = GPIO_DIR_OUTPUT,
-	/* .gpio25  NATIVE */
-	/* .gpio26  NATIVE */
-	.gpio27 = GPIO_DIR_INPUT,
-	.gpio28 = GPIO_DIR_INPUT,
-	/* .gpio29  NATIVE */
-	/* .gpio30  NATIVE */
-	/* .gpio31  NATIVE */
-};
-
-const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio2 = GPIO_LEVEL_HIGH,
-	.gpio4 = GPIO_LEVEL_HIGH,
-	.gpio5 = GPIO_LEVEL_HIGH,
-	.gpio8 = GPIO_LEVEL_HIGH,
-	.gpio12 = GPIO_LEVEL_LOW,
-	.gpio24 = GPIO_LEVEL_LOW,
-};
-
-const struct pch_gpio_set1 pch_gpio_set1_invert = {
-};
-
-const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio32 = GPIO_MODE_NATIVE, /* Always GPIO on desktop. Mobile Native. PM_CLKRUN_N */
-	.gpio33 = GPIO_MODE_NATIVE, /* HDADOCKEN_R_N */
-	.gpio34 = GPIO_MODE_GPIO,   /* PCH_GPIO34 -> SATA_PWR_EN0_N */
-	.gpio35 = GPIO_MODE_GPIO,   /* SATA_PWR_EN1_R_N  */
-	.gpio36 = GPIO_MODE_NATIVE, /* SATA_ODD_PRSNT_R_N */
-	.gpio37 = GPIO_MODE_NATIVE, /* SATA_ODD_DA_N_R */
-	.gpio38 = GPIO_MODE_GPIO,   /* MFG_MODE */
-	.gpio39 = GPIO_MODE_GPIO,   /* GFX_CRB_DET */
-	.gpio40 = GPIO_MODE_NATIVE, /* USB_OC_2_5_R_N */
-	.gpio41 = GPIO_MODE_GPIO,   /* USB_0_1_PWR */
-	.gpio42 = GPIO_MODE_NATIVE, /* USB_OC_6_7_R_N */
-	.gpio43 = GPIO_MODE_NATIVE, /* USB_OSC_8_9_R_N */
-	.gpio44 = GPIO_MODE_NATIVE, /* CK_SLOT5_OE_N */
-	.gpio45 = GPIO_MODE_NATIVE, /* CK_PCIE_LAN_REQ_N */
-	.gpio46 = GPIO_MODE_GPIO,   /* PCH_GPIO46_R -> DDR Voltage Select Bit 1 */
-	.gpio47 = GPIO_MODE_NATIVE, /* PEGA_CKREQ_N */
-	.gpio48 = GPIO_MODE_GPIO,   /* BIOS_RESP -> J8E6 */
-	.gpio49 = GPIO_MODE_GPIO,   /* PCH_GP_49 -> CRIT_TEMP_REP_N */
-	.gpio50 = GPIO_MODE_GPIO,   /* DGPU_HOLD_RST_N */
-	.gpio51 = GPIO_MODE_GPIO,   /* BBS_BIT1 Strap */
-	.gpio52 = GPIO_MODE_GPIO,   /* DGPU_SELECT_N */
-	.gpio53 = GPIO_MODE_GPIO,   /* DGPU_PWM_SELECT_N -> PEG_JTAG5 */
-	.gpio54 = GPIO_MODE_GPIO,   /* DGPU_PWR_EN_N -> PEG_RSVD5 */
-	.gpio55 = GPIO_MODE_GPIO,   /* STP_A16OVR Strap */
-	.gpio56 = GPIO_MODE_NATIVE, /* MC_CKREQ_N */
-	.gpio57 = GPIO_MODE_GPIO,   /* Always GPIO. NFC_IRQ_R */
-	.gpio58 = GPIO_MODE_NATIVE, /* SML1_CK */
-	.gpio59 = GPIO_MODE_NATIVE, /* USB_OC_0_1_R_N */
-	.gpio60 = GPIO_MODE_GPIO,   /* DRAMRST_CNTRL_PCH */
-	.gpio61 = GPIO_MODE_NATIVE, /* PM_SUS_STAT_N */
-	.gpio62 = GPIO_MODE_NATIVE, /* SUS_CK */
-	.gpio63 = GPIO_MODE_NATIVE, /* SLP_S5_R_N */
-};
-
-const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	/* .gpio32  NATIVE */
-	/* .gpio33  NATIVE */
-	.gpio34 = GPIO_DIR_OUTPUT,
-	.gpio35 = GPIO_DIR_OUTPUT,
-	/* .gpio36  NATIVE */
-	/* .gpio37  NATIVE */
-	.gpio38 = GPIO_DIR_INPUT,
-	.gpio39 = GPIO_DIR_INPUT,
-	/* .gpio40  NATIVE */
-	.gpio41 = GPIO_DIR_OUTPUT,
-	/* .gpio42  NATIVE */
-	/* .gpio43  NATIVE */
-	/* .gpio44  NATIVE */
-	/* .gpio45  NATIVE */
-	.gpio46 = GPIO_DIR_OUTPUT,
-	/* .gpio47  NATIVE */
-	.gpio48 = GPIO_DIR_INPUT,
-	.gpio49 = GPIO_DIR_OUTPUT,
-	.gpio50 = GPIO_DIR_OUTPUT,
-	.gpio51 = GPIO_DIR_OUTPUT,
-	.gpio52 = GPIO_DIR_OUTPUT,
-	.gpio53 = GPIO_DIR_OUTPUT,
-	.gpio54 = GPIO_DIR_OUTPUT,
-	.gpio55 = GPIO_DIR_OUTPUT,
-	/* .gpio56  NATIVE */
-	.gpio57 = GPIO_DIR_INPUT,
-	/* .gpio58  NATIVE */
-	/* .gpio59  NATIVE */
-	.gpio60 = GPIO_DIR_OUTPUT,
-	/* .gpio61  NATIVE */
-	/* .gpio62  NATIVE */
-	/* .gpio63  NATIVE */
-};
-
-const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio34 = GPIO_LEVEL_LOW,
-	.gpio41 = GPIO_LEVEL_HIGH,
-	.gpio35 = GPIO_LEVEL_LOW,
-	.gpio46 = GPIO_LEVEL_HIGH,
-	.gpio49 = GPIO_LEVEL_HIGH,
-	.gpio50 = GPIO_LEVEL_HIGH,
-	.gpio51 = GPIO_LEVEL_LOW,
-	.gpio52 = GPIO_LEVEL_LOW,
-	.gpio53 = GPIO_LEVEL_LOW,
-	.gpio54 = GPIO_LEVEL_LOW,
-	.gpio55 = GPIO_LEVEL_LOW,
-	.gpio60 = GPIO_LEVEL_HIGH,
-};
-
-const struct pch_gpio_set3 pch_gpio_set3_mode = {
-	.gpio64 = GPIO_MODE_NATIVE, /* CK_PCH_SIO_DOCK_R -> TP_CK_PCI_SIO_DOCK */
-	.gpio65 = GPIO_MODE_NATIVE, /* CK_FLEX1 */
-	.gpio66 = GPIO_MODE_GPIO,   /* CK_FLEX2 */
-	.gpio67 = GPIO_MODE_GPIO,   /* DGPU_PRSNT_N -> PEG_RSVD3 */
-	.gpio68 = GPIO_MODE_GPIO,   /* SATA_ODD_PWRGT */
-	.gpio69 = GPIO_MODE_GPIO,   /* SV_DET -> J8E5 */
-	.gpio70 = GPIO_MODE_GPIO,   /* USB3_DET_P2_N */
-	.gpio71 = GPIO_MODE_GPIO,   /* USB3_DET_P3_N */
-	.gpio72 = GPIO_MODE_NATIVE, /* PM_BATLOW_R_N */
-	.gpio73 = GPIO_MODE_NATIVE, /* CK_REQ_DOCK_N */
-	.gpio74 = GPIO_MODE_NATIVE, /* PCH_GPIO74_R -> AMB_THM2_R_N (PCHHOT) */
-	.gpio75 = GPIO_MODE_NATIVE, /* SM1_DATA */
-};
-
-const struct pch_gpio_set3 pch_gpio_set3_direction = {
-	.gpio64 = GPIO_DIR_OUTPUT,
-	/* .gpio65  NATIVE */
-	.gpio66 = GPIO_DIR_OUTPUT,
-	.gpio67 = GPIO_DIR_INPUT,
-	.gpio68 = GPIO_DIR_OUTPUT,
-	.gpio69 = GPIO_DIR_INPUT,
-	.gpio70 = GPIO_DIR_INPUT,
-	.gpio71 = GPIO_DIR_INPUT,
-	/* .gpio72  NATIVE */
-	/* .gpio73  NATIVE */
-	/* .gpio74  NATIVE */
-	/* .gpio75  NATIVE */
-};
-
-const struct pch_gpio_set3 pch_gpio_set3_level = {
-	.gpio64 = GPIO_LEVEL_LOW,
-	.gpio66 = GPIO_LEVEL_LOW,
-	.gpio68 = GPIO_LEVEL_HIGH,
-};
-
-const struct pch_gpio_map graysreef_gpio_map = {
-	.set1 = {
-		.mode      = &pch_gpio_set1_mode,
-		.direction = &pch_gpio_set1_direction,
-		.level     = &pch_gpio_set1_level,
-		.invert    = &pch_gpio_set1_invert,
-	},
-	.set2 = {
-		.mode      = &pch_gpio_set2_mode,
-		.direction = &pch_gpio_set2_direction,
-		.level     = &pch_gpio_set2_level,
-	},
-	.set3 = {
-		.mode      = &pch_gpio_set3_mode,
-		.direction = &pch_gpio_set3_direction,
-		.level     = &pch_gpio_set3_level,
-	},
-};
-
-#endif
diff --git a/src/mainboard/intel/graysreef/hda_verb.h b/src/mainboard/intel/graysreef/hda_verb.h
deleted file mode 100644
index 9a4a740..0000000
--- a/src/mainboard/intel/graysreef/hda_verb.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static const u32 mainboard_cim_verb_data[] = {
-	/* coreboot specific header */
-	0x10134210,	// Codec Vendor / Device ID: Cirrus Logic CS4210
-	0x10134210,	// Subsystem ID
-	0x00000007,	// Number of jacks
-
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
-	0x00172010,
-	0x00172142,
-	0x00172213,
-	0x00172310,
-
-	/* Pin Widget Verb Table */
-
-	/* Pin Complex (NID 0x05)     1/8   Gray  HP Out at Ext Front */
-	0x00571cf0,
-	0x00571d20,
-	0x00571e21,
-	0x00571f02,
-
-	/* Pin Complex (NID 0x06)  Analog Unknown  Speaker at Int N/A */
-	0x00671c10,
-	0x00671d00,
-	0x00671e17,
-	0x00671f90,
-
-	/* Pin Complex (NID 0x07)     1/8    Grey  Line In at Ext Front */
-	0x00771cf0,
-	0x00771d20,
-	0x00771ea1,
-	0x00771f02,
-
-	/* Pin Complex (NID 0x08)  Analog Unknown  Mic at Oth Mobile-In */
-	0x00871c37,
-	0x00871d00,
-	0x00871ea7,
-	0x00871f77,
-
-	/* Pin Complex (NID 0x09) Digital Unknown  Mic at Oth Mobile-In */
-	0x00971c3e,
-	0x00971d00,
-	0x00971ea6,
-	0x00971f77,
-
-	/* Pin Complex (NID 0x0a) Optical   Black  SPDIF Out at Ext N/A */
-	0x00a71cf0,
-	0x00a71d10,
-	0x00a71e45,
-	0x00a71f43,
-
-	/* coreboot specific header */
-	0x80862805,	// Codec Vendor / Device ID: Intel CougarPoint HDMI
-	0x80860101,	// Subsystem ID
-	0x00000004,	// Number of jacks
-
-	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
-	0x00172001,
-	0x00172101,
-	0x00172286,
-	0x00172380,
-
-	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
-	0x30571c10,
-	0x30571d00,
-	0x30571e56,
-	0x30571f18,
-
-	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
-	0x30671c20,
-	0x30671d00,
-	0x30671e56,
-	0x30671f18,
-
-	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
-	0x30771c30,
-	0x30771d00,
-	0x30771e56,
-	0x30771f18
-};
-
diff --git a/src/mainboard/intel/graysreef/mainboard.c b/src/mainboard/intel/graysreef/mainboard.c
deleted file mode 100644
index 8ac538b..0000000
--- a/src/mainboard/intel/graysreef/mainboard.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <console/console.h>
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-#include <x86emu/x86emu.h>
-#endif
-#include <pc80/mc146818rtc.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-#include <arch/coreboot_tables.h>
-#include "hda_verb.h"
-#include <southbridge/intel/lynxpoint/pch.h>
-
-void mainboard_suspend_resume(void)
-{
-	/* Call SMM finalize() handlers before resume */
-	outb(0xcb, 0xb2);
-}
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static int int15_handler(struct eregs *regs)
-{
-	int res=-1;
-
-	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
-			__func__, regs->eax & 0xffff);
-
-	switch(regs->eax & 0xffff) {
-	case 0x5f34:
-		/*
-		 * Set Panel Fitting Hook:
-		 *  bit 2 = Graphics Stretching
-		 *  bit 1 = Text Stretching
-		 *  bit 0 = Centering (do not set with bit1 or bit2)
-		 *  0     = video bios default
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffffff00;
-		regs->ecx |= 0x01;
-		res = 0;
-		break;
-	case 0x5f35:
-		/*
-		 * Boot Display Device Hook:
-		 *  bit 0 = CRT
-		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
-		 *  bit 3 = LFP
-		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
-		 *  bit 6 = EFP2 *
-		 *  bit 7 = LFP2
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffff0000;
-		regs->ecx |= 0x0000;
-		res = 0;
-		break;
-	case 0x5f51:
-		/*
-		 * Hook to select active LFP configuration:
-		 *  00h = No LVDS, VBIOS does not enable LVDS
-		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
-		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
-		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
-		 */
-		regs->eax &= 0xffff0000;
-		regs->eax |= 0x005f;
-		regs->ecx &= 0xffff0000;
-		regs->ecx |= 0x0003;
-		res = 0;
-		break;
-	case 0x5f70:
-		switch ((regs->ecx >> 8) & 0xff) {
-		case 0:
-			/* Get Mux */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		case 1:
-			/* Set Mux */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		case 2:
-			/* Get SG/Non-SG mode */
-			regs->eax &= 0xffff0000;
-			regs->eax |= 0x005f;
-			regs->ecx &= 0xffff0000;
-			regs->ecx |= 0x0000;
-			res = 0;
-			break;
-		default:
-			/* Interrupt was not handled */
-			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
-				((regs->ecx >> 8) & 0xff));
-			return 0;
-		}
-		break;
-
-        default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-#endif
-
-#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
-static int int15_handler(void)
-{
-	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
-			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
-
-	switch (M.x86.R_AX) {
-	case 0x5f34:
-		/*
-		 * Set Panel Fitting Hook:
-		 *  bit 2 = Graphics Stretching
-		 *  bit 1 = Text Stretching
-		 *  bit 0 = Centering (do not set with bit1 or bit2)
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0x0001;
-		break;
-	case 0x5f35:
-		/*
-		 * Boot Display Device Hook:
-		 *  bit 0 = CRT
-		 *  bit 1 = TV (eDP) *
-		 *  bit 2 = EFP *
-		 *  bit 3 = LFP
-		 *  bit 4 = CRT2
-		 *  bit 5 = TV2 (eDP) *
-		 *  bit 6 = EFP2 *
-		 *  bit 7 = LFP2
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0x0000;
-		break;
-	case 0x5f51:
-		/*
-		 * Hook to select active LFP configuration:
-		 *  00h = No LVDS, VBIOS does not enable LVDS
-		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
-		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
-		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
-		 */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 3;
-		break;
-	case 0x5f70:
-		/* Unknown */
-		M.x86.R_AX = 0x005f;
-		M.x86.R_CX = 0;
-		break;
-	default:
-		/* Interrupt was not handled */
-		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
-			M.x86.R_AX);
-		return 0;
-	}
-
-	/* Interrupt handled */
-	return 1;
-}
-#endif
-
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-static void int15_install(void)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
-	typedef int (* yabel_handleIntFunc)(void);
-	extern yabel_handleIntFunc yabel_intFuncArray[256];
-	yabel_intFuncArray[0x15] = int15_handler;
-#endif
-#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	mainboard_interrupt_handlers(0x15, &int15_handler);
-#endif
-}
-#endif
-
-/* Audio Setup */
-
-extern const u32 * cim_verb_data;
-extern u32 cim_verb_data_size;
-
-static void verb_setup(void)
-{
-	cim_verb_data = mainboard_cim_verb_data;
-	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
-}
-
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
-
-static void mainboard_enable(device_t dev)
-{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	/* Install custom int15 handler for VGA OPROM */
-	int15_install();
-#endif
-	verb_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	CHIP_NAME("Compal Link ChromeBox")
-	.enable_dev = mainboard_enable,
-};
-
diff --git a/src/mainboard/intel/graysreef/mainboard_smi.c b/src/mainboard/intel/graysreef/mainboard_smi.c
deleted file mode 100644
index ecfc385..0000000
--- a/src/mainboard/intel/graysreef/mainboard_smi.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
-
-int mainboard_io_trap_handler(int smif)
-{
-	switch (smif) {
-	case 0x99:
-		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
-		break;
-	default:
-		return 0;
-	}
-
-	/* On success, the IO Trap Handler returns 0
-	 * On failure, the IO Trap Handler returns a value != 0
-	 *
-	 * For now, we force the return value to 0 and log all traps to
-	 * see what's going on.
-	 */
-	//gnvs->smif = 0;
-	return 1;
-}
-
-/*
- * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
- * The IO address is hardcoded as we don't have device path in SMM.
- */
-#define SIO_GPIO_BASE_SET4	(0x730 + 3)
-#define SIO_GPIO_BLINK_GPIO45	0x25
-void mainboard_smi_sleep(u8 slp_typ)
-{
-	u8 reg8;
-
-	switch (slp_typ) {
-	case SLP_TYP_S3:
-	case SLP_TYP_S4:
-		break;
-
-	case SLP_TYP_S5:
-		/* Turn off LED */
-		reg8 = inb(SIO_GPIO_BASE_SET4);
-		reg8 |= (1 << 5);
-		outb(reg8, SIO_GPIO_BASE_SET4);
-		break;
-	}
-}
-
-#define APMC_FINALIZE 0xcb
-
-static int mainboard_finalized = 0;
-
-int mainboard_smi_apmc(u8 apmc)
-{
-	switch (apmc) {
-	case APMC_FINALIZE:
-		if (mainboard_finalized) {
-			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
-			return 0;
-		}
-
-		intel_me_finalize_smm();
-		intel_pch_finalize_smm();
-		intel_northbridge_haswell_finalize_smm();
-		intel_cpu_haswell_finalize_smm();
-
-		mainboard_finalized = 1;
-		break;
-	}
-	return 0;
-}
diff --git a/src/mainboard/intel/graysreef/onboard.h b/src/mainboard/intel/graysreef/onboard.h
deleted file mode 100644
index 52f53e0..0000000
--- a/src/mainboard/intel/graysreef/onboard.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef LUMPY_ONBOARD_H
-#define LUMPY_ONBOARD_H
-
-#include <arch/smp/mpspec.h>
-
-#define LUMPY_LIGHTSENSOR_NAME      "lightsensor"
-#define LUMPY_LIGHTSENSOR_I2C_ADDR  0x44
-#define LUMPY_LIGHTSENSOR_GSI       20
-#define LUMPY_LIGHTSENSOR_IRQ       14
-#define LUMPY_LIGHTSENSOR_IRQ_MODE  (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
-
-#define LUMPY_TRACKPAD_NAME         "trackpad"
-#define LUMPY_TRACKPAD_I2C_ADDR     0x67
-#define LUMPY_TRACKPAD_GSI          21
-#define LUMPY_TRACKPAD_IRQ          15
-#define LUMPY_TRACKPAD_IRQ_MODE     (MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW)
-
-#endif
diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c
deleted file mode 100644
index c12e03c..0000000
--- a/src/mainboard/intel/graysreef/romstage.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <lib.h>
-#include <timestamp.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
-#include "southbridge/intel/lynxpoint/gpio.h"
-#include <arch/cpu.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include "gpio.h"
-#if CONFIG_CHROMEOS
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
-
-static void pch_enable_lpc(void)
-{
-	device_t dev = PCH_LPC_DEV;
-
-	/* Set COM1/COM2 decode range */
-	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
-
-	/* Enable SuperIO + COM1 + PS/2 Keyboard/Mouse */
-	u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN;
-	pci_write_config16(dev, LPC_EN, lpc_config);
-}
-
-static void rcba_config(void)
-{
-	u32 reg32;
-
-	/*
-	 *             GFX    INTA -> PIRQA (MSI)
-	 * D28IP_P1IP  WLAN   INTA -> PIRQB
-	 * D28IP_P4IP  ETH0   INTB -> PIRQC
-	 * D29IP_E1P   EHCI1  INTA -> PIRQD
-	 * D26IP_E2P   EHCI2  INTA -> PIRQE
-	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
-	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
-	 * D31IP_TTIP  THRT   INTC -> PIRQH
-	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
-	 */
-
-	/* Device interrupt pin register (board specific) */
-	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
-		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
-	RCBA32(D30IP) = (NOINT << D30IP_PIP);
-	RCBA32(D29IP) = (INTA << D29IP_E1P);
-	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
-		(INTB << D28IP_P4IP);
-	RCBA32(D27IP) = (INTA << D27IP_ZIP);
-	RCBA32(D26IP) = (INTA << D26IP_E2P);
-	RCBA32(D25IP) = (NOINT << D25IP_LIP);
-	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
-
-	/* Device interrupt route registers */
-	DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
-	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
-	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
-	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
-	DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
-	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
-	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
-
-	/* Enable IOAPIC (generic) */
-	RCBA16(OIC) = 0x0100;
-	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(OIC);
-
-	/* Disable unused devices (board specific) */
-	reg32 = RCBA32(FD);
-	reg32 |= PCH_DISABLE_ALWAYS;
-	RCBA32(FD) = reg32;
-}
-
-// FIXME, this function is generic code that should go to sb/... or
-// nb/../early_init.c
-static void early_pch_init(void)
-{
-	u8 reg8;
-
-	// reset rtc power status
-	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
-	reg8 &= ~(1 << 2);
-	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
-}
-
-void main(unsigned long bist)
-{
-	int boot_mode = 0;
-	int cbmem_was_initted;
-	u32 pm1_cnt;
-	u16 pm1_sts;
-
-#if CONFIG_COLLECT_TIMESTAMPS
-	tsc_t start_romstage_time;
-	tsc_t before_dram_time;
-	tsc_t after_dram_time;
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-#endif
-	struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: DEFAULT_PCIEXBAR,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: HPET_ADDR,
-		rcba: DEFAULT_RCBA,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		temp_mmio_base: 0xfed08000,
-		system_type: 0, // 0 Mobile, 1 Desktop/Server
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xa0, 0xa2, 0xa4, 0xa6 },
-		ec_present: 0,
-		// 0 = leave channel enabled
-		// 1 = disable dimm 0 on channel
-		// 2 = disable dimm 1 on channel
-		// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 0,
-		dimm_channel1_disabled: 0,
-		max_ddr3_freq: 1600,
-		usb_port_config: {
-			{ 1, 0, 0x0040 }, /* P0: Back USB3 port  (OC0) */
-			{ 1, 0, 0x0040 }, /* P1: Back USB3 port  (OC0) */
-			{ 1, 1, 0x0040 }, /* P2: Flex Port on bottom (OC1) */
-			{ 1, 8, 0x0040 }, /* P3: Docking connector (no OC) */
-			{ 1, 8, 0x0040 }, /* P4: Mini PCIE (no OC) */
-			{ 1, 1, 0x0040 }, /* P5: USB eSATA header (OC1) */
-			{ 1, 3, 0x0040 }, /* P6: Front Header J8H2 (OC3) */
-			{ 1, 3, 0x0040 }, /* P7: Front Header J8H2 (OC3) */
-			{ 1, 4, 0x0040 }, /* P8: USB/LAN Jack (OC4) */
-			{ 1, 4, 0x0040 }, /* P9: USB/LAN Jack (OC4) */
-			{ 1, 5, 0x0040 }, /* P10: Front Header J7H3 (OC5) */
-			{ 1, 5, 0x0040 }, /* P11: Front Header J7H3 (OC5) */
-			{ 1, 6, 0x0040 }, /* P12: USB/DP Jack (OC6) */
-			{ 1, 6, 0x0040 }, /* P13: USB/DP Jack (OC6) */
-		},
-	};
-
-#if CONFIG_COLLECT_TIMESTAMPS
-	start_romstage_time = rdtsc();
-#endif
-
-	if (bist == 0)
-		enable_lapic();
-
-	pch_enable_lpc();
-
-	/* Enable GPIOs */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
-	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-	setup_pch_gpios(&graysreef_gpio_map);
-
-	/* Early Console setup */
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	/*
-	 * FIXME: MCHBAR isn't setup yet. It's setup in
-	 * haswell_early_initialization().
-	 */
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk(BIOS_DEBUG, "soft reset detected\n");
-		boot_mode = 1;
-
-		/* System is not happy after keyboard reset... */
-		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
-		outb(0x6, 0xcf9);
-		while (1) {
-			hlt();
-		}
-	}
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	haswell_early_initialization(HASWELL_MOBILE);
-	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
-
-	/* Check PM1_STS[15] to see if we are waking from Sx */
-	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
-
-	/* Read PM1_CNT[12:10] to determine which Sx state */
-	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
-
-	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
-	}
-
-	post_code(0x38);
-	/* Enable SPD ROMs and DDR-III DRAM */
-	enable_smbus();
-
-	/* Prepare USB controller early in S3 resume */
-	if (boot_mode == 2)
-		enable_usb_bar();
-
-	post_code(0x3a);
-	pei_data.boot_mode = boot_mode;
-#if CONFIG_COLLECT_TIMESTAMPS
-	before_dram_time = rdtsc();
-#endif
-	sdram_initialize(&pei_data);
-
-#if CONFIG_COLLECT_TIMESTAMPS
-	after_dram_time = rdtsc();
-#endif
-	post_code(0x3b);
-	/* Perform some initialization that must run before stage2 */
-	early_pch_init();
-	post_code(0x3c);
-
-	/* This should probably go away. Until now it is required
-	 * and mainboard specific
-	 */
-	rcba_config();
-	post_code(0x3d);
-
-	quick_ram_check();
-	post_code(0x3e);
-
-	MCHBAR16(SSKPD) = 0xCAFE;
-#if CONFIG_EARLY_CBMEM_INIT
-	cbmem_was_initted = !cbmem_initialize();
-#else
-	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
-						     - HIGH_MEMORY_SIZE));
-#endif
-
-#if CONFIG_HAVE_ACPI_RESUME
-	/* If there is no high memory area, we didn't boot before, so
-	 * this is not a resume. In that case we just create the cbmem toc.
-	 */
-
-	*(u32 *)CBMEM_BOOT_MODE = 0;
-	*(u32 *)CBMEM_RESUME_BACKUP = 0;
-
-	if ((boot_mode == 2) && cbmem_was_initted) {
-		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
-		if (resume_backup_memory) {
-			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
-			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
-		}
-		/* Magic for S3 resume */
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
-	} else if (boot_mode == 2) {
-		/* Failed S3 resume, reset to come up cleanly */
-		outb(0x6, 0xcf9);
-		while (1) {
-			hlt();
-		}
-	} else {
-		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
-	}
-#endif
-	post_code(0x3f);
-#if CONFIG_CHROMEOS
-	init_chromeos(boot_mode);
-#endif
-#if CONFIG_COLLECT_TIMESTAMPS
-	timestamp_init(base_time);
-	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
-	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
-	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
-	timestamp_add_now(TS_END_ROMSTAGE);
-#endif
-#if CONFIG_CONSOLE_CBMEM
-	/* Keep this the last thing this function does. */
-	cbmemc_reinit();
-#endif
-}
diff --git a/src/mainboard/intel/graysreef/thermal.h b/src/mainboard/intel/graysreef/thermal.h
deleted file mode 100644
index 2068686..0000000
--- a/src/mainboard/intel/graysreef/thermal.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef GRAYSREEF_THERMAL_H
-#define GRAYSREEF_THERMAL_H
-
-/* Fan is OFF */
-#define FAN4_THRESHOLD_OFF	0
-#define FAN4_THRESHOLD_ON	0
-#define FAN4_PWM		0x00
-
-/* Fan is at LOW speed */
-#define FAN3_THRESHOLD_OFF	48
-#define FAN3_THRESHOLD_ON	55
-#define FAN3_PWM		0x40
-
-/* Fan is at MEDIUM speed */
-#define FAN2_THRESHOLD_OFF	52
-#define FAN2_THRESHOLD_ON	64
-#define FAN2_PWM		0x80
-
-/* Fan is at HIGH speed */
-#define FAN1_THRESHOLD_OFF	60
-#define FAN1_THRESHOLD_ON	68
-#define FAN1_PWM		0xb0
-
-/* Fan is at FULL speed */
-#define FAN0_THRESHOLD_OFF	66
-#define FAN0_THRESHOLD_ON	78
-#define FAN0_PWM		0xff
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE	90
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE		100
-
-#endif



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