[coreboot] New patch to review for coreboot: 6bb8525 baskingridge: zero out alt_gp_smi_en in devicetree

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Tue Mar 12 22:51:14 CET 2013

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2673


commit 6bb8525518ef836b35f948c104dd923aa6068127
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Dec 12 12:32:43 2012 -0600

    baskingridge: zero out alt_gp_smi_en in devicetree
    The baskingridge has a non-zero alt_gp_smi_en value in the
    devicetree.cb file. It has just to be determined which GPI
    pins should trigger an SMI on basking ridge. Without this change
    the board would hang during boot (presumably through a SMI flood).
    No more hangs once the value is zero.
    Change-Id: I9704071bb7966bd3d0bbbc4aafede3f42d829b17
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
 src/mainboard/intel/baskingridge/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb
index 737de1c..c74767a 100644
--- a/src/mainboard/intel/baskingridge/devicetree.cb
+++ b/src/mainboard/intel/baskingridge/devicetree.cb
@@ -47,7 +47,7 @@ chip northbridge/intel/haswell
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
 			register "gpi1_routing" = "1"
 			register "gpi14_routing" = "2"
-			register "alt_gp_smi_en" = "0x0002"
+			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en" = "0x4000"
 			register "ide_legacy_combined" = "0x0"

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