[coreboot] New patch to review for coreboot: 8883c2d lynxpoint: Add support for disabling ULT devices

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Wed Mar 13 02:42:23 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2695

-gerrit

commit 8883c2d159c49f1a639f586b0988e2af9e3cd49e
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 10 13:20:40 2013 -0800

    lynxpoint: Add support for disabling ULT devices
    
    These enables are hidden behind IOBP for some reason.
    
    Boot to linux with SDIO disabled and see that
    the SDIO driver does not load and crash the system.
    
    Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/lynxpoint/pch.c | 24 ++++++++++++++++++++++++
 src/southbridge/intel/lynxpoint/pch.h | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 1fb4915..41c596c 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -61,6 +61,27 @@ static void pch_hide_devfn(unsigned devfn)
 	case PCI_DEVFN(20, 0): /* XHCI */
 		RCBA32_OR(FD, PCH_DISABLE_XHCI);
 		break;
+	case PCI_DEVFN(21, 0): /* DMA */
+		pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 1): /* I2C0 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 2): /* I2C1 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 3): /* SPI0 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 4): /* SPI1 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 5): /* UART0 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
+	case PCI_DEVFN(21, 6): /* UART1 */
+		pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
 	case PCI_DEVFN(22, 0): /* MEI #1 */
 		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 		break;
@@ -73,6 +94,9 @@ static void pch_hide_devfn(unsigned devfn)
 	case PCI_DEVFN(22, 3): /* KT */
 		RCBA32_OR(FD2, PCH_DISABLE_KT);
 		break;
+	case PCI_DEVFN(23, 0): /* SDIO */
+		pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		break;
 	case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
 		RCBA32_OR(BUC, PCH_DISABLE_GBE);
 		break;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 229b795..f27ae90 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -286,6 +286,40 @@ unsigned get_gpios(const int *gpio_num_array);
 #define SATA_IOBP_SP0G3IR	0xea000151
 #define SATA_IOBP_SP1G3IR	0xea000051
 
+/* Serial IO IOBP Registers */
+#define SIO_IOBP_PORTCTRL0	0xcb000000	/* SDIO D23:F0 */
+#define  SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN		(1 << 5)
+#define  SIO_IOBP_PORTCTRL0_PCI_CONF_DIS	(1 << 4)
+#define SIO_IOBP_PORTCTRL1	0xcb000014	/* SDIO D23:F0 */
+#define  SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x)	(((x) & 3) << 13)
+#define SIO_IOBP_GPIODF		0xcb000154
+#define  SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN	(1 << 4)
+#define  SIO_IOBP_GPIODF_DMA_IDLE_DET_EN	(1 << 3)
+#define  SIO_IOBP_GPIODF_UART_IDLE_DET_EN	(1 << 2)
+#define  SIO_IOBP_GPIODF_I2C_IDLE_DET_EN	(1 << 1)
+#define  SIO_IOBP_GPIODF_SPI_IDLE_DET_EN	(1 << 0)
+#define SIO_IOBP_PORTCTRL2	0xcb000240	/* DMA D21:F0 */
+#define SIO_IOBP_PORTCTRL3	0xcb000248	/* I2C0 D21:F1 */
+#define SIO_IOBP_PORTCTRL4	0xcb000250	/* I2C1 D21:F2 */
+#define SIO_IOBP_PORTCTRL5	0xcb000258	/* SPI0 D21:F3 */
+#define SIO_IOBP_PORTCTRL6	0xcb000260	/* SPI1 D21:F4 */
+#define SIO_IOBP_PORTCTRL7	0xcb000268	/* UART0 D21:F5 */
+#define SIO_IOBP_PORTCTRL8	0xcb000270	/* UART1 D21:F6 */
+/* PORTCTRL 2-8 have the same layout */
+#define  SIO_IOBP_PORTCTRL_ACPI_IRQ_EN		(1 << 21)
+#define  SIO_IOBP_PORTCTRL_PCI_CONF_DIS		(1 << 20)
+#define  SIO_IOBP_PORTCTRL_SNOOP_SELECT(x)	(((x) & 3) << 18)
+#define  SIO_IOBP_PORTCTRL_INT_PIN(x)		(((x) & 0xf) << 2)
+#define SIO_IOBP_FUNCDIS0	0xce00aa07	/* DMA D21:F0 */
+#define SIO_IOBP_FUNCDIS1	0xce00aa47	/* I2C0 D21:F1 */
+#define SIO_IOBP_FUNCDIS2	0xce00aa87	/* I2C1 D21:F2 */
+#define SIO_IOBP_FUNCDIS3	0xce00aac7	/* SPI0 D21:F3 */
+#define SIO_IOBP_FUNCDIS4	0xce00ab07	/* SPI1 D21:F4 */
+#define SIO_IOBP_FUNCDIS5	0xce00ab47	/* UART0 D21:F5 */
+#define SIO_IOBP_FUNCDIS6	0xce00ab87	/* UART1 D21:F6 */
+#define SIO_IOBP_FUNCDIS7	0xce00ae07	/* SDIO D23:F0 */
+#define  SIO_IOBP_FUNCDIS_DIS			(1 << 8)
+
 /* PCI Configuration Space (D31:F3): SMBus */
 #define PCH_SMBUS_DEV		PCI_DEV(0, 0x1f, 3)
 #define SMB_BASE		0x20



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