[coreboot] Patch merged into coreboot/master: 26e7dd7 haswell: more ULT/LP support and minor tweaks

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 26e7dd703dea8dce30829d8bb73c1f27a2178d72
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Dec 19 09:12:31 2012 -0800

    haswell: more ULT/LP support and minor tweaks
    
    - Add ME device ID for Lynxpoint LP
    - Add GPU device IDs for ULT
    - SATA init tweaks from checking against DXE reference code
    - Remove the ICH7 from the SPI driver so it works on all lynxpoint
    without having to add more LPC device ID checks
    - Add function disable for audio dsp and xhci, remove PCI bridge
    - Add interrupt route registers for new devices (needs romstage setup)
    
    Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/2680
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Mar 13 03:20:37 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Thu Mar 14 20:16:26 2013, giving +2
See http://review.coreboot.org/2680 for details.

-gerrit