[coreboot] Patch set updated for coreboot: f37bd76 Super i/o W83627DHG UARTB could not function properly.

[Wolfgang Kamp (wmkamp@datakamp.de)]

Wolfgang Kamp (wmkamp at datakamp.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2626

-gerrit

commit f37bd7638f3279dc194c12c96913f7de622dfb7d
Author: Wolfgang Kamp <wmkamp at datakamp.de>
Date:   Mon Mar 11 16:35:42 2013 +0100

    Super i/o W83627DHG UARTB could not function properly.
    
    Pins 78-85 are set to GPIO after power on or reset.
    Pins must be redirected to UARTB if enabled.
    Look at W83627DHG databook version 1.4 page 185 Chip
    (global) Control Register CR2C.
    
    Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
    Signed-off-by: Wolfgang Kamp <wmkamp at datakamp.de>
---
 src/superio/winbond/w83627dhg/superio.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 26f2921..bbde26a 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -37,6 +37,17 @@ void pnp_exit_ext_func_mode(device_t dev)
 	outb(0xaa, dev->path.pnp.port);
 }
 
+static void w83627dhg_enable_UR2(device_t dev)
+{
+	u8 reg8;
+
+	pnp_enter_ext_func_mode(dev);
+	reg8 = pnp_read_config(dev, 0x2c);
+	reg8 |= (0x3);
+	pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
+	pnp_exit_ext_func_mode(dev);
+}
+
 static void w83627dhg_init(device_t dev)
 {
 	struct superio_winbond_w83627dhg_config *conf = dev->chip_info;
@@ -45,6 +56,9 @@ static void w83627dhg_init(device_t dev)
 		return;
 
 	switch(dev->path.pnp.device) {
+	case W83627DHG_SP2:
+		w83627dhg_enable_UR2(dev);
+		break;
 	case W83627DHG_KBC:
 		pc_keyboard_init(&conf->keyboard);
 		break;