[coreboot] New patch to review for coreboot: 5455e38 Add bd82x6x XHCI(USB3) S3/S4 workaround

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Fri Mar 15 21:13:37 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2759

-gerrit

commit 5455e38d72a5d4e5b9a62f1f419d9bdebdbd8637
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Mon Feb 11 14:39:28 2013 -0700

    Add bd82x6x XHCI(USB3) S3/S4 workaround
    
    The bd82x6x requires some additional setting on S3/S4 entry.
    
    Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 src/southbridge/intel/bd82x6x/smihandler.c | 45 ++++++++++++++++++++++++++----
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 093da5c..5d5dad1 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -328,15 +328,50 @@ static void southbridge_gate_memory_reset(void)
 
 static void xhci_sleep(u8 slp_typ)
 {
-	u32 reg32;
+	u32 reg32, xhci_bar;
+	u16 reg16;
 
-	if (slp_typ == SLP_TYP_S5) {
-	    reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74);
-	    reg32 |= (1 << 8 | 0x03 );
-	    pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32);
+	switch (slp_typ) {
+	case SLP_TYP_S3:
+	case SLP_TYP_S4:
+		reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+		reg16 &= ~0x03UL;
+		pcie_write_config32(PCH_XHCI_DEV, 0x74, reg16);
+
+		reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
+		reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+		pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
+
+		xhci_bar = pcie_read_config32(PCH_XHCI_DEV,
+				              PCI_BASE_ADDRESS_0) & ~0xFUL;
+
+		if ((xhci_bar + 0x4C0) & 1)
+			pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
+		if ((xhci_bar + 0x4D0) & 1)
+			pch_iobp_update(0xEC000182, ~0UL, (3 << 2));
+		if ((xhci_bar + 0x4E0) & 1)
+			pch_iobp_update(0xEC000282, ~0UL, (3 << 2));
+		if ((xhci_bar + 0x4F0) & 1)
+			pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
+
+		reg32 = pcie_read_config32(PCH_XHCI_DEV, PCI_COMMAND);
+		reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+		pcie_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32);
+
+		reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+		reg16 |= 0x03;
+		pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16);
+		break;
+
+	case SLP_TYP_S5:
+		reg16 = pcie_read_config16(PCH_XHCI_DEV, 0x74);
+		reg16 |= ((1 << 8) | 0x03);
+		pcie_write_config16(PCH_XHCI_DEV, 0x74, reg16);
+		break;
 	}
 }
 
+
 static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
 {
 	u8 reg8;



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