[coreboot] Patch merged into coreboot/master: 42ad200 Lippert Fam14 DSDT: Add secondary bus range to PCI0

gerrit at coreboot.org gerrit at coreboot.org
Sun Mar 17 19:55:04 CET 2013

the following patch was just integrated into master:
commit 42ad2006572ea784548a79aabfaa3b00295d1215
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Fri Mar 15 13:05:59 2013 -0600

    Lippert Fam14 DSDT: Add secondary bus range to PCI0
    Adding the 'WordBusNumber' macro to the PCI0
    CRES ResourceTemplate in the Persimmon DSDT.
    This sets up the bus number for the PCI0 device
    and the secondary bus number in the CRS method.
    This change came in response to a 'dmesg' error
    which states:
    '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
    By adding the 'WordBusNumber' macro, ACPI can set
    up a valid range for the PCIe downstream busses,
    thereby relieving the Linux kernel from "guessing"
    the valid range based off _BBN or assuming [0-0xFF].
    The Linux kernel code that checks this bus range is
    in `drivers/acpi/pci_root.c`.  PCI busses can have
    up to 256 secondary busses connected to them via
    a PCI-PCI bridge.  However, these busses do not
    have to be sequentially numbered, so leaving out a
    section of the range (eg. allowing [0-0x7F]) will
    unnecessarily restrict the downstream busses.
    This is the same change as made to Persimmon with
    change-id I44f22:
    Change-Id: Ie36b60973c6a5f9076bb55c8f451532711a2f8a8
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
    Reviewed-on: http://review.coreboot.org/2737
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 15 20:18:51 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sun Mar 17 19:55:03 2013, giving +2
See http://review.coreboot.org/2737 for details.


More information about the coreboot mailing list