[coreboot] Patch merged into coreboot/master: e6c3b1d haswell: include TSEG region in cacheable memory

gerrit at coreboot.org gerrit at coreboot.org
Sun Mar 17 20:05:16 CET 2013

the following patch was just integrated into master:
commit e6c3b1d30d3fa88af6da6fcc115aa6cba3c55d1c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Dec 21 21:22:07 2012 -0600

    haswell: include TSEG region in cacheable memory
    The SMRR takes precedence over the MTRR entries. Therefore, if the TSEG
    region is setup as cacheable through the MTTRs, accesses to the TSEG
    region before SMM relocation are cached. This allows for the setup of
    SMM relocation to be faster by caching accesses to the future TSEG
    (SMRAM) memory.
    MC MAP: TOM: 0x140000000
    MC MAP: TOUUD: 0x18f600000
    MC MAP: MESEG_BASE: 0x13f000000
    MC MAP: MESEG_LIMIT: 0x7fff0fffff
    MC MAP: REMAP_BASE: 0x13f000000
    MC MAP: REMAP_LIMIT: 0x18f5fffff
    MC MAP: TOLUD: 0xafa00000
    MC MAP: BGSM: 0xad800000
    MC MAP: BDSM: 0xada00000
    MC MAP: TESGMB: 0xad000000
    MC MAP: GGC: 0x209
       PCI: 00:00.0 resource base ad000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 4
       PCI: 00:00.0 resource base ad800000 size 2200000 align 0 gran 0 limit 0 flags f0000200 index 5
    Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
    Setting variable MTRR 1, base: 2048MB, range:  512MB, type WB
    Setting variable MTRR 2, base: 2560MB, range:  256MB, type WB
    Adding hole at 2776MB-2816MB
    Setting variable MTRR 3, base: 2776MB, range:    8MB, type UC
    Setting variable MTRR 4, base: 2784MB, range:   32MB, type UC
    Zero-sized MTRR range @0KB
     Allocate an msr - basek = 00400000, sizek = 0023d800,
    Setting variable MTRR 5, base: 4096MB, range: 2048MB, type WB
    Setting variable MTRR 6, base: 6144MB, range:  256MB, type WB
    Adding hole at 6390MB-6400MB
    Setting variable MTRR 7, base: 6390MB, range:    2MB, type UC
    MTRR translation from MB to addresses:
    MTRR 0: 0x00000000 -> 0x80000000 WB
    MTRR 1: 0x80000000 -> 0xa0000000 WB
    MTRR 2: 0xa0000000 -> 0xb0000000 WB
    MTRR 3: 0xad800000 -> 0xae000000 UC
    MTRR 4: 0xae000000 -> 0xb0000000 UC
    I'm not a fan of the marking physical address space with MTRRs as being
    UC which is PCI space, but it is technically correct.
    Lastly, drop a comment describing AP startup flow through coreboot.
    Change-Id: Ic63c0377b9c20102fcd3f190052fb32bc5f89182
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2690
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>

Build-Tested: build bot (Jenkins) at Fri Mar 15 00:26:45 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sun Mar 17 20:05:15 2013, giving +2
See http://review.coreboot.org/2690 for details.


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