[coreboot] Patch merged into coreboot/master: 239c2e8 haswell platforms: restructure romstage main

gerrit at coreboot.org gerrit at coreboot.org
Sun Mar 17 22:53:33 CET 2013

the following patch was just integrated into master:
commit 239c2e843f976d5915964c8cb1923305c574f8b5
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Dec 19 11:31:17 2012 -0600

    haswell platforms: restructure romstage main
    There was a mix of setup code sprinkled across the various components:
    southbridge code in the northbridge, etc. This commit reorganizes the
    code so that northbridge code doesn't initialize southbridge components.
    Additionally, the calling dram initialization no longer calls out to ME
    code. The main() function in the mainboard calls the necessary ME
    functions before and after dram initialization.
    The biggest change is the addition of an early_pch_init() function
    which initializes the BARs, GPIOs, and RCBA configuration. It is also
    responsible for reporting back to the caller if the board is being
    woken up from S3. The one sequence difference is that the RCBA config
    is performed before claling the reference code.
    Lastly the rcba configuration was changed to be table driven so that
    different board/configurations can use the same code. It should be
    possible to have board/configuration specific gpio and rcba
    configuration while reusing the romstage code.
    Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2681
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Thu Mar 14 23:23:32 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Sun Mar 17 22:53:28 2013, giving +2
See http://review.coreboot.org/2681 for details.


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