[coreboot] Patch merged into coreboot/master: 305b1f0 haswell: Parallel AP bringup

gerrit at coreboot.org gerrit at coreboot.org
Tue Mar 19 05:15:23 CET 2013


the following patch was just integrated into master:
commit 305b1f0d30b68c310d4dfa7e1a5f432769a65b31
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Jan 15 08:27:05 2013 -0600

    haswell: Parallel AP bringup
    
    This patch parallelizes the AP startup for Haswell-based devices. It
    does not touch the generic secondary startup code. Instead it provides
    its own MP support matching up with the Haswell BWG. It seemed to be too
    much trouble to support the old startup way and this new way. Because of
    that parallel loading is the only thing supported.
    
    A couple of things to note:
    1. Micrcode needs to be loaded twice. Once before MTRR and caching is
       enabled. And a second time after SMM relocation.
    2. The sipi_vector is entirely self-contained. Once it is loaded and
       written back to RAM the APs do not access memory outside of the
       sipi_vector load location until a sync up in ramstage.
    3. SMM relocation is kicked off by an IPI to self w/ SMI set as the
       destination mode.
    
    The following are timings from cbmem with dev mode disabled and recovery mode
    enabled to boot directly into the kernel. This was done on the
    baskingridge CRB with a 4-core 8-thread CPU and 2 DIMMs 1GiB each. The
    kernel has console enabled on the serial port. Entry 70 is the device
    initialization, and that is where the APs are brought up. With these two
    examples it looks to shave off ~200 ms of boot time.
    
    Before:
       1:55,382
       2:57,606 (2,223)
       3:3,108,983 (3,051,377)
       4:3,110,084 (1,101)
       8:3,113,109 (3,024)
       9:3,156,694 (43,585)
      10:3,156,815 (120)
      30:3,157,110 (295)
      40:3,158,180 (1,069)
      50:3,160,157 (1,977)
      60:3,160,366 (208)
      70:4,221,044 (1,060,677)
      75:4,221,062 (18)
      80:4,227,185 (6,122)
      90:4,227,669 (484)
      99:4,265,596 (37,927)
    1000:4,267,822 (2,225)
    1001:4,268,507 (685)
    1002:4,268,780 (272)
    1003:4,398,676 (129,896)
    1004:4,398,979 (303)
    1100:7,477,601 (3,078,621)
    1101:7,480,210 (2,608)
    
    After:
       1:49,518
       2:51,778 (2,259)
       3:3,081,186 (3,029,407)
       4:3,082,252 (1,066)
       8:3,085,137 (2,884)
       9:3,130,339 (45,202)
      10:3,130,518 (178)
      30:3,130,544 (26)
      40:3,131,125 (580)
      50:3,133,023 (1,897)
      60:3,133,278 (255)
      70:4,009,259 (875,980)
      75:4,009,273 (13)
      80:4,015,947 (6,674)
      90:4,016,430 (482)
      99:4,056,265 (39,835)
    1000:4,058,492 (2,226)
    1001:4,059,176 (684)
    1002:4,059,450 (273)
    1003:4,189,333 (129,883)
    1004:4,189,770 (436)
    1100:7,262,358 (3,072,588)
    1101:7,263,926 (1,567)
    
    Booted the baskingridge board as noted above. Also analyzed serial
    messages with pcserial enabled.
    
    Change-Id: Ifedc7f787953647c228b11afdb725686e38c4098
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: http://review.coreboot.org/2779
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Mar 19 02:20:03 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Tue Mar 19 05:15:22 2013, giving +2
See http://review.coreboot.org/2779 for details.

-gerrit



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