[coreboot] X201 porting

[George Chriss]

> From phcoder at gmail.com  Wed Jan 16 21:16:43 2013
> Date: Wed, 16 Jan 2013 21:16:43 +0100
> Subject: [coreboot] X201 porting
> Message-ID: <50F70AAB.7030007 at gmail.com>
>
> Hello, all. I've began porting coreboot to X201 laptop. I've analysed
> the original firmware (Phoenix). Video in original firmware is inited by
> VGA ROM. The firmware chip is an MX25L6445E SOIC8 package, 8 Mibibytes.
> Flashable externally with buspirate but you need an additional power
> supply and make sure that cable from chip to buspirate don't exceed ~10cm.
> One part of original consists of EFI executables. I've replaced the
> executables there with my own and when it ran, the RAM was already
> inited but not PCI.

Lenovo x201i also uses a Macronix MX25L6445E chip and I'd like to give it a
try using a Bus Pirate (ver. 3.6).

Which BIOS<->Bus Pirate pin assignments + serial mode are you using?  Is
the 'additional power supply' provided by the '3V3' pin on the Bus Pirate
or an external power supply?  Are there any special instructions on keeping
the laptop powered or should the laptop be fully 'off'?

I'm currently running a modified BIOS to bypass MiniPCI whitelist
checks.[1]  Is there a way to have the Pirate save a known-good backup
should flashing fail?  I've found flashrom-generated BIOS backups to be
problematic vs. external flashing.

Any other step-by-step guidance on the flashing process would also be
helpful.

Sincerely,
George

[1]
http://www.thinkwiki.org/wiki/Problem_with_unauthorized_MiniPCI_network_card


> I attach the pcidump and memory maps from normal boot (normalboot.txt)
> and when I insert GRUB in BIOS (grubinbios.txt). As you can see the
> devices visible in both modes differ. Especially communication
> controllers and PCI-PCI bridge. I attach 2 programs: x201_analyze and
> x201_reconstruct. With them you can split the original (and create
> descriptive XML) and then recreate firmware with changed files. I could
> with it also remove files from pack 1 in order to free up some space and
> so modified BIOSes continued to boot. lzint code is borrowed from phdeco.
> Right now the only working output console is through the use of system
> speaker ("spkmodem") and analysing it on another machine. The keyboard
> works for input. I've added "spkmodem" to GRUB for this but this code
> depends on having calibrated TSC. I'll adjust it to use only PIT instead
> and will contribute to coreboot then.
> My next step is to remove all parts of original BIOS which are not used
> to executed before the point I was able to take over and put in a
> coreboot in freed space and launch it from small .efi to take over the
> boot at this point. How much more init is needed from this point to
> booted kernel? Especially how much new code fro coreboot is needed.
> In the next stage I'l be working on eliminating original memory initer
> and replace it with coreboot one.
> --
> Regards
> Vladimir '?-coder/phcoder' Serbinenko
>
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