[coreboot] VIA C7 on BCom Winnet P680 - L1/L2 cache very slow

Aaron Durbin adurbin at chromium.org
Mon Oct 7 16:22:45 CEST 2013

On Sun, Oct 6, 2013 at 1:43 AM, Corey Osgood <corey.osgood at gmail.com> wrote:
> After sending the last message, I've done a little more debugging and dumped
> cr0, and also checked the C7 FCR, everything indicates the cache is properly
> enabled and not in NoWriteThrough mode, although I have very little C7
> specific information and none of it relating to cache.
> So, I'm now looking elsewhere, and at the moment I'm looking at MTRRs. All
> the fixed MTRRs, under coreboot, are 0'd out, and variable are all type 6
> (WB?), as can be seen in the attached boot log. Here's the way the stock
> BIOS sets them up:

MTRR: Physical address space:
0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 0
0x0000000004000000 - 0x000000003e000000 size 0x3a000000 type 6
0x000000003e000000 - 0x00000000fff80000 size 0xc1f80000 type 0
0x00000000fff80000 - 0x0000000100000000 size 0x00080000 type 5

0->64MiB is uncacheable
64MiB->992MiB is cacheable
992MiB-> -512KiB is uncacheable
-512KiB->4GiB is write-protect

The fixed MTRRs cover the first 1MiB so it's not surprising those are
zero'd out. The only odd thing I see in the variable MTRRs is the ROM
not being marked as WP, but I suspect that is from CONFIG_CACHE_ROM
not being enabled.

Looking through your resources I don't see anything that covers memory
during read resources (flags field):
#define IORESOURCE_MEM 0x00000200
#define IORESOURCE_CACHEABLE 0x00004000

Any flags with the bits 0x4200 should be cacheable memory.

DOMAIN: 0000 resource base c0000 size 3df40000 align 0 gran 0 limit 0
flags e0004200 index b

The above shows up ding assign resources. The MTRR code has a 64MiB
min alignment which makes me think that is where the 64MiB->992MiB
comes from.

I would do two things:

1. Add all ram resources during the read_resources() step. That way
the IO hole can be properly picked.
2. Ensure all the memory you know exist are added to the resource
list, including 0 -> 64MiB.

Hope that helps.


More information about the coreboot mailing list