[coreboot] Help required to initialize coreboot as Seabios (floppy mechanism for DUET) payload
Anthony Ross
anthonyross230 at gmail.com
Sun Oct 20 08:09:48 CEST 2013
Hello Coreboot Team,
Well Im very sorry that i forgot to mention in my previous email (Require
help to boot coreboot with seabios' s floppy mechanism ) that the bootup of
coreboot was initialized under qemu-kvm. I was able to perform this despite
having no virtualization support.
I have delayed a lot in responding and sorry for that too.Well I have begun
a new thread and as suggested earlier by the coreboot team here is the
output of `cbfstool build/coreboot.rom print`.
coreboot.rom: 1024 kB, bootblocksize 848, romsize 1048576, offset 0x0
> alignment: 64 bytes
>
> Name Offset Type
> Size
> cmos_layout.bin 0x0 cmos_layout
> 1160
> fallback/romstage 0x4c0 stage
> 15390
> fallback/coreboot_ram 0x4140 stage
> 43939
> fallback/payload 0xed40 payload
> 63172
> config 0x1e440 raw
> 3029
> floppyimg/MyFloppy.lzma 0x1f040 raw
> 575728
> (empty) 0xab980 null
> 344792
Not that this time I have booted coreboot with no hdd image & neither any
virtual cd-rom image.
Thanks
Neo
(attached coreboot and SeaBIOS log)
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coreboot-4.0-4718-g11b4780 Sat Oct 19 18:38:01 IST 2013 starting...
CBMEM region 17ee0000-17ffffff (cbmem_reinit)
CBMEM region 17ee0000-17ffffff (cbmem_init)
Adding CBMEM entry as no. 1
Loading image.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (147520 bytes), entry @ 0x100000
Jumping to image.
QEMU debugcon not found [port 0x402]
coreboot-4.0-4718-g11b4780 Sat Oct 19 18:38:01 IST 2013 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
QEMU: firmware config interface detected
QEMU: max_cpus is 1
CPU: APIC: 00 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1237] ops
PCI: 00:00.0 [8086/1237] enabled
PCI: 00:01.0 [8086/7000] bus ops
PCI: 00:01.0 [8086/7000] enabled
PCI: 00:01.1 [8086/7010] ops
PCI: 00:01.1 [8086/7010] enabled
PCI: 00:01.3 [8086/7113] bus ops
Wakeup from ACPI sleep type S5 (PMCNTRL=0000)
PCI: 00:01.3 [8086/7113] enabled
PCI: 00:02.0 [1013/00b8] enabled
scan_static_bus for PCI: 00:01.0
scan_static_bus for PCI: 00:01.0 done
scan_static_bus for PCI: 00:01.3
scan_static_bus for PCI: 00:01.3 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Detected 384 MiB RAM below 4G.
Detected 0 MiB RAM above 4G.
QEMU: reserve ioports 0x0510-0x0511 [firmware-config]
QEMU: reserve ioports 0x5658-0x5658 [vmware-port]
QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug]
QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug]
QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0]
CBMEM region 17ee0000-17ffffff (cbmem_late_set_table)
DOMAIN: 0000 read_resources bus 0 link: 0
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b
DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c
DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d
DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e
DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f
DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10
DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
PCI: 00:00.0
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PCI: 00:01.1
PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:01.3
PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10
PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.1 20 * [0x0 - 0xf] io
DOMAIN: 0000 compute_resources_io: base: 10 size: 10 align: 4 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem
PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem
PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem
DOMAIN: 0000 compute_resources_mem: base: 2011000 size: 2011000 align: 25 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:01.3
constrain_resources: PCI: 00:02.0
avoid_fixed_resources2: DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00005659 lim->limit 0000adff
avoid_fixed_resources2: DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 18000000 lim->limit febfffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:5659 size:10 align:4 gran:0 limit:adff
Assigned: PCI: 00:01.1 20 * [0x5800 - 0x580f] io
DOMAIN: 0000 allocate_resources_io: next_base: 5810 size: 10 align: 4 gran: 0 done
DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011000 align:25 gran:0 limit:febfffff
Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem
Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem
Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem
DOMAIN: 0000 allocate_resources_mem: next_base: fe011000 size: 2011000 align: 25 gran: 0 done
Root Device assign_resources, bus 0 link: 0
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 20 <- [0x0000005800 - 0x000000580f] size 0x00000010 gran 0x04 io
PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem
PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem
PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 5659 size 10 align 4 gran 0 limit adff flags 40040100 index 10000000
DOMAIN: 0000 resource base fc000000 size 2011000 align 25 gran 0 limit febfffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b
DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c
DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d
DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e
DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f
DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10
DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
PCI: 00:00.0
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PCI: 00:01.1
PCI: 00:01.1 resource base 5800 size 10 align 4 gran 4 limit adff flags 60000100 index 20
PCI: 00:01.3
PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:02.0
PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10
PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 00
PCI: 00:01.0 cmd <- 00
PCI: 00:01.1 cmd <- 01
PCI: 00:01.3 cmd <- 00
PCI: 00:02.0 cmd <- 03
done.
Initializing devices...
Root Device init
CPU_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device 623
CPU: family 06, model 02, stepping 03
CPU #0 initialized
PCI: 00:00.0 init
Keyboard init...
Assigning IRQ 10 to 0:1.3
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x400
PCI: 00:01.0 init
RTC Init
PCI: 00:01.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: off
PCI: 00:02.0 init
CBFS: ERROR: No file header found at 0xffc80 - try next aligned address: 0xffcc0.
CBFS: WARNING: 'pci1013,00b8.rom' not found.
CBFS: Could not find file 'pci1013,00b8.rom'.
Option ROM address for PCI: 00:02.0 = fe000000
PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f
PCI ROM image, vendor ID 1013, device ID 00b8,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
PCI: 00:02.0: enabled 1
CPU: 00: enabled 1
CBMEM region 17ee0000-17ffffff (cbmem_reinit)
Adding CBMEM entry as no. 2
Moving GDT to 17ee0400...ok
CBMEM Base is 17ee0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 3
Copying Interrupt Routing Table to 0x17ee0600... done.
PIRQ table: 128 bytes.
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 17ee1600.
ACPI: * HPET
ACPI: added table 1/32, length now 40
ACPI: * MADT
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * FACS
ACPI: * DSDT @ 17ee1920 Length fa0
ACPI: * FADT
ACPI: added table 4/32, length now 52
ACPI: * SSDT
Found 1 CPU(s).
ACPI: added table 5/32, length now 56
current = 17ee2a00
ACPI: done.
ACPI tables: 5120 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 17eeca00
Root Device (Emulation QEMU x86 i440fx/piix4)
CPU_CLUSTER: 0 (QEMU Northbridge i440fx)
APIC: 00 (unknown)
DOMAIN: 0000 (QEMU Northbridge i440fx)
PCI: 00:00.0 (QEMU Northbridge i440fx)
PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:02.0 (unknown)
CPU: 00 (unknown)
SMBIOS tables: 381 bytes.
Adding CBMEM entry as no. 6
Adding CBMEM entry as no. 7
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 15e0
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x17fed200
rom_table_end = 0x17fed200
... aligned to 0x17ff0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-0000000017edffff: RAM
3. 0000000017ee0000-0000000017ffffff: CONFIGURATION TABLES
4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 17fed200, 0x1f4 bytes, checksum 7f17
coreboot table: 524 bytes.
Multiboot Information structure has been written.
FREE SPACE 0. 17ff5200 0000ae00
CAR GLOBALS 1. 17ee0200 00000200
GDT 2. 17ee0400 00000200
IRQ TABLE 3. 17ee0600 00001000
ACPI 4. 17ee1600 0000b400
SMBIOS 5. 17eeca00 00000800
ACPI RESUME 6. 17eed200 00100000
COREBOOT 7. 17fed200 00008000
Loading segment from rom address 0xfff0ed78
code (compression=1)
New segment dstaddr 0xe1208 memsize 0x1edf8 srcaddr 0xfff0edb0 filesize 0xf624
(cleaned up) New segment addr 0xe1208 size 0x1edf8 offset 0xfff0edb0 filesize 0xf624
Loading segment from rom address 0xfff0ed94
Entry Point 0x000fef2c
Loading Segment: addr: 0x00000000000e1208 memsz: 0x000000000001edf8 filesz: 0x000000000000f624
lb: [0x0000000000100000, 0x0000000000124040)
Post relocation: addr: 0x00000000000e1208 memsz: 0x000000000001edf8 filesz: 0x000000000000f624
using LZMA
[ 0x000e1208, 00100000, 0x00100000) <- fff0edb0
dest 000e1208, end 00100000, bouncebuffer 17e97f80
Loaded segments
Jumping to boot code at 000fef2c
CPU0: stack: 0011f000 - 00120000, lowest used address 0011fb44, stack used: 1212 bytes
entry = 0x000fef2c
lb_start = 0x00100000
lb_size = 0x00024040
buffer = 0x17e97f80
coreboot-4.0-4718-g11b4780 Sat Oct 19 18:38:01 IST 2013 starting...
CBMEM region 17ee0000-17ffffff (cbmem_reinit)
CBMEM section cac4e6a3: using existing location at 17ee0200.
Loading image.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (147520 bytes), entry @ 0x100000
Jumping to image.
QEMU debugcon not found [port 0x402]
coreboot-4.0-4718-g11b4780 Sat Oct 19 18:38:01 IST 2013 booting...
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
QEMU: firmware config interface detected
QEMU: max_cpus is 1
CPU: APIC: 00 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1237] ops
PCI: 00:00.0 [8086/1237] enabled
PCI: 00:01.0 [8086/7000] bus ops
PCI: 00:01.0 [8086/7000] enabled
PCI: 00:01.1 [8086/7010] ops
PCI: 00:01.1 [8086/7010] enabled
PCI: 00:01.3 [8086/7113] bus ops
Wakeup from ACPI sleep type S0 (PMCNTRL=1401)
PCI: 00:01.3 [8086/7113] enabled
PCI: 00:02.0 [1013/00b8] enabled
scan_static_bus for PCI: 00:01.0
scan_static_bus for PCI: 00:01.0 done
scan_static_bus for PCI: 00:01.3
scan_static_bus for PCI: 00:01.3 done
PCI: pci_scan_bus returning with max=001
scan_static_bus for Root Device done
done
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Detected 384 MiB RAM below 4G.
Detected 0 MiB RAM above 4G.
QEMU: reserve ioports 0x0510-0x0511 [firmware-config]
QEMU: reserve ioports 0x5658-0x5658 [vmware-port]
QEMU: reserve ioports 0xae00-0xae0f [pci-hotplug]
QEMU: reserve ioports 0xaf00-0xaf1f [cpu-hotplug]
QEMU: reserve ioports 0xafe0-0xafe3 [piix4-gpe0]
CBMEM region 17ee0000-17ffffff (cbmem_late_set_table)
DOMAIN: 0000 read_resources bus 0 link: 0
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b
DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c
DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d
DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e
DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f
DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10
DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
PCI: 00:00.0
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PCI: 00:01.1
PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:01.3
PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:02.0
PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10
PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.1 20 * [0x0 - 0xf] io
DOMAIN: 0000 compute_resources_io: base: 10 size: 10 align: 4 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem
PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem
PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem
DOMAIN: 0000 compute_resources_mem: base: 2011000 size: 2011000 align: 25 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:01.3
constrain_resources: PCI: 00:02.0
avoid_fixed_resources2: DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00005659 lim->limit 0000adff
avoid_fixed_resources2: DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 18000000 lim->limit febfffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:5659 size:10 align:4 gran:0 limit:adff
Assigned: PCI: 00:01.1 20 * [0x5800 - 0x580f] io
DOMAIN: 0000 allocate_resources_io: next_base: 5810 size: 10 align: 4 gran: 0 done
DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011000 align:25 gran:0 limit:febfffff
Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem
Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem
Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem
DOMAIN: 0000 allocate_resources_mem: next_base: fe011000 size: 2011000 align: 25 gran: 0 done
Root Device assign_resources, bus 0 link: 0
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 20 <- [0x0000005800 - 0x000000580f] size 0x00000010 gran 0x04 io
PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem
PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem
PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:00.0
DOMAIN: 0000 resource base 5659 size 10 align 4 gran 0 limit adff flags 40040100 index 10000000
DOMAIN: 0000 resource base fc000000 size 2011000 align 25 gran 0 limit febfffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
DOMAIN: 0000 resource base c0000 size 17f40000 align 0 gran 0 limit 0 flags e0004200 index b
DOMAIN: 0000 resource base 510 size 2 align 0 gran 0 limit ffff flags e0000100 index c
DOMAIN: 0000 resource base 5658 size 1 align 0 gran 0 limit ffff flags e0000100 index d
DOMAIN: 0000 resource base ae00 size 10 align 0 gran 0 limit ffff flags e0000100 index e
DOMAIN: 0000 resource base af00 size 20 align 0 gran 0 limit ffff flags e0000100 index f
DOMAIN: 0000 resource base afe0 size 4 align 0 gran 0 limit ffff flags e0000100 index 10
DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2
DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3
PCI: 00:00.0
PCI: 00:01.0
PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2
PCI: 00:01.1
PCI: 00:01.1 resource base 5800 size 10 align 4 gran 4 limit adff flags 60000100 index 20
PCI: 00:01.3
PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1
PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2
PCI: 00:02.0
PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10
PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30
Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 00
PCI: 00:01.0 cmd <- 00
PCI: 00:01.1 cmd <- 01
PCI: 00:01.3 cmd <- 00
PCI: 00:02.0 cmd <- 03
done.
Initializing devices...
Root Device init
CPU_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device 623
CPU: family 06, model 02, stepping 03
CPU #0 initialized
PCI: 00:00.0 init
Keyboard init...
Assigning IRQ 10 to 0:1.3
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x400
PCI: 00:01.0 init
RTC Init
PCI: 00:01.1 init
IDE: Primary IDE interface: on
IDE: Secondary IDE interface: on
IDE: Access to legacy IDE ports: off
PCI: 00:02.0 init
CBFS: ERROR: No file header found at 0xffc80 - try next aligned address: 0xffcc0.
CBFS: WARNING: 'pci1013,00b8.rom' not found.
CBFS: Could not find file 'pci1013,00b8.rom'.
Option ROM address for PCI: 00:02.0 = fe000000
PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x010f
PCI ROM image, vendor ID 1013, device ID 00b8,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:01.3: enabled 1
PCI: 00:02.0: enabled 1
CPU: 00: enabled 1
CBMEM region 17ee0000-17ffffff (cbmem_reinit)
ok
CBMEM Base is 17ee0000.
Copying Interrupt Routing Table to 0x000f0000... done.
CBMEM section 49525154: using existing location at 17ee0600.
Copying Interrupt Routing Table to 0x17ee0600... done.
PIRQ table: 128 bytes.
CBMEM section 41435049: using existing location at 17ee1600.
ACPI: Writing ACPI tables at 17ee1600.
ACPI: * HPET
ACPI: added table 1/32, length now 40
ACPI: * MADT
ACPI: added table 2/32, length now 44
ACPI: * MCFG
ACPI: added table 3/32, length now 48
ACPI: * FACS
ACPI: * DSDT @ 17ee1920 Length fa0
ACPI: * FADT
ACPI: added table 4/32, length now 52
ACPI: * SSDT
Found 1 CPU(s).
ACPI: added table 5/32, length now 56
current = 17ee2a00
ACPI: done.
ACPI tables: 5120 bytes.
CBMEM section 534d4254: using existing location at 17eeca00.
smbios_write_tables: 17eeca00
Root Device (Emulation QEMU x86 i440fx/piix4)
CPU_CLUSTER: 0 (QEMU Northbridge i440fx)
APIC: 00 (unknown)
DOMAIN: 0000 (QEMU Northbridge i440fx)
PCI: 00:00.0 (QEMU Northbridge i440fx)
PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:01.3 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge)
PCI: 00:02.0 (unknown)
CPU: 00 (unknown)
SMBIOS tables: 381 bytes.
CBMEM section 5245534d: using existing location at 17eed200.
CBMEM section 43425442: using existing location at 17fed200.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 15e0
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x17fed200
rom_table_end = 0x17fed200
... aligned to 0x17ff0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-0000000017edffff: RAM
3. 0000000017ee0000-0000000017ffffff: CONFIGURATION TABLES
4. 00000000ff800000-00000000ffffffff: RESERVED
Wrote coreboot table at: 17fed200, 0x1f4 bytes, checksum 7f17
coreboot table: 524 bytes.
Multiboot Information structure has been written.
FREE SPACE 0. 17ff5200 0000ae00
CAR GLOBALS 1. 17ee0200 00000200
GDT 2. 17ee0400 00000200
IRQ TABLE 3. 17ee0600 00001000
ACPI 4. 17ee1600 0000b400
SMBIOS 5. 17eeca00 00000800
ACPI RESUME 6. 17eed200 00100000
COREBOOT 7. 17fed200 00008000
Loading segment from rom address 0xfff0ed78
code (compression=1)
New segment dstaddr 0xe1208 memsize 0x1edf8 srcaddr 0xfff0edb0 filesize 0xf624
(cleaned up) New segment addr 0xe1208 size 0x1edf8 offset 0xfff0edb0 filesize 0xf624
Loading segment from rom address 0xfff0ed94
Entry Point 0x000fef2c
Loading Segment: addr: 0x00000000000e1208 memsz: 0x000000000001edf8 filesz: 0x000000000000f624
lb: [0x0000000000100000, 0x0000000000124040)
Post relocation: addr: 0x00000000000e1208 memsz: 0x000000000001edf8 filesz: 0x000000000000f624
using LZMA
[ 0x000e1208, 00100000, 0x00100000) <- fff0edb0
dest 000e1208, end 00100000, bouncebuffer 17e97f80
Loaded segments
Jumping to boot code at 000fef2c
CPU0: stack: 0011f000 - 00120000, lowest used address 0011fb44, stack used: 1212 bytes
entry = 0x000fef2c
lb_start = 0x00100000
lb_size = 0x00024040
buffer = 0x17e97f80
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