From wordpress at blogs.coreboot.org  Wed Jul  1 03:01:32 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Wed, 1 Jul 2015 01:01:32 +0000
Subject: [coreboot] =?utf-8?q?New_on_blogs=2Ecoreboot=2Eorg=3A_=5BGSoC=5D_?=
	=?utf-8?q?coreboot_for_ARM64_Qemu_=E2=80=93_Week_=234_and_=235?=
Message-ID: <9613b6ec5de8597530a11eb0d2ba869f@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150701/d9d7617e/attachment.html>

From echelon at free.fr  Wed Jul  1 10:46:18 2015
From: echelon at free.fr (echelon at free.fr)
Date: Wed, 1 Jul 2015 10:46:18 +0200 (CEST)
Subject: [coreboot] trouble ahead?
Message-ID: <675913151.665836556.1435740378567.JavaMail.root@zimbra6-e1.priv.proxad.net>

Hello,

Sorry to fall in catastrophism again, but what do you think about that:

http://www.kitguru.net/components/anton-shilov/microsoft-is-interested-to-buy-advanced-micro-devices-source/

Quite bad news for coreboot isnt it?....

:-/

Florentin


From pgeorgi at google.com  Wed Jul  1 11:38:26 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Wed, 1 Jul 2015 11:38:26 +0200
Subject: [coreboot] trouble ahead?
In-Reply-To: <675913151.665836556.1435740378567.JavaMail.root@zimbra6-e1.priv.proxad.net>
References: <675913151.665836556.1435740378567.JavaMail.root@zimbra6-e1.priv.proxad.net>
Message-ID: <CAE-gjdXh4Eu86b4ZguBfTm_inydUtytx-+RiGsje6NcJHzkJDA@mail.gmail.com>

2015-07-01 10:46 GMT+02:00  <echelon at free.fr>:
> Quite bad news for coreboot isnt it?....
Unlikely. For one, it's one of many rumors (search around, and you'll
find that every IT company with a sufficient bank account was
"interested" do buy AMD at one point or another).

AMD is tons of different business units, and there was ever only one
that even acknowledged coreboot.
And their existing business case to justify the involvement with
coreboot doesn't vanish with a new owner.


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From rminnich at gmail.com  Wed Jul  1 16:09:53 2015
From: rminnich at gmail.com (ron minnich)
Date: Wed, 01 Jul 2015 14:09:53 +0000
Subject: [coreboot] trouble ahead?
In-Reply-To: <CAE-gjdXh4Eu86b4ZguBfTm_inydUtytx-+RiGsje6NcJHzkJDA@mail.gmail.com>
References: <675913151.665836556.1435740378567.JavaMail.root@zimbra6-e1.priv.proxad.net>
 <CAE-gjdXh4Eu86b4ZguBfTm_inydUtytx-+RiGsje6NcJHzkJDA@mail.gmail.com>
Message-ID: <CAP6exY++XZNE8ytH6xWrQS-BOVS=cJ4HOGhMFFr5RJydnhw0rQ@mail.gmail.com>

I can't see that it matters at all.

ron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150701/03e4ac84/attachment.html>

From echelon at free.fr  Wed Jul  1 16:43:05 2015
From: echelon at free.fr (echelon at free.fr)
Date: Wed, 1 Jul 2015 16:43:05 +0200 (CEST)
Subject: [coreboot] =?utf-8?q?Re=C2=A0=3A_Re=3A__trouble_ahead=3F?=
In-Reply-To: <CAP6exY++XZNE8ytH6xWrQS-BOVS=cJ4HOGhMFFr5RJydnhw0rQ@mail.gmail.com>
Message-ID: <115758414.666631072.1435761785362.JavaMail.root@zimbra6-e1.priv.proxad.net>

Depends .. if the big software company mentioned in the FA sees UEFI as *VERY* strategical for its business, what would be the point to be "nice" with a project that provides a competing solution of platform initialisation code?.. 
Now, on the other hand, I'm aware that they contribute to many open source projects (even to the Linux kernel I heard..) but nevertheless Im a little bit worried..
My 2 eurocents (still alive!..)
 Florentin

----- Mail d'origine -----
De: ron minnich <rminnich at gmail.com>
?: Patrick Georgi <pgeorgi at google.com>, Florentin Demetrescu <echelon at free.fr>
Cc: Coreboot <coreboot at coreboot.org>
Envoy?: Wed, 01 Jul 2015 16:09:53 +0200 (CEST)
Objet: Re: [coreboot] trouble ahead?

I can't see that it matters at all.

ron



From rminnich at gmail.com  Wed Jul  1 19:17:38 2015
From: rminnich at gmail.com (ron minnich)
Date: Wed, 01 Jul 2015 17:17:38 +0000
Subject: [coreboot] trouble ahead?
In-Reply-To: <115758414.666631072.1435761785362.JavaMail.root@zimbra6-e1.priv.proxad.net>
References: <CAP6exY++XZNE8ytH6xWrQS-BOVS=cJ4HOGhMFFr5RJydnhw0rQ@mail.gmail.com>
 <115758414.666631072.1435761785362.JavaMail.root@zimbra6-e1.priv.proxad.net>
Message-ID: <CAP6exYLw3zFYUm41rbSkT8qpNcvkiYe-dtLkHb6nDbrTWLnvug@mail.gmail.com>

On Wed, Jul 1, 2015 at 7:46 AM <echelon at free.fr> wrote:

> Depends .. if the big software company mentioned in the FA sees UEFI as
> *VERY* strategical for its business, what would be the point to be "nice"
> with a project that provides a competing solution of platform
> initialisation code?..
>

The big company of which you speak has seen UEFI as very strategial for 15
years now ... who cares? I never did.



> Now, on the other hand, I'm aware that they contribute to many open source
> projects (even to the Linux kernel I heard..) but nevertheless Im a little
> bit worried..
> My 2 eurocents (still alive!..)
>


don't worry, be happy!

ron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150701/af8e72dc/attachment.html>

From lynxis at fe80.eu  Thu Jul  2 19:42:39 2015
From: lynxis at fe80.eu (Alexander Couzens)
Date: Thu, 2 Jul 2015 19:42:39 +0200
Subject: [coreboot] rtc migrations / century byte used
Message-ID: <20150702194239.75b707e3@lazus.yip>

Hi,

I mentioned some problems while debugging windows on a x201.
Also linux throw a warning with the RTC, but it could recover
the correct time.
coreboot multiple use of one nvram byte on lots of boards.
On most board 0x32/b400 is used by some nvram settings as well as the OS interprets the time (century) from the same byte.
The century byte saves the century in bcd format. The default location is 0x32 / b400.

find src/mainboard/ -iname cmos.layout | xargs grep -h '^400'  | sort | uniq -c
    112 400          1       e       1        power_on_after_fail
     33 400          1       e       2        hyper_threading
      1 400          8       h       0        century
      9 400          8       h       0        volume
      1 400         8         r       0        stumpy_usb_reset_disable
      2 400         8       h       0        volume
# 37 boards can be removed from this list, because they disabled the century byte in facp.

This leads to 3 topic:
 * how can we change cmos.layout in a way no or less settings gets lost? e.g. add a version field and a way to migrate these. or do we ignore the loss of data?
 * do we want to support the century byte?
 * how do we fix the multiusage, because it makes problems atm.

best
lynxis

--
Alexander Couzens

mail: lynxis at fe80.eu
jabber: lynxis at jabber.ccc.de
mobile: +4915123277221
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150702/9838af3e/attachment.sig>

From amigabill at gmail.com  Thu Jul  2 20:10:56 2015
From: amigabill at gmail.com (Bill Toner)
Date: Thu, 2 Jul 2015 14:10:56 -0400
Subject: [coreboot] board bringup/debug howto?
Message-ID: <CAHQf8SHJVZiEcevxzBYWEt4-ZiOAnY9EdbdE3fcoBBQS4Fq5_w@mail.gmail.com>

Amd's embedded developer site suggests the sage smartprobe for jtag
debugging a target board. Sage's website shows this is discontinued. Whay
other options are there for bringup and lowlevel firmware and os driver
debug?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150702/38768a87/attachment.html>

From peter at stuge.se  Thu Jul  2 20:34:37 2015
From: peter at stuge.se (Peter Stuge)
Date: Thu, 2 Jul 2015 20:34:37 +0200
Subject: [coreboot] board bringup/debug howto?
In-Reply-To: <CAHQf8SHJVZiEcevxzBYWEt4-ZiOAnY9EdbdE3fcoBBQS4Fq5_w@mail.gmail.com>
References: <CAHQf8SHJVZiEcevxzBYWEt4-ZiOAnY9EdbdE3fcoBBQS4Fq5_w@mail.gmail.com>
Message-ID: <20150702183437.28292.qmail@stuge.se>

Bill Toner wrote:
> options .. for bringup and lowlevel firmware and os driver debug?

printf() over the channel of your choice (there are a few) and bus
analyzers.


//Peter


From paulepanter at users.sourceforge.net  Thu Jul  2 22:42:41 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 02 Jul 2015 22:42:41 +0200
Subject: [coreboot] CBMEM console deactivated in coreboot and activated
	SeaBIOS
Message-ID: <1435869761.3703.37.camel@users.sourceforge.net>

Dear coreboot folks,


if the CBMEM console is disabled in coreboot and only enabled in
SeaBIOS, currently SeaBIOS does not write any messages to the CBMEM
console (SeaBIOS commit f24eb2f85 (build: CONFIG_VGA_FIXUP_ASM should
depend on CONFIG_BUILD_VGABIOS)).

    $ more src/fw/coreboot.c
    [?]
    struct cb_cbmem_ref *cbref = find_cb_subtable(cbh, CB_TAG_CBMEM_CONSOLE);
    if (cbref) {
        cbcon = (void*)(u32)cbref->cbmem_addr;
        debug_banner();
        dprintf(1, "Found coreboot cbmem console @ %llx\n", cbref->cbmem_addr);
    }
    [?]

Does the CBMEM specification(?) allow to add the CBMEM console
section(?) ? CB_TAG_CBMEM_CONSOLE 0x17 ? after coreboot has run? If
yes, I could try to adapt SeaBIOS to do just that in case coreboot does
not set it up.


Thanks,

Paul
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150702/c787b4ef/attachment.asc>

From jakllsch at kollasch.net  Fri Jul  3 05:23:08 2015
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Thu, 2 Jul 2015 22:23:08 -0500
Subject: [coreboot] rtc migrations / century byte used
In-Reply-To: <20150702194239.75b707e3@lazus.yip>
References: <20150702194239.75b707e3@lazus.yip>
Message-ID: <20150703032300.GF3064@tazenda.kollasch.net>

On Thu, Jul 02, 2015 at 07:42:39PM +0200, Alexander Couzens wrote:
> Hi,
> 
> I mentioned some problems while debugging windows on a x201.
> Also linux throw a warning with the RTC, but it could recover
> the correct time.
> coreboot multiple use of one nvram byte on lots of boards.
> On most board 0x32/b400 is used by some nvram settings as well as the OS interprets the time (century) from the same byte.
> The century byte saves the century in bcd format. The default location is 0x32 / b400.
> 
> find src/mainboard/ -iname cmos.layout | xargs grep -h '^400'  | sort | uniq -c
>     112 400          1       e       1        power_on_after_fail
>      33 400          1       e       2        hyper_threading
>       1 400          8       h       0        century

this is probably winent/mb6047, which I recently fixed.

>       9 400          8       h       0        volume
>       1 400         8         r       0        stumpy_usb_reset_disable
>       2 400         8       h       0        volume
> # 37 boards can be removed from this list, because they disabled the century byte in facp.
> 
> This leads to 3 topic:
>  * how can we change cmos.layout in a way no or less settings gets lost? e.g. add a version field and a way to migrate these. or do we ignore the loss of data?

Doesn't look like any of the affected settings are extremely important.

>  * do we want to support the century byte?

We pretty much have to.  Between all the FACPs that say to use it and
the OSes (such as NetBSD) that look at byte 0x32 for the century without
checking the FACP.

>  * how do we fix the multiusage, because it makes problems atm.

I say we mark it like I did mb6047 or mark it reserved.  Also we
probably have a problem with checksumming come January 1st 2100 A.D....

	Jonathan Kollasch


From adam.duncan at gmail.com  Fri Jul  3 16:27:38 2015
From: adam.duncan at gmail.com (Adam Duncan)
Date: Fri, 3 Jul 2015 10:27:38 -0400
Subject: [coreboot] Recommended broadwell board w coreboot support
Message-ID: <CA+LD=-dTQN0Xs8Ds=tXsZxLZ5wMbResKvMUvzyUm3eiuxrs0uQ@mail.gmail.com>

Hi, I'm looking for a board with an Intel broadwell on it that I can get a
coreboot build going for. Do you have any recommendations?

Are there any commercial boards with the broadwell that are currently
supported?

If not, do you know which boards would be the easiest to focus on?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/bec0182e/attachment.html>

From kroms at posteo.be  Fri Jul  3 16:27:32 2015
From: kroms at posteo.be (kroms at posteo.be)
Date: Fri, 03 Jul 2015 16:27:32 +0200
Subject: [coreboot] T400 screen issue / EDID handling
Message-ID: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>

Hello,

I allready contacted Francis from libreboot and he forwared me to this 
list, because it seems to be an issue regarding coreboot.

I have flashed a Lenovo T400 with libreboot.

The T400 has an Intel GPU and I am able to use it with an external 
display connected to the onboard vga-port.

The issue is, that I can't use the internal display, which is an 
1440x900 Samusung LTN141WD-L05, EDID dump:

https://paste.debian.net/plainh/b3699c60

It seems like the internal screen is powered on while booting but it 
stays black.

Francis assumes that this is due to bugs in how coreboot handles the 
EDID.

Here is an EDID dump of a working display:

http://paste.debian.net/plainh/776705d5

Anyone is able to help?

Thanks in advance!




From adam.duncan at gmail.com  Fri Jul  3 16:39:48 2015
From: adam.duncan at gmail.com (Adam Duncan)
Date: Fri, 3 Jul 2015 10:39:48 -0400
Subject: [coreboot] Looking for Broadwell board for coreboot build
Message-ID: <CA+LD=-euUJzq+x+CQVquMdzo7R4jaxs8XCo-RdJTF=fQEudu+w@mail.gmail.com>

Hi, I'm looking for a board with an Intel broadwell on it that I can get a
coreboot build going for. Do you have any recommendations?

Are there any commercial boards with the broadwell that are currently
supported?

If not, do you know which boards would be the easiest to focus on?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/6393e559/attachment.html>

From rminnich at gmail.com  Fri Jul  3 19:39:08 2015
From: rminnich at gmail.com (ron minnich)
Date: Fri, 03 Jul 2015 17:39:08 +0000
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
Message-ID: <CAP6exYLzyOzQmVwV43sQBi0oYqnCx=QNyw23SoOrsrGVAeRWWg@mail.gmail.com>

Gee, what fun. There are lots of things that can go wrong, to get some
idea, see the
display handling for HP Falco, in which we managed 4 different types of
displays.

I'll try to take a look later, but just keep in mind that the displays are
frequently not all the same
on different production runs of a laptop so something that works fine on
one gives black
screen on another ...

ron

On Fri, Jul 3, 2015 at 7:35 AM <kroms at posteo.be> wrote:

> Hello,
>
> I allready contacted Francis from libreboot and he forwared me to this
> list, because it seems to be an issue regarding coreboot.
>
> I have flashed a Lenovo T400 with libreboot.
>
> The T400 has an Intel GPU and I am able to use it with an external
> display connected to the onboard vga-port.
>
> The issue is, that I can't use the internal display, which is an
> 1440x900 Samusung LTN141WD-L05, EDID dump:
>
> https://paste.debian.net/plainh/b3699c60
>
> It seems like the internal screen is powered on while booting but it
> stays black.
>
> Francis assumes that this is due to bugs in how coreboot handles the
> EDID.
>
> Here is an EDID dump of a working display:
>
> http://paste.debian.net/plainh/776705d5
>
> Anyone is able to help?
>
> Thanks in advance!
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/9be02105/attachment.html>

From francisco.dominguez.lerma2 at gmail.com  Fri Jul  3 21:35:37 2015
From: francisco.dominguez.lerma2 at gmail.com (francisco dominguez)
Date: Fri, 3 Jul 2015 21:35:37 +0200
Subject: [coreboot] About coreboot
Message-ID: <CAEmxpzuh-1qG-3S5OQpQ8qcTe7dtU3_TQ_VSKVd6tFpWzw-8hg@mail.gmail.com>

Hi, I'm new, I would like to help develop coreboot is C, I am interested to
collaborate because I like to learn more about C and take the chance to
help this fantastic community.

What language is written coreboot?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/fa90eae3/attachment.html>

From rminnich at gmail.com  Fri Jul  3 21:38:28 2015
From: rminnich at gmail.com (ron minnich)
Date: Fri, 03 Jul 2015 19:38:28 +0000
Subject: [coreboot] About coreboot
In-Reply-To: <CAEmxpzuh-1qG-3S5OQpQ8qcTe7dtU3_TQ_VSKVd6tFpWzw-8hg@mail.gmail.com>
References: <CAEmxpzuh-1qG-3S5OQpQ8qcTe7dtU3_TQ_VSKVd6tFpWzw-8hg@mail.gmail.com>
Message-ID: <CAP6exYJ7PN7cYs5UE6WXfntfkZGH3Ay2eGuXr3AJkTA28adthQ@mail.gmail.com>

Coreboot is written in C and assembly, with very little assembly. Your best
bet is to build the QEMU target first and just learn how to build, boot,
and change it.

ron

On Fri, Jul 3, 2015 at 12:36 PM francisco dominguez <
francisco.dominguez.lerma2 at gmail.com> wrote:

> Hi, I'm new, I would like to help develop coreboot is C, I am interested to
> collaborate because I like to learn more about C and take the chance to
> help this fantastic community.
>
> What language is written coreboot?
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/bba55e48/attachment.html>

From paulepanter at users.sourceforge.net  Fri Jul  3 23:19:46 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 03 Jul 2015 23:19:46 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
Message-ID: <1435958386.5493.61.camel@users.sourceforge.net>

Dear Kroms,


Am Freitag, den 03.07.2015, 16:27 +0200 schrieb kroms at posteo.be:
> 
> I allready contacted Francis from libreboot and he forwared me to 
> this list, because it seems to be an issue regarding coreboot.

welcome and thank you for writing a message to the mailing list.

> I have flashed a Lenovo T400 with libreboot.
> 
> The T400 has an Intel GPU and I am able to use it with an external 
> display connected to the onboard vga-port.
> 
> The issue is, that I can't use the internal display, which is an 
> 1440x900 Samusung LTN141WD-L05, EDID dump:
> 
> https://paste.debian.net/plainh/b3699c60

Please attach such information in the future instead of pasting it.

> It seems like the internal screen is powered on while booting but it 
> stays black.
> 
> Francis assumes that this is due to bugs in how coreboot handles the 
> EDID.
> 
> Here is an EDID dump of a working display:
> 
> http://paste.debian.net/plainh/776705d5

Ditto.

> Anyone is able to help?

Please send us your configuration (.config of coreboot and the payload)
and the log files from coreboot (cbmem -c), the payload and Linux.
That?s one of the advantages of using coreboot, that you have logs.
Please also provide the output of `build/cbfstool build/coreboot.rom
print`.


Thanks,

Paul
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/12551dec/attachment.asc>

From peter90609 at gmail.com  Fri Jul  3 09:53:03 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Fri, 3 Jul 2015 15:53:03 +0800
Subject: [coreboot] Question about making Qemu diskimg
Message-ID: <CACS=nFOhqC2QXz+H_Xv1-f7-2fUcEbnHZsra=xYT6iZjCKQV+Q@mail.gmail.com>

Hello

I have some questions about making Qemu disk image.

1. In QEMU_Build_Tutorial ,one step is to copy root file system to the
diskimg "* # cp -R /* /mnt/rootfs *",I what  know what files are necessary
?(I don't want put all of it,it might be too large)


2. Is it necessary to put Debian in diskimg?


3. I can't figure out this situation :
I can't successfully boot my disk image ,but can boot by QEMU download
image,so I try to create a empty disk image , format it as
(EXT2/EXT3/EXT4). mount QEMU download image and copy all of files into my
image mount's directory.Boot my disk image again,and It does't work.What's
wrong with my idea?I thought change my image contents to download's and it
can be work.It seems not.


thank for your help~
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150703/2ca63f61/attachment.html>

From kroms at posteo.be  Sat Jul  4 11:11:47 2015
From: kroms at posteo.be (kroms at posteo.be)
Date: Sat, 04 Jul 2015 11:11:47 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <1435958386.5493.61.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
Message-ID: <44e753be1d353223502ddde14a9b668e@posteo.de>

Dear Paul, dear Ron,

thank you for your messages!

I used a pre-compiled libreboot ROM image for flashing my T400:

t400_8mb_ukqwerty_vesafb.rom

(source: http://mirrors.mit.edu/libreboot/20150518/rom/)

I attached most of the requested information, I hope I found the right 
information:

requested information -> attached file or remark

.config of coreboot -> config_t400_8mb_libreboot

and the payload -> the 4 files beginning with grub_

log files from coreboot (cbmem -c) -> cbmem_-c

the payload -> I dont know to get or find it.

and Linux -> Do you mean the output of dmesg?

output of `build/cbfstool build/coreboot.rom print -> 
cbfstool_t400_8mb_ukqwerty_vesafb.rom (I used cbfstool on the used 
pre-compiled rom)

I attached the EDID dumps from my non working and a working display as 
well.

I hope this helps, if you need further information please let me know 
and I will try to provide them.

If you still need the logs files from the payload and Linux please give 
me the commands I have to execute. I am kind of a noob using Linux.

Thanks again an best regards,

Kroms










Am 03.07.2015 23:19 schrieb Paul Menzel:
> Dear Kroms,
> 
> 
> Am Freitag, den 03.07.2015, 16:27 +0200 schrieb kroms at posteo.be:
>> 
>> I allready contacted Francis from libreboot and he forwared me to
>> this list, because it seems to be an issue regarding coreboot.
> 
> welcome and thank you for writing a message to the mailing list.
> 
>> I have flashed a Lenovo T400 with libreboot.
>> 
>> The T400 has an Intel GPU and I am able to use it with an external
>> display connected to the onboard vga-port.
>> 
>> The issue is, that I can't use the internal display, which is an
>> 1440x900 Samusung LTN141WD-L05, EDID dump:
>> 
>> https://paste.debian.net/plainh/b3699c60
> 
> Please attach such information in the future instead of pasting it.
> 
>> It seems like the internal screen is powered on while booting but it
>> stays black.
>> 
>> Francis assumes that this is due to bugs in how coreboot handles the
>> EDID.
>> 
>> Here is an EDID dump of a working display:
>> 
>> http://paste.debian.net/plainh/776705d5
> 
> Ditto.
> 
>> Anyone is able to help?
> 
> Please send us your configuration (.config of coreboot and the payload)
> and the log files from coreboot (cbmem -c), the payload and Linux.
> That?s one of the advantages of using coreboot, that you have logs.
> Please also provide the output of `build/cbfstool build/coreboot.rom
> print`.
> 
> 
> Thanks,
> 
> Paul
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: edid_of_a_working_display
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0008.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: my_nonworking_edid
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0009.ksh>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: cbmem_-c
Type: text/x-c
Size: 71961 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0001.c>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: cbfstool_t400_8mb_ukqwerty_vesafb.rom
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0010.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: config_t400_8mb_libreboot
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0011.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: grub_menuentries_common.cfg
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0012.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: grub_extra_vesafb.cfg
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0013.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: grub_memdisk.cfg
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0014.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: grub_extra_common.cfg
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150704/b7737bf5/attachment-0015.ksh>

From paulepanter at users.sourceforge.net  Sun Jul  5 09:42:18 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 05 Jul 2015 09:42:18 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <44e753be1d353223502ddde14a9b668e@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
Message-ID: <1436082138.13469.47.camel@users.sourceforge.net>

Dear Kroms,


Am Samstag, den 04.07.2015, 11:11 +0200 schrieb kroms at posteo.be:

> I used a pre-compiled libreboot ROM image for flashing my T400:
> 
> t400_8mb_ukqwerty_vesafb.rom
> 
> (source: http://mirrors.mit.edu/libreboot/20150518/rom/)
> 
> I attached most of the requested information, I hope I found the 
> right information:
> 
> requested information -> attached file or remark
> 
> .config of coreboot -> config_t400_8mb_libreboot
> 
> and the payload -> the 4 files beginning with grub_
> 
> log files from coreboot (cbmem -c) -> cbmem_-c

Thank you. Unfortunately, I was unable to see anything suspicious in
there. Libreboot seems to strip of the coreboot revision it uses from
the banner, which is not good. It might be in the revision file in
CBFS.

    build/cbfstool build/coreboot.rom extract -n revision -f revision.txt

> the payload -> I dont know to get or find it.

It is GRUB. Unfortunately, I do not see GRUB?s debug messages in CBMEM.

> and Linux -> Do you mean the output of dmesg?

Indeed, that?s one way of getting them. Please provide the output.

[?]


Thanks,

Paul


PS: It?s quite common to use interleaved posting style [1] on mailing
lists.


[1] https://en.wikipedia.org/wiki/Posting_style
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150705/effe9a82/attachment.asc>

From info at gluglug.org.uk  Sun Jul  5 16:57:30 2015
From: info at gluglug.org.uk (Francis Rowe)
Date: Sun, 05 Jul 2015 15:57:30 +0100
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <1436082138.13469.47.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
Message-ID: <559945DA.7080802@gluglug.org.uk>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


> Thank you. Unfortunately, I was unable to see anything suspicious
> in there. Libreboot seems to strip of the coreboot revision it uses
> from the banner, which is not good. It might be in the revision
> file in CBFS.
> 

Libreboot builds coreboot without the .git directory, so it's not
possible to get the coreboot revision. You can find out what version
of coreboot it is by looking at
resources/scripts/helpers/download/coreboot

He is using libreboot 20150518, so the coreboot revision that he's
using is e19c8b0091022ae3f490601aed0c290cd5171b79

See
http://git.savannah.gnu.org/cgit/libreboot.git/tree/resources/scripts/helpers/download/coreboot?id=r20150518fix

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBAgAGBQJVmUXaAAoJEP9Ft0z50c+UzDwIAIvUK5lpPHveEKdoGeHRIvZ/
wrfTuzqtM2snIT2baypZTpcirxCfcLonr4dntKG4VkL5edxzWTjWpPF855vLyCeQ
gLBdGjHlZ+NTyZZDvkPoHJNGaPhoYUaUk/2L6GafUgYBRgxWcOjJs5xyfHk1VU/L
BcXFztVKfPM2BDWW0nue8ycdxzo3fTfAwNdCCCFBaypi22eEQXqEt4WNjAxlKbwE
Y1VxUn7klMDqP0HYCtWDr2Gmgw58LirZ2ZCq+Q00oae8ZXYIJzpp/qM6si8n25HI
lzuU9AHIzDiMQ/hGAuU0J6VOK9uHw+DTgFjWyCgu69DgInA9mfihoQbLd+ro/Lo=
=1+ZG
-----END PGP SIGNATURE-----


From info at gluglug.org.uk  Sun Jul  5 16:59:50 2015
From: info at gluglug.org.uk (Francis Rowe)
Date: Sun, 05 Jul 2015 15:59:50 +0100
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <559945DA.7080802@gluglug.org.uk>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <559945DA.7080802@gluglug.org.uk>
Message-ID: <55994666.7010605@gluglug.org.uk>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1



On 05/07/15 15:57, Francis Rowe wrote:
> 
>> Thank you. Unfortunately, I was unable to see anything
>> suspicious in there. Libreboot seems to strip of the coreboot
>> revision it uses from the banner, which is not good. It might be
>> in the revision file in CBFS.
> 
> 
> Libreboot builds coreboot without the .git directory, so it's not 
> possible to get the coreboot revision. You can find out what
> version of coreboot it is by looking at 
> resources/scripts/helpers/download/coreboot
> 
> He is using libreboot 20150518, so the coreboot revision that he's 
> using is e19c8b0091022ae3f490601aed0c290cd5171b79
> 
> See 
> http://git.savannah.gnu.org/cgit/libreboot.git/tree/resources/scripts/helpers/download/coreboot?id=r20150518fix
>
> 
> 

Note: this bug also affects coreboot upstream, using no additional
patches, from the latest version in the "master" branch from
http://review.coreboot.org/coreboot

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBAgAGBQJVmUZmAAoJEP9Ft0z50c+UGw8IAMCziSv5jfp078b9lokEapUb
kuWPtXAGPrAaZN92kaQRRlGPcp5OF0vAJxhpBPQlMBzl7taizhCb0+BSXKVncusY
GL/eXc2eKRt/sYRWCJxM8Eu3uukUH3ybhHLubR/kOmQ1gi2fuzYXbo+qb2ViJ5dZ
+wF+lyIHxj9RxCEY2TvuLO7c0MjdduC3GdUmlp9am7P+5qWbFr22lok0VznkZ54B
QKorLCxrLPrZnmpZJr1rL0UfkgGZ6uurtK6kbMYhdIsOXTlvgvuu22lnjqKr9fJ2
EwcLWAM9ywq8Aph4HyhEMcVCbj2izVdAURTsK7vGUAwaV7R9s2yfVCLcWmr7mXQ=
=71Qg
-----END PGP SIGNATURE-----


From kroms at posteo.be  Sun Jul  5 17:05:12 2015
From: kroms at posteo.be (kroms at posteo.be)
Date: Sun, 05 Jul 2015 17:05:12 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <1436082138.13469.47.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
Message-ID: <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>

Dear Paul,

thank you for looking into the files!

> It might be in the revision file in CBFS.
> 
>     build/cbfstool build/coreboot.rom extract -n revision -f 
> revision.txt

Please find attached the revision.txt.

>> and Linux -> Do you mean the output of dmesg?
> 
> Indeed, that?s one way of getting them. Please provide the output.
> 
It is also attached. I hope the information will help you to get closer 
to the solution.


> PS: It?s quite common to use interleaved posting style [1] on mailing
> lists.
> 
> 
> [1] https://en.wikipedia.org/wiki/Posting_style

Thank you for the hint. I will do so, the next time I am posting a link 
to a mailing-list.

Best Regards,

Kroms
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: output_dmesg
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150705/f0bfee1e/attachment-0001.ksh>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: revision.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150705/f0bfee1e/attachment-0001.txt>

From lynxis at fe80.eu  Sun Jul  5 21:28:59 2015
From: lynxis at fe80.eu (Alexander Couzens)
Date: Sun, 5 Jul 2015 21:28:59 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <559945DA.7080802@gluglug.org.uk>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <559945DA.7080802@gluglug.org.uk>
Message-ID: <20150705212859.68c13470@lazus.yip>

On Sun, 05 Jul 2015 15:57:30 +0100
Francis Rowe <info at gluglug.org.uk> wrote:

> Libreboot builds coreboot without the .git directory, so it's not
> possible to get the coreboot revision. You can find out what version
I don't understand why you're removing the .git directory.
But anyhow, you should patch the coreboot version script. The script should
take your specific version of your libreboot build script git repo.
Please prefix the version with "libreboot", it makes all our live easier to know what version is running and from where the version comes from.
And btw. this makes your coreboot' build reproducible, which isn't it atm.

Best
lynxis
-- 
Alexander Couzens

mail: lynxis at fe80.eu
jabber: lynxis at jabber.ccc.de
mobile: +4915123277221
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150705/dba15108/attachment.sig>

From info at gluglug.org.uk  Sun Jul  5 23:02:38 2015
From: info at gluglug.org.uk (Francis Rowe)
Date: Sun, 05 Jul 2015 22:02:38 +0100
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <20150705212859.68c13470@lazus.yip>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>	<1435958386.5493.61.camel@users.sourceforge.net>	<44e753be1d353223502ddde14a9b668e@posteo.de>	<1436082138.13469.47.camel@users.sourceforge.net>	<559945DA.7080802@gluglug.org.uk>
 <20150705212859.68c13470@lazus.yip>
Message-ID: <55999B6E.7090703@gluglug.org.uk>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

> I don't understand why you're removing the .git directory. But
> anyhow, you should patch the coreboot version script. The script
> should take your specific version of your libreboot build script
> git repo. Please prefix the version with "libreboot", it makes all
> our live easier to know what version is running and from where the
> version comes from. And btw. this makes your coreboot' build
> reproducible, which isn't it atm.

Libreboot removes all of the blobs from coreboot. In doing so, a diff
showing those deletions (therefore, containing the blobs) is shown.
The git history in coreboot also shows blobs that have been added or
deleted, over time.

By not deleting the .git directory, libreboot would be distributing
blobs. That's why it's deleted.

However, your comment is valid; I should patch the build system in
coreboot so that it shows libreboot-<insert revision here> in the
coreboot-libre boot logs (as seen from serial output, EHCI debug
output or cbmem -c). I've added a note for myself, reminding me to do
this.


-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBAgAGBQJVmZtuAAoJEP9Ft0z50c+UW3AH+QGjaH5w/rIEWhKCYvXUDFOj
U6yNgGFT8kkXEWaS+vZY1iVrDdIGbEx9SM27ZXroUWLlIS90XiHyzYGqztJgzfrB
3XaYFI17WYwpoQ5f3OGyF8uycc1JlQQQ8zs7xDZywNNVYR4pJUkXHleaYEOb9k3U
GJ4PdO22fqTcyZH5XZXk0ga0oZp8N3ChLJgA2gy7L0fGfX73VxQL0CvQ/bMdMsOG
hERR4wf7cy4Z6BV1p65lt4Hi60kbEiQ5JpTBawQ80xGUCq2yVyxjJDrY+Pn/1W2l
vHmyeM2iBpAroUEZ0f2XnWH8KDEAkoMiM1H6vu6ZHybGrK/JNqf+Le9AXA5oWfo=
=p9+b
-----END PGP SIGNATURE-----


From 1395158558 at qq.com  Mon Jul  6 12:02:08 2015
From: 1395158558 at qq.com (=?ISO-8859-1?B?RE0zNjU=?=)
Date: Mon, 6 Jul 2015 18:02:08 +0800
Subject: [coreboot] minnowboardmax coreboot intel uefi payload :Failed to
	find the required acpi table
Message-ID: <tencent_010695531FDF3F0F786DA800@qq.com>

Hello!
      I tested intel uefi payload instead of seabios in coreboot minnowboard max .
      It failed with "Failed to find the required acpi table ".
      If I use seabios payload ,the bios runs ok!
      I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to build coreboot.
      I used "https://firmware.intel.com/develop/" 2014-WW26-UEFI.coreboot.Payload.zip to builed uefi in coreboot.
      The whole terminal log is :
   POST: 0x4a
POST: 0x4b
POST: 0x4c
POST: 0x4d
POST: 0x4e
POST: 0x4f
POST: 0x39
POST: 0x80
POST: 0x70
POST: 0x71
POST: 0x72
POST: 0x24
POST: 0x25
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x55
POST: 0x73
APIC: 00 missing read_resources
PCI: 00:00.0 missing set_resources
POST: 0x74
POST: 0x75
POST: 0x75
POST: 0x93
POST: 0x9b
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
Warning: PCI Device 2 does not have an IRQ entry, skipping it
POST: 0x75
POST: 0x75
POST: 0x76
POST: 0x77
find_current_mrc_cache_local: No valid fast boot cache found.
POST: 0x79
POST: 0x9c
POST: 0x9e
POST: 0x9d
POST: 0x7a
POST: 0x7b
POST: 0xf8
PROGRESS CODE: V03020003 I0
Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi
PROGRESS CODE: V03020002 I0
0. 0000000000000000 - 0000000000000FFF [10]
1. 0000000000001000 - 000000000009FFFF [01]
2. 00000000000A0000 - 00000000000FFFFF [02]
3. 0000000000100000 - 000000007ACBCFFF [01]
4. 000000007ACBD000 - 000000007ADFFFFF [10]
5. 000000007AE00000 - 000000007FFFFFFF [02]
6. 00000000E0000000 - 00000000EFFFFFFF [02]
7. 00000000FEB00000 - 00000000FEC00FFF [02]
8. 00000000FED01000 - 00000000FED01FFF [02]
9. 00000000FED03000 - 00000000FED03FFF [02]
10. 00000000FED05000 - 00000000FED05FFF [02]
11. 00000000FED08000 - 00000000FED08FFF [02]
12. 00000000FED0C000 - 00000000FED0FFFF [02]
13. 00000000FED1C000 - 00000000FED1CFFF [02]
14. 00000000FEE00000 - 00000000FEE00FFF [02]
15. 00000000FEF00000 - 00000000FEFFFFFF [02]
16. 00000000FF800000 - 00000000FFFFFFFF [02]
Low memory 0x7ACBD000, High Memory 0x0
LowMemorySize: 0x7ACBD000.
HighMemorySize: 0x0.
PeiMemBase: 0x76CB0000.
PeiMemSize: 0x4000000.
PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
Found one valid fv : 0x820000.
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0
The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000
Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
Actual Coreboot header: 0x7ACBD000.
Failed to find the required acpi table


PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c (338): ((BOOLEAN)(0==1))
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150706/9788eaf6/attachment.html>

From wangsiyuanbuaa at gmail.com  Mon Jul  6 13:31:04 2015
From: wangsiyuanbuaa at gmail.com (WANG Siyuan)
Date: Mon, 6 Jul 2015 19:31:04 +0800
Subject: [coreboot] ACPI resource problem
Message-ID: <CAKhuMPmYN=Ub7F=LqQqGrS0VQCJurT+_AuFCBNt+HUc8KZsm4w@mail.gmail.com>

Hi,
I have a question about acpi resource.

My device need the resource:
    Name(_CRS, ResourceTemplate() {
      IRQ(Edge, ActiveHigh, Exclusive) {3}
      Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
    })
In Win8's device manager, I got error "This device cannot find enough free
resources that it can use."

I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource->flags =
IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED
|  IORESOURCE_ASSIGNED; I still got this error.

I have 2 questions:
1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)?
2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}?

Any replay is appreciated!

Yours sincerely,
WANG Siyuan
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150706/08ac9324/attachment.html>

From pgeorgi at google.com  Mon Jul  6 22:28:57 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Mon, 6 Jul 2015 22:28:57 +0200
Subject: [coreboot] HEADS UP: Bug in automatic testing on gerrit/jenkins
Message-ID: <CAE-gjdW38=Ae46pbqNBJNCeku9FEmpTZhjQpZQANxo-7ouO=Tw@mail.gmail.com>

Hi all,

today I noticed that our test builders at http://qa.coreboot.org/
weren't actually testing the commits that are pending review on
http://review.coreboot.org/ as they were asked to, but (most of the
time) a commit from early-June.

We fixed the issue (Jenkins, the tool that orchestrates
qa.coreboot.org, dropped some configuration value during an update
that we needed to set again), but unfortunately some commits sneaked
in that broke the tree.

Fixes for these bugs are in, but when pushing changes for code review,
the builders may still report errors that are unrelated to your
change. See http://qa.coreboot.org/job/coreboot-gerrit/27371/ for an
example.

That's because the builders use exactly the commit you pushed, without
applying any new changes to it. If you run into that situation, please
rebase your commits to the current master, since (as of a couple of
minutes ago) it includes the bug fixes.

$ git pull
$ git rebase master $your_local_branch
$ git push (as usual)


Sorry for the inconvenience,
Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From wordpress at blogs.coreboot.org  Mon Jul  6 04:52:01 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Mon, 6 Jul 2015 02:52:01 +0000
Subject: [coreboot] New on blogs.coreboot.org: [GSoC] EC/H8S firmware week #5
Message-ID: <be7cf4ffd81ebf4190c1dd1342c5488b@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150706/7673ddc5/attachment-0001.html>

From 1395158558 at qq.com  Tue Jul  7 03:58:46 2015
From: 1395158558 at qq.com (=?ISO-8859-1?B?RE0zNjU=?=)
Date: Tue, 7 Jul 2015 09:58:46 +0800
Subject: [coreboot] minnowboardmax coreboot intel uefi payload :Failed to
	find the required acpi table
Message-ID: <tencent_2FD451C610CCE6504AB1172F@qq.com>

Hello!
      I tested intel uefi payload instead of seabios in coreboot minnowboard max .
      It failed with "Failed to find the required acpi table ".
      If I use seabios payload ,the bios runs ok!
      I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to build coreboot.
      I used "https://firmware.intel.com/develop/" 2014-WW26-UEFI.coreboot.Payload.zip to builed uefi in coreboot.
      The whole terminal log is :
   POST: 0x4a
POST: 0x4b
POST: 0x4c
POST: 0x4d
POST: 0x4e
POST: 0x4f
POST: 0x39
POST: 0x80
POST: 0x70
POST: 0x71
POST: 0x72
POST: 0x24
POST: 0x25
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x55
POST: 0x73
APIC: 00 missing read_resources
PCI: 00:00.0 missing set_resources
POST: 0x74
POST: 0x75
POST: 0x75
POST: 0x93
POST: 0x9b
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
Warning: PCI Device 2 does not have an IRQ entry, skipping it
POST: 0x75
POST: 0x75
POST: 0x76
POST: 0x77
find_current_mrc_cache_local: No valid fast boot cache found.
POST: 0x79
POST: 0x9c
POST: 0x9e
POST: 0x9d
POST: 0x7a
POST: 0x7b
POST: 0xf8
PROGRESS CODE: V03020003 I0
Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi
PROGRESS CODE: V03020002 I0
0. 0000000000000000 - 0000000000000FFF [10]
1. 0000000000001000 - 000000000009FFFF [01]
2. 00000000000A0000 - 00000000000FFFFF [02]
3. 0000000000100000 - 000000007ACBCFFF [01]
4. 000000007ACBD000 - 000000007ADFFFFF [10]
5. 000000007AE00000 - 000000007FFFFFFF [02]
6. 00000000E0000000 - 00000000EFFFFFFF [02]
7. 00000000FEB00000 - 00000000FEC00FFF [02]
8. 00000000FED01000 - 00000000FED01FFF [02]
9. 00000000FED03000 - 00000000FED03FFF [02]
10. 00000000FED05000 - 00000000FED05FFF [02]
11. 00000000FED08000 - 00000000FED08FFF [02]
12. 00000000FED0C000 - 00000000FED0FFFF [02]
13. 00000000FED1C000 - 00000000FED1CFFF [02]
14. 00000000FEE00000 - 00000000FEE00FFF [02]
15. 00000000FEF00000 - 00000000FEFFFFFF [02]
16. 00000000FF800000 - 00000000FFFFFFFF [02]
Low memory 0x7ACBD000, High Memory 0x0
LowMemorySize: 0x7ACBD000.
HighMemorySize: 0x0.
PeiMemBase: 0x76CB0000.
PeiMemSize: 0x4000000.
PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
Found one valid fv : 0x820000.
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0
The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000
Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
Actual Coreboot header: 0x7ACBD000.
Failed to find the required acpi table


PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c (338): ((BOOLEAN)(0==1))
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150707/71543c86/attachment.html>

From caoducquan at gmail.com  Tue Jul  7 11:32:22 2015
From: caoducquan at gmail.com (Cao Duc Quan)
Date: Tue, 7 Jul 2015 16:32:22 +0700
Subject: [coreboot] How to build SPI ROM 8MB image
Message-ID: <CAJPUe9os9HYwVzjfJ7QPZm=2WrRXT2bpbTUkK91kmnZLaK68dg@mail.gmail.com>

Dear all,
I am trying to make coreboot work on BayTrail-I SoC E3845.
I wonder if anyone could build the SPI ROM 8MB image with coreboot? I found
that I got 2MB image with normal building so I have to flash two times
SPI.rom first then flash coreboot.rom.

Many Thanks,
-- 
Quan Cao
0976574864
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150707/947ba37e/attachment.html>

From wangfei.jimei at gmail.com  Tue Jul  7 11:39:21 2015
From: wangfei.jimei at gmail.com (WANG FEI)
Date: Tue, 7 Jul 2015 10:39:21 +0100
Subject: [coreboot] How to build SPI ROM 8MB image
In-Reply-To: <CAJPUe9os9HYwVzjfJ7QPZm=2WrRXT2bpbTUkK91kmnZLaK68dg@mail.gmail.com>
References: <CAJPUe9os9HYwVzjfJ7QPZm=2WrRXT2bpbTUkK91kmnZLaK68dg@mail.gmail.com>
Message-ID: <CAGH0wH3rpSe=pRoZ1Ogp1up2Ck6Jo-dTiXrV+s9RFg3hq-WhfA@mail.gmail.com>

Update BOARD_ROMSIZE_KB_2048 in src\mainboard\intel\bayleybay_fsp\Kconfig
to BOARD_ROMSIZE_KB_8192, re-generate .config and make sure .config the ROM
size is 8MB, now you can run make to generate 8MB ROM.

On Tue, Jul 7, 2015 at 10:32 AM, Cao Duc Quan <caoducquan at gmail.com> wrote:

> Dear all,
> I am trying to make coreboot work on BayTrail-I SoC E3845.
> I wonder if anyone could build the SPI ROM 8MB image with coreboot? I
> found that I got 2MB image with normal building so I have to flash two
> times SPI.rom first then flash coreboot.rom.
>
> Many Thanks,
> --
> Quan Cao
> 0976574864
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150707/1670e0a8/attachment.html>

From wangfei.jimei at gmail.com  Tue Jul  7 13:22:05 2015
From: wangfei.jimei at gmail.com (WANG FEI)
Date: Tue, 7 Jul 2015 12:22:05 +0100
Subject: [coreboot] ACPI resource problem
In-Reply-To: <CAKhuMPmYN=Ub7F=LqQqGrS0VQCJurT+_AuFCBNt+HUc8KZsm4w@mail.gmail.com>
References: <CAKhuMPmYN=Ub7F=LqQqGrS0VQCJurT+_AuFCBNt+HUc8KZsm4w@mail.gmail.com>
Message-ID: <CAGH0wH3R1hPK8SsFKFZdp72V=+bd3chCztxtjtAvWudT7ZnVpA@mail.gmail.com>

Siyuan, did you reserved 0xFEDC2000 - 0xFEDC2FFF in ASL file? what you've
done in your code is to reserve this MMIO area in E820 table, OS will not
take this area, but it's not enough for ACPI.

Here is a sample to reserve MMIO area in asl file.

// TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000,,, TPMR)

On Mon, Jul 6, 2015 at 12:31 PM, WANG Siyuan <wangsiyuanbuaa at gmail.com>
wrote:

> Hi,
> I have a question about acpi resource.
>
> My device need the resource:
>     Name(_CRS, ResourceTemplate() {
>       IRQ(Edge, ActiveHigh, Exclusive) {3}
>       Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
>     })
> In Win8's device manager, I got error "This device cannot find enough free
> resources that it can use."
>
> I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource->flags =
> IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED
> |  IORESOURCE_ASSIGNED; I still got this error.
>
> I have 2 questions:
> 1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)?
> 2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}?
>
> Any replay is appreciated!
>
> Yours sincerely,
> WANG Siyuan
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150707/4c0d7b69/attachment.html>

From wangfei.jimei at gmail.com  Tue Jul  7 13:26:55 2015
From: wangfei.jimei at gmail.com (WANG FEI)
Date: Tue, 7 Jul 2015 12:26:55 +0100
Subject: [coreboot] minnowboardmax coreboot intel uefi payload :Failed
 to find the required acpi table
In-Reply-To: <tencent_2FD451C610CCE6504AB1172F@qq.com>
References: <tencent_2FD451C610CCE6504AB1172F@qq.com>
Message-ID: <CAGH0wH1bpyG7AAvOsHNjfL-qXFSY48DSfPdEDtscimMrxoF8LQ@mail.gmail.com>

My understanding is that your coreboot does not have ACPI table, you
possible 1) add ACPI support in coreboot, or 2) modify UEFI payload to
remove the assert if ACPI table not exist, or 3) trying the latest coreboot
package from edk2 source tree.

On Tue, Jul 7, 2015 at 2:58 AM, DM365 <1395158558 at qq.com> wrote:

> Hello!
>       I tested intel uefi payload instead of seabios in coreboot
> minnowboard max .
>       It failed with "Failed to find the required acpi table ".
>       If I use seabios payload ,the bios runs ok!
>       I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to
> build coreboot.
>       I used "https://firmware.intel.com/develop/"
> 2014-WW26-UEFI.coreboot.Payload.zip
> <https://firmware.intel.com/sites/default/files/2014-WW26-UEFI.CoreBoot.Payload.zip> to
> builed uefi in coreboot.
> <https://firmware.intel.com/sites/default/files/2014-WW26-UEFI.CoreBoot.Payload.zip>
>       The whole terminal log is :
>    POST: 0x4a
> POST: 0x4b
> POST: 0x4c
> POST: 0x4d
> POST: 0x4e
> POST: 0x4f
> POST: 0x39
> POST: 0x80
> POST: 0x70
> POST: 0x71
> POST: 0x72
> POST: 0x24
> POST: 0x25
> POST: 0x24
> POST: 0x25
> POST: 0x55
> POST: 0x24
> POST: 0x25
> POST: 0x55
> POST: 0x55
> POST: 0x73
> APIC: 00 missing read_resources
> PCI: 00:00.0 missing set_resources
> POST: 0x74
> POST: 0x75
> POST: 0x75
> POST: 0x93
> POST: 0x9b
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> Warning: PCI Device 2 does not have an IRQ entry, skipping it
> POST: 0x75
> POST: 0x75
> POST: 0x76
> POST: 0x77
> find_current_mrc_cache_local: No valid fast boot cache found.
> POST: 0x79
> POST: 0x9c
> POST: 0x9e
> POST: 0x9d
> POST: 0x7a
> POST: 0x7b
> POST: 0xf8
> PROGRESS CODE: V03020003 I0
> Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi
> PROGRESS CODE: V03020002 I0
> 0. 0000000000000000 - 0000000000000FFF [10]
> 1. 0000000000001000 - 000000000009FFFF [01]
> 2. 00000000000A0000 - 00000000000FFFFF [02]
> 3. 0000000000100000 - 000000007ACBCFFF [01]
> 4. 000000007ACBD000 - 000000007ADFFFFF [10]
> 5. 000000007AE00000 - 000000007FFFFFFF [02]
> 6. 00000000E0000000 - 00000000EFFFFFFF [02]
> 7. 00000000FEB00000 - 00000000FEC00FFF [02]
> 8. 00000000FED01000 - 00000000FED01FFF [02]
> 9. 00000000FED03000 - 00000000FED03FFF [02]
> 10. 00000000FED05000 - 00000000FED05FFF [02]
> 11. 00000000FED08000 - 00000000FED08FFF [02]
> 12. 00000000FED0C000 - 00000000FED0FFFF [02]
> 13. 00000000FED1C000 - 00000000FED1CFFF [02]
> 14. 00000000FEE00000 - 00000000FEE00FFF [02]
> 15. 00000000FEF00000 - 00000000FEFFFFFF [02]
> 16. 00000000FF800000 - 00000000FFFFFFFF [02]
> Low memory 0x7ACBD000, High Memory 0x0
> LowMemorySize: 0x7ACBD000.
> HighMemorySize: 0x0.
> PeiMemBase: 0x76CB0000.
> PeiMemSize: 0x4000000.
> PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
> Found one valid fv : 0x820000.
> Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
> Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry
> point: 801BC0
> The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is
> 0x820000
> Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
> Actual Coreboot header: 0x7ACBD000.
> Failed to find the required acpi table
>
> PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c
> (338): ((BOOLEAN)(0==1))
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150707/f8474324/attachment.html>

From no-reply at raptorengineeringinc.com  Wed Jul  8 10:00:26 2015
From: no-reply at raptorengineeringinc.com (Raptor Engineering Automated Coreboot Test Stand)
Date: Wed, 8 Jul 2015 03:00:26 -0500
Subject: [coreboot] ASUS KFSN4-DRE Automated Test Failure
Message-ID: <20150708080026.GA23427@cb-test-ctl>

The ASUS KFSN4-DRE fails verification as of commit 2941b28080fff82503484a99c3fa740a01bb30cc

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
2941b28 toolchain.inc: Don't overwrite architecture specific CFLAGS
8e39975 memlayout: Add timestamp regions for t210 and cygnus

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand
Want to test on your own equipment?  Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit https://www.raptorengineeringinc.com for more information

Please contact Timothy Pearson at Raptor Engineering <tpearson at raptorengineeringinc.com> regarding any issues stemming from this notification
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 1436342414-0-automaster.log.bz2
Type: application/octet-stream
Size: 29603 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150708/d73b75c7/attachment-0001.obj>

From ilios86 at gmail.com  Wed Jul  8 13:47:19 2015
From: ilios86 at gmail.com (YongGon Kim)
Date: Wed, 8 Jul 2015 20:47:19 +0900
Subject: [coreboot] Kernel couldn't find proper MAC address with coreboot
	(gigabyte ma785gmt-ud2h)
Message-ID: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>

I have used coreboot and successfully boot ubuntu 14.04 (only console
mode).
But kernel couldn't find proper MAC address and only ff:ff:ff:ff:ff:ff is
printed.

When kernel is booted, r8169 module is successfully loaded but
it failed to find proper MAC address with following messages.

[    1.165748] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
[    1.165850] r8169 0000:04:00.0: can't disable ASPM; OS doesn't have ASPM
control
[    1.166010] r8169 0000:04:00.0 (unregistered net_device): unknown MAC,
using family default
[    1.176236] r8169 0000:04:00.0 (unregistered net_device):
rtl_chipcmd_cond == 1 (loop: 100, delay: 100).
[    1.176448] r8169 0000:04:00.0: irq 43 for MSI/MSI-X
[    1.176609] r8169 0000:04:00.0 eth0: RTL8168b/8111b at
0xffffc900003ac000, ff:ff:ff:ff:ff:ff, XID 9cf0f8ff IRQ 43
[    1.176732] r8169 0000:04:00.0 eth0: jumbo features [frames: 4080 bytes,
tx checksumming: ko]


I found that, with normal BIOS, MAC address are located within PCI I/O
memory space pointed by 2nd base address register of ethernet PCI device.
But with coreboot, memory space pointed by 2nd BAR of ethernet device
only contains 0xff.

I tried to figure out how PCI I/O memory space is initialized and
allocated,
but i'm stuck now and need some helps.
I only found some hints in kernel log that following messages are only
shown with coreboot booting for ethernet pci device.
...
[    0.120164] pci 0000:04:00.0: no compatible bridge window for [mem
0xc8010000-0xc8010fff 64bit pref]
[    0.120164] pci 0000:04:00.0: no compatible bridge window for [mem
0xc8000000-0xc800ffff 64bit pref]
...
[    0.271531] pci 0000:04:00.0: BAR 4: can't assign mem pref (size 0x10000)
[    0.271620] pci 0000:04:00.0: BAR 4: trying firmware assignment [mem
0xc8000000-0xc800ffff 64bit pref]
[    0.271724] pci 0000:04:00.0: BAR 4: assigned [mem 0xc8000000-0xc800ffff
64bit pref]
...

Is there anyone who knows how to handle this situation?
It's okay for me to update kernel source (e.g. r8169 module) instead of
coreboot source code.
I just want to know what the problem is and any possible way to resolve it.


I'm using GIGABYTE GA-MA785GMT-UD2H (rev 1.1) with external graphic card
(nvida GTS 250).
I have uploaded detailed information using board_status.sh
Following is link for the information.
http://review.coreboot.org/gitweb?p=board-status.git;a=commit;h=dedf456d25748368da19d556828c7ef95e3f3073


Thank you.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150708/de89c231/attachment.html>

From philbyjohn at gmail.com  Wed Jul  8 15:00:22 2015
From: philbyjohn at gmail.com (philby john)
Date: Wed, 8 Jul 2015 18:30:22 +0530
Subject: [coreboot] build coreboot for Braswell soc
Message-ID: <CAJYP-=DjEoLxduVS6WFxVOaL9uP1ZHPePqB060oNU7gx8yHrHw@mail.gmail.com>

Hello,

My intention is to build coreboot for the Braswell soc. But looking at
src/Kconfig I realize none of the soc code (baytrail, braswell, broadwell)
can be compiled because the path to respective Kconfig soc's (source
"src/soc/*/*/Kconfig") have not been defined. Also the qa build environment
at qa.coreboot.org does not seem to build for Braswell.

Can someone please guide me on the procedure to compile the Braswell SoC
platform?

Thanks and regards,
Philby
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150708/499735f4/attachment.html>

From vidwer at gmail.com  Wed Jul  8 15:59:04 2015
From: vidwer at gmail.com (Idwer Vollering)
Date: Wed, 8 Jul 2015 15:59:04 +0200
Subject: [coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems incomplete?
Message-ID: <CAPp9OrkeBjTykLXPxXw3LKd8g7_XcEtq7aUrxVBunwWjsmqR9g@mail.gmail.com>

Board: asus/f2a85-m

In "AMD Bolton FCH Register Reference Guide" (51192), page 2-154, this
register "Interrupt Line ? RW ? 32 bits - [PCI_Reg:3Ch]" is 0x12/0x11
while having booted the vendor binary and 0xff/0xff when having booted
coreboot.

Could the erratic value cause SeaBIOS boot issues? See
http://www.coreboot.org/pipermail/seabios/2014-June/008148.html and
http://www.coreboot.org/pipermail/seabios/2014-June/008150.html

lspci -s 10.{0,1} -nnvvvxx output follows.

vendor binary:
00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
    Subsystem: ASUSTeK Computer Inc. Device [1043:8527]
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 18
    Region 0: Memory at fef4a000 (64-bit, non-prefetchable)
    Capabilities: [50] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
        Address: 00000000fee13000  Data: 0031
    Capabilities: [90] MSI-X: Enable- Count=8 Masked-
        Vector table: BAR=0 offset=00001000
        PBA: BAR=0 offset=00001080
    Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
        DevCap:    MaxPayload 128 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
OBFF Disabled
00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00
10: 04 a0 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85
30: 00 00 00 00 50 00 00 00 00 00 00 00 12 01 00 00
40: 00 00 00 00 00 00 00 00 88 00 00 00 08 77 76 76
50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 87 00 00 30 e1 fe 00 00 00 00 31 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00

00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
    Subsystem: ASUSTeK Computer Inc. Device [1043:8527]
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin B routed to IRQ 17
    Region 0: Memory at fef48000 (64-bit, non-prefetchable)
    Capabilities: [50] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
        Address: 00000000fee10000  Data: 0034
    Capabilities: [90] MSI-X: Enable- Count=8 Masked-
        Vector table: BAR=0 offset=00001000
        PBA: BAR=0 offset=00001080
    Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
        DevCap:    MaxPayload 128 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
OBFF Disabled
00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00
10: 04 80 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85
30: 00 00 00 00 50 00 00 00 00 00 00 00 11 02 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 66 00
50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 87 00 00 00 e1 fe 00 00 00 00 34 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00

coreboot:
00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
    Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI
Controller [1022:7812]
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin A routed to IRQ 255
    Region 0: Memory at f0148000 (64-bit, non-prefetchable)
    Capabilities: [50] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
        Address: 00000000fee10000  Data: 0033
    Capabilities: [90] MSI-X: Enable- Count=8 Masked-
        Vector table: BAR=0 offset=00001000
        PBA: BAR=0 offset=00001080
    Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
        DevCap:    MaxPayload 128 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
OBFF Disabled
00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00
10: 04 80 14 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00
50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 87 00 00 00 e1 fe 00 00 00 00 33 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00

00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
    Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI
Controller [1022:7812]
    Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx+
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
    Latency: 0, Cache Line Size: 64 bytes
    Interrupt: pin B routed to IRQ 255
    Region 0: Memory at f014a000 (64-bit, non-prefetchable)
    Capabilities: [50] Power Management version 3
        Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
PME(D0+,D1-,D2-,D3hot+,D3cold+)
        Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
    Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
        Address: 00000000fee11000  Data: 0032
    Capabilities: [90] MSI-X: Enable- Count=8 Masked-
        Vector table: BAR=0 offset=00001000
        PBA: BAR=0 offset=00001080
    Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
        DevCap:    MaxPayload 128 bytes, PhantFunc 0
            ExtTag- RBE+
        DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
            RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
            MaxPayload 128 bytes, MaxReadReq 512 bytes
        DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
        DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
OBFF Not Supported
        DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
OBFF Disabled
00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00
10: 04 a0 14 f0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78
30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 02 00 00
40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00
50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 87 00 00 10 e1 fe 00 00 00 00 32 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00


From pgeorgi at google.com  Wed Jul  8 16:24:55 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Wed, 8 Jul 2015 16:24:55 +0200
Subject: [coreboot] Fwd:  build coreboot for Braswell soc
In-Reply-To: <CAE-gjdXp=Vwj58ue9XasOO6dsdeghZupbfSVP63nq1OTE20=bg@mail.gmail.com>
References: <CAJYP-=DjEoLxduVS6WFxVOaL9uP1ZHPePqB060oNU7gx8yHrHw@mail.gmail.com>
 <CAE-gjdXp=Vwj58ue9XasOO6dsdeghZupbfSVP63nq1OTE20=bg@mail.gmail.com>
Message-ID: <CAE-gjdUtDJjjzEji97Visk5VT7dPhvhLehFBb9fhkaggi1jUbQ@mail.gmail.com>

2015-07-08 15:00 GMT+02:00 philby john <philbyjohn at gmail.com>:
> But looking at
> src/Kconfig I realize none of the soc code (baytrail, braswell, broadwell)
> can be compiled because the path to respective Kconfig soc's (source
> "src/soc/*/*/Kconfig") have not been defined.
I don't understand what you're saying here.
Kconfig includes all src/soc/*/*/Kconfig in src/Kconfig, line 375.
The build system includes all src/soc/*/*/Makefile.inc in Makefile.inc, line 57.

What's missing?

> Also the qa build environment at qa.coreboot.org does not seem to build for Braswell.
That's because there is no board using Braswell in the repository.
(git grep SOC_INTEL_BRASWELL src/mainboard doesn't return anything)


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From vidwer at gmail.com  Wed Jul  8 16:49:03 2015
From: vidwer at gmail.com (Idwer Vollering)
Date: Wed, 8 Jul 2015 16:49:03 +0200
Subject: [coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems
	incomplete?
In-Reply-To: <CAPp9OrkeBjTykLXPxXw3LKd8g7_XcEtq7aUrxVBunwWjsmqR9g@mail.gmail.com>
References: <CAPp9OrkeBjTykLXPxXw3LKd8g7_XcEtq7aUrxVBunwWjsmqR9g@mail.gmail.com>
Message-ID: <CAPp9Or=EonHW37ynO0V2Er+YMWwoLMPO1RFtDb+aPD_zXTVzng@mail.gmail.com>

Subject should read "Re: Hudson-D4 (A85X): IRQ routing of XHCI seems
incomplete?"

2015-07-08 15:59 GMT+02:00 Idwer Vollering <vidwer at gmail.com>:
> Board: asus/f2a85-m
>
> In "AMD Bolton FCH Register Reference Guide" (51192), page 2-154, this
> register "Interrupt Line ? RW ? 32 bits - [PCI_Reg:3Ch]" is 0x12/0x11
> while having booted the vendor binary and 0xff/0xff when having booted
> coreboot.

This is about hudson, not bolton..
Unfortunately its RRG/RPR/databook is not public :(
http://support.amd.com/en-us/search/tech-docs#k=a85x

>
> Could the erratic value cause SeaBIOS boot issues? See
> http://www.coreboot.org/pipermail/seabios/2014-June/008148.html and
> http://www.coreboot.org/pipermail/seabios/2014-June/008150.html
>
> lspci -s 10.{0,1} -nnvvvxx output follows.
>
> vendor binary:
> 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
> USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
>     Subsystem: ASUSTeK Computer Inc. Device [1043:8527]
>     Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx+
>     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>     Latency: 0, Cache Line Size: 64 bytes
>     Interrupt: pin A routed to IRQ 18
>     Region 0: Memory at fef4a000 (64-bit, non-prefetchable)
>     Capabilities: [50] Power Management version 3
>         Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0+,D1-,D2-,D3hot+,D3cold+)
>         Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>     Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
>         Address: 00000000fee13000  Data: 0031
>     Capabilities: [90] MSI-X: Enable- Count=8 Masked-
>         Vector table: BAR=0 offset=00001000
>         PBA: BAR=0 offset=00001080
>     Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
>         DevCap:    MaxPayload 128 bytes, PhantFunc 0
>             ExtTag- RBE+
>         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
>             MaxPayload 128 bytes, MaxReadReq 512 bytes
>         DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
>         DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
> OBFF Not Supported
>         DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
> OBFF Disabled
> 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00
> 10: 04 a0 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85
> 30: 00 00 00 00 50 00 00 00 00 00 00 00 12 01 00 00
> 40: 00 00 00 00 00 00 00 00 88 00 00 00 08 77 76 76
> 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
> 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 05 90 87 00 00 30 e1 fe 00 00 00 00 31 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
> a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> 00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
> USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
>     Subsystem: ASUSTeK Computer Inc. Device [1043:8527]
>     Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx+
>     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>     Latency: 0, Cache Line Size: 64 bytes
>     Interrupt: pin B routed to IRQ 17
>     Region 0: Memory at fef48000 (64-bit, non-prefetchable)
>     Capabilities: [50] Power Management version 3
>         Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0+,D1-,D2-,D3hot+,D3cold+)
>         Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>     Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
>         Address: 00000000fee10000  Data: 0034
>     Capabilities: [90] MSI-X: Enable- Count=8 Masked-
>         Vector table: BAR=0 offset=00001000
>         PBA: BAR=0 offset=00001080
>     Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
>         DevCap:    MaxPayload 128 bytes, PhantFunc 0
>             ExtTag- RBE+
>         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
>             MaxPayload 128 bytes, MaxReadReq 512 bytes
>         DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
>         DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
> OBFF Not Supported
>         DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
> OBFF Disabled
> 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00
> 10: 04 80 f4 fe 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 27 85
> 30: 00 00 00 00 50 00 00 00 00 00 00 00 11 02 00 00
> 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 66 00
> 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
> 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 05 90 87 00 00 00 e1 fe 00 00 00 00 34 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
> a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> coreboot:
> 00:10.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
> USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
>     Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI
> Controller [1022:7812]
>     Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx+
>     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>     Latency: 0, Cache Line Size: 64 bytes
>     Interrupt: pin A routed to IRQ 255
>     Region 0: Memory at f0148000 (64-bit, non-prefetchable)
>     Capabilities: [50] Power Management version 3
>         Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0+,D1-,D2-,D3hot+,D3cold+)
>         Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>     Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
>         Address: 00000000fee10000  Data: 0033
>     Capabilities: [90] MSI-X: Enable- Count=8 Masked-
>         Vector table: BAR=0 offset=00001000
>         PBA: BAR=0 offset=00001080
>     Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
>         DevCap:    MaxPayload 128 bytes, PhantFunc 0
>             ExtTag- RBE+
>         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
>             MaxPayload 128 bytes, MaxReadReq 512 bytes
>         DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
>         DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
> OBFF Not Supported
>         DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
> OBFF Disabled
> 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 80 00
> 10: 04 80 14 f0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78
> 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00
> 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00
> 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
> 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 05 90 87 00 00 00 e1 fe 00 00 00 00 33 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
> a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> 00:10.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] FCH
> USB XHCI Controller [1022:7812] (rev 03) (prog-if 30 [XHCI])
>     Subsystem: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI
> Controller [1022:7812]
>     Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop-
> ParErr- Stepping- SERR- FastB2B- DisINTx+
>     Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>     Latency: 0, Cache Line Size: 64 bytes
>     Interrupt: pin B routed to IRQ 255
>     Region 0: Memory at f014a000 (64-bit, non-prefetchable)
>     Capabilities: [50] Power Management version 3
>         Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0+,D1-,D2-,D3hot+,D3cold+)
>         Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>     Capabilities: [70] MSI: Enable+ Count=1/8 Maskable- 64bit+
>         Address: 00000000fee11000  Data: 0032
>     Capabilities: [90] MSI-X: Enable- Count=8 Masked-
>         Vector table: BAR=0 offset=00001000
>         PBA: BAR=0 offset=00001080
>     Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 00
>         DevCap:    MaxPayload 128 bytes, PhantFunc 0
>             ExtTag- RBE+
>         DevCtl:    Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>             RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
>             MaxPayload 128 bytes, MaxReadReq 512 bytes
>         DevSta:    CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
>         DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+,
> OBFF Not Supported
>         DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-,
> OBFF Disabled
> 00: 22 10 12 78 06 04 10 00 03 30 03 0c 10 00 00 00
> 10: 04 a0 14 f0 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 12 78
> 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 02 00 00
> 40: 00 00 00 00 00 00 00 00 04 00 00 00 11 01 ff 00
> 50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
> 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 05 90 87 00 00 10 e1 fe 00 00 00 00 32 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00
> a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00


From nico at nicorikken.eu  Wed Jul  8 22:35:16 2015
From: nico at nicorikken.eu (Nico Rikken)
Date: Wed, 08 Jul 2015 22:35:16 +0200
Subject: [coreboot] Req: FOSS-restricting firmware hints
Message-ID: <1436387716.1109.46.camel@nicorikken.eu>

Dear ARM-netbook and Coreboot readers,

In FSFE context we're looking for examples regarding firmware
restrictions on modern computer hardware. This so that we can shed light
on the difficult situation you are all too familiar with. Examples are:

- Trusted Platform Module (TPM) chips
- Secure Boot
- Intel
  - Management Engine
  - Advanced Management Technology
  - Boot Guard

It will be great if you can add some from the top of your head, ideally
including some references. I'll be doing my own research as well, but
your hints will greatly help this process.

Kind regards,
Nico Rikken
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 213 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150708/02b6f5c4/attachment.asc>

From tpearson at raptorengineeringinc.com  Wed Jul  8 22:48:08 2015
From: tpearson at raptorengineeringinc.com (Timothy Pearson)
Date: Wed, 08 Jul 2015 15:48:08 -0500
Subject: [coreboot] Req: FOSS-restricting firmware hints
In-Reply-To: <1436387716.1109.46.camel@nicorikken.eu>
References: <1436387716.1109.46.camel@nicorikken.eu>
Message-ID: <559D8C88.6000102@raptorengineeringinc.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 07/08/2015 03:35 PM, Nico Rikken wrote:
> Dear ARM-netbook and Coreboot readers,
> 
> In FSFE context we're looking for examples regarding firmware
> restrictions on modern computer hardware. This so that we can shed light
> on the difficult situation you are all too familiar with. Examples are:
> 
> - Trusted Platform Module (TPM) chips
> - Secure Boot
> - Intel
>   - Management Engine
>   - Advanced Management Technology
>   - Boot Guard
> 
> It will be great if you can add some from the top of your head, ideally
> including some references. I'll be doing my own research as well, but
> your hints will greatly help this process.
> 
> Kind regards,
> Nico Rikken
> 

AMD's Platform Security Processor (PSP) is another example -- the x86
portion of the processor won't start unless the PSP says it's OK, and
the PSP firmware is signed such that it cannot be replaced with a free
software equivalent.

- -- 
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645
http://www.raptorengineeringinc.com
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQEcBAEBAgAGBQJVnYyGAAoJEK+E3vEXDOFbOVEH/j+qjA/YFO23my05VL1RS1Za
ZvKWopkCws3bYNqf3cd6g6z342tywJZ3LXA+9YAcCEWgMfbCYaLLycObHsTlK9Yy
yY+x98Fa7474E/SREkb+B7nRmQ8hwVawS0UmsLqYbkHnZmnUW8GnhSrp2B8ZZG3v
sNK2TVhJbxIcGuw7MF9AFqzJ/dFN1mk/NHIVagDArwQXXWRtt2h4l3M6e97F3Jhi
tio2VjPzPRvxHnB0qv0BnhtpTDn1yTafV1zCmZdv7qVPQHCWIsp2N7h9v5XwVtYO
3mfXcYUjjSyBJHNpAJjRbUcmaD1fCLAJw0NDRfFnJ9oelyMljAW/2ACdHtA90MU=
=djPw
-----END PGP SIGNATURE-----


From r.marek at assembler.cz  Thu Jul  9 00:26:12 2015
From: r.marek at assembler.cz (Rudolf Marek)
Date: Thu, 09 Jul 2015 00:26:12 +0200
Subject: [coreboot] Hudson-D4 (A88X): IRQ routing of XHCI seems
	incomplete?
In-Reply-To: <CAPp9OrkeBjTykLXPxXw3LKd8g7_XcEtq7aUrxVBunwWjsmqR9g@mail.gmail.com>
References: <CAPp9OrkeBjTykLXPxXw3LKd8g7_XcEtq7aUrxVBunwWjsmqR9g@mail.gmail.com>
Message-ID: <559DA384.50709@assembler.cz>

Hi

>
> In "AMD Bolton FCH Register Reference Guide" (51192), page 2-154, this
> register "Interrupt Line ? RW ? 32 bits - [PCI_Reg:3Ch]" is 0x12/0x11
> while having booted the vendor binary and 0xff/0xff when having booted
> coreboot.

Well this register is used only by OS when MPTABLE/ACPI PCI routing fails. The
register is only a storage, it does not drive any logic.Btw 12/11 is wrong as
PCI specs says it can be 0-15 range.

So the issues must be something else.

Thanks
Rudolf



From peter at stuge.se  Thu Jul  9 00:41:22 2015
From: peter at stuge.se (Peter Stuge)
Date: Thu, 9 Jul 2015 00:41:22 +0200
Subject: [coreboot] Req: FOSS-restricting firmware hints
In-Reply-To: <1436387716.1109.46.camel@nicorikken.eu>
References: <1436387716.1109.46.camel@nicorikken.eu>
Message-ID: <20150708224122.30118.qmail@stuge.se>

Nico Rikken wrote:
> - Intel
>   - Management Engine
>   - Advanced Management Technology

I think you are confusing these two terms. Please read the book
http://www.apress.com/9781430265719 to learn about Intel's platform
security technology.


//Peter


From 1395158558 at qq.com  Thu Jul  9 04:36:09 2015
From: 1395158558 at qq.com (=?gb18030?B?RE0zNjU=?=)
Date: Thu, 9 Jul 2015 10:36:09 +0800
Subject: [coreboot] =?gb18030?q?RE=A3=BA__minnowboardmax_coreboot_intel_ue?=
 =?gb18030?q?fi_payload_=3AFailedto_find_the_required_acpi_table?=
In-Reply-To: <CAGH0wH1bpyG7AAvOsHNjfL-qXFSY48DSfPdEDtscimMrxoF8LQ@mail.gmail.com>
References: <tencent_2FD451C610CCE6504AB1172F@qq.com>
 <CAGH0wH1bpyG7AAvOsHNjfL-qXFSY48DSfPdEDtscimMrxoF8LQ@mail.gmail.com>
Message-ID: <tencent_3C71D443673588841038DC85@qq.com>

I try the latest coreboot package from edk2.
The acpi table is ok,but there is new question."ERROR: C00000002:V03058002 I0 FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F 7A801AD8".
The whole log is :
POST: 0x4a
POST: 0x4b
POST: 0x4c
POST: 0x4d
POST: 0x4e
POST: 0x4f
POST: 0x39
POST: 0x80
POST: 0x70
POST: 0x71
POST: 0x72
POST: 0x24
POST: 0x25
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x55
POST: 0x73
APIC: 00 missing read_resources
PCI: 00:00.0 missing set_resources
POST: 0x74
POST: 0x75
POST: 0x75
POST: 0x93
POST: 0x9b
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
Warning: PCI Device 2 does not have an IRQ entry, skipping it
POST: 0x75
POST: 0x75
POST: 0x76
POST: 0x77
find_current_mrc_cache_local: No valid fast boot cache found.
POST: 0x79
POST: 0x9c
POST: 0x9e
POST: 0x9d
POST: 0x7a
POST: 0x7b
POST: 0xf8
PROGRESS CODE: V03020003 I0
Loading PEIM at 0x0000080F4A0 EntryPoint=0x0000080F700 CbSupportPeim.efi
PROGRESS CODE: V03020002 I0
0. 0000000000000000 - 0000000000000FFF [10]
1. 0000000000001000 - 000000000009FFFF [01]
2. 00000000000A0000 - 00000000000FFFFF [02]
3. 0000000000100000 - 000000007ACBCFFF [01]
4. 000000007ACBD000 - 000000007ADFFFFF [10]
5. 000000007AE00000 - 000000007FFFFFFF [02]
6. 00000000E0000000 - 00000000EFFFFFFF [02]
7. 00000000FEB00000 - 00000000FEC00FFF [02]
8. 00000000FED01000 - 00000000FED01FFF [02]
9. 00000000FED03000 - 00000000FED03FFF [02]
10. 00000000FED05000 - 00000000FED05FFF [02]
11. 00000000FED08000 - 00000000FED08FFF [02]
12. 00000000FED0C000 - 00000000FED0FFFF [02]
13. 00000000FED1C000 - 00000000FED1CFFF [02]
14. 00000000FEE00000 - 00000000FEE00FFF [02]
15. 00000000FEF00000 - 00000000FEFFFFFF [02]
16. 00000000FF800000 - 00000000FFFFFFFF [02]
Low memory 0x7ACBD000, High Memory 0x0
LowMemorySize: 0x7ACBD000.
HighMemorySize: 0x0.
PeiMemBase: 0x76CB0000.
PeiMemSize: 0x4000000.
PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
Found one valid fv : 0x3E000000830000.
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801C77
The 1th FV start address is 0x00000830000, size is 0x003E0000, handle is 0x830000
Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
Actual Coreboot header: 7ACBD000.
Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x24000
Find CbMemTable Id 0x534D4254, base 7ACC5000, size 0x800
Detected Acpi Table at 0x7ACD6000, length 0x24000
Detected Smbios Table at 0x7ACC5000, length 0x800
Create system table info guid hob
Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x1000
Find Rsdp at 7ACD6000
Find Rsdt 0x7ACD6030, Xsdt 0x7ACD60E0
PmCtrl Reg 0x404
PmTimer Reg 0x408
Reset Reg 0xCF9
Reset Value 0x6
PmEvt Reg 0x400
PmGpeEn Reg 0x424
Create acpi board info guid hob
Found coreboot video frame buffer information
physical_address: 0x0
x_resolution: 0x0
y_resolution: 0x0
bits_per_pixel: 0x0
bytes_per_line: 0x0
red_mask_size: 0x0
red_mask_pos: 0x0
green_mask_size: 0x0
green_mask_pos: 0x0
blue_mask_size: 0x0
blue_mask_pos: 0x0
reserved_mask_size: 0x0
reserved_mask_pos: 0x0
Create frame buffer info guid hob
PROGRESS CODE: V03020003 I0
Temp Stack : BaseAddress=0x88000 Length=0x8000
Temp Heap  : BaseAddress=0x80000 Length=0xD30
Total temporary memory:    65536 bytes.
  temporary memory stack ever used: 32768 bytes.
  temporary memory heap used:       3376 bytes.
Old Stack size 32768, New stack size 131072
Stack Hob: BaseAddress=0x76CB0000 Length=0x20000
Heap Offset = 0x76C50000 Stack Offset = 0x76C40000
Loading PEIM at 0x0007ACA6000 EntryPoint=0x0007ACA6260 PeiCore.efi
Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
Loading PEIM at 0x0007ACA2000 EntryPoint=0x0007ACA2260 DxeIpl.efi
PROGRESS CODE: V03020002 I0
PROGRESS CODE: V03020003 I0
Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
DXE IPL Entry
Loading PEIM at 0x0007AC7F000 EntryPoint=0x0007AC7F2C0 DxeCore.efi
PROGRESS CODE: V03021001 I0
Loading DXE CORE at 0x0007AC7F000 EntryPoint=0x0007AC7F2C0
Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6
PROGRESS CODE: V03040003 I0
Loading driver F80697E9-7FD6-4665-8646-88E33EF71DFC
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A98F040
Loading driver at 0x0007A985000 EntryPoint=0x0007A9852C0 SecurityStubDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98FF18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 94AB2F58-1438-4EF1-9152-18941A3A0E68 7A987428
InstallProtocolInterface: A46423E3-4617-49F1-B9FF-D1BFA9115839 7A987420
PROGRESS CODE: V03040003 I0
Loading driver 1A1E4886-9517-440E-9FDE-3BE44CEE2136
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A98F380
Loading driver at 0x0007A970000 EntryPoint=0x0007A9702C0 CpuDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98FB58
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 26BACCB1-6F42-11D4-BCE7-0080C73C8881 7A979480
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
  Flushing GCD
Detect CPU count: 2
Does not find any HOB stored CPU BIST information!
InstallProtocolInterface: 3FDDA605-A76E-4F46-AD29-12F4531B3D08 7A9793A8
PROGRESS CODE: V03040003 I0
Loading driver C8339973-A563-4561-B858-D8476F9DEFC4
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97C040
Loading driver at 0x0007A97A000 EntryPoint=0x0007A97A2C0 Metronome.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97CF18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 26BACCB2-6F42-11D4-BCE7-0080C73C8881 7A97BA10
PROGRESS CODE: V03040003 I0
Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97C380
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Core\RuntimeDxe\RuntimeDxe\DEBUG\RuntimeDxe.pdb  !!!!!!!!
Loading driver at 0x0007AB83000 EntryPoint=0x0007AB832C0 RuntimeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97CDD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: B7DFB4E1-052F-449F-87BE-9818FC91B733 7AB85100
PROGRESS CODE: V03040003 I0
Loading driver 4B28E4C7-FF36-4E10-93CF-A82159E777C5
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97E0C0
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\ResetSystemRuntimeDxe\ResetSystemRuntimeDxe\DEBUG\ResetSystemRuntimeDxe.pdb  !!!!!!!!
Loading driver at 0x0007AB80000 EntryPoint=0x0007AB802C0 ResetSystemRuntimeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97EED8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 27CFAC88-46CC-11D4-9A38-0090273FC14D 0
PROGRESS CODE: V03040003 I0
Loading driver 02B01AD5-7E59-43E8-A6D8-238180613A5A
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97E540
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\Variable\EmuRuntimeDxe\EmuVariableRuntimeDxe\DEBUG\EmuVariableRuntimeDxe.pdb  !!!!!!!!
Loading driver at 0x0007AB7B000 EntryPoint=0x0007AB7B2C0 EmuVariableRuntimeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97E798
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 1E5668E2-8481-11D4-BCF1-0080C73C8881 0
InstallProtocolInterface: 6441F818-6362-4E44-B570-7DBA31DD2453 0
PROGRESS CODE: V03040003 I0
Loading driver A19B1FE7-C1BC-49F8-875F-54A5D542443F
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97D2C0
Loading driver at 0x0007A96C000 EntryPoint=0x0007A96C2C0 CpuIo2Dxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97DA58
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: AD61F191-AE5F-4C0E-B9FA-E869D288C64F 7A96DC30
PROGRESS CODE: V03040003 I0
Loading driver 9B680FCE-AD6B-4F3A-B60B-F59899003443
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97D740
Loading driver at 0x0007A954000 EntryPoint=0x0007A9542C0 DevicePathDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96FF18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 0379BE4E-D706-437D-B037-EDB82FB772A4 7A95B6E0
InstallProtocolInterface: 8B843E20-8132-4852-90CC-551A4E4A7F1C 7A95B720
InstallProtocolInterface: 05C99A21-C70F-4AD2-8A5F-35DF3343F51E 7A95B730
PROGRESS CODE: V03040003 I0
Loading driver 96B5C032-DF4C-4B6E-8232-438DCF448D0E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96F880
Loading driver at 0x0007A968000 EntryPoint=0x0007A9682C0 NullMemoryTestDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96F098
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 309DE7F1-7F5E-4ACE-B49C-531BE5AA95EF 7A969900
PROGRESS CODE: V03040003 I0
Loading driver 79CA4208-BBA1-4A9A-8456-E1E66A81484E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96E040
Loading driver at 0x0007A966000 EntryPoint=0x0007A9662C0 Legacy8259.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96E2D8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 38321DBA-4FE0-4E17-8AEC-413055EAEDC1 7A9677E0
PROGRESS CODE: V03040003 I0
Loading driver 348C4D62-BFBD-4882-9ECE-C80BB1C4783B
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96EA00
Loading driver at 0x0007A91C000 EntryPoint=0x0007A91C2C0 HiiDatabase.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96ED18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: E9CA4775-8657-47FC-97E7-7ED65A084324 7A935D68
InstallProtocolInterface: 0FD96974-23AA-4CDC-B9CB-98D17750322A 7A935DB0
InstallProtocolInterface: EF9FC172-A1B2-4693-B327-6D32FC416042 7A935DD8
InstallProtocolInterface: 587E72D7-CC50-4F79-8209-CA291FC1A10F 7A935E30
InstallProtocolInterface: 0A8BADD5-03B8-4D19-B128-7B8F0EDAA596 7A935E60
InstallProtocolInterface: 31A6406A-6BDF-4E46-B2A2-EBAA89C40920 7A935D88
PROGRESS CODE: V03040003 I0
Loading driver C68DAA4E-7AB5-41E8-A91D-5954421053F3
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96B200
Loading driver at 0x0007A960000 EntryPoint=0x0007A9602C0 CbSupportDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96B858
PROGRESS CODE: V03040002 I0
Install Acpi Table at 0x7ACD6000, length 0x24000
Install Smbios Table at 0x7ACC5000, length 0x800
PmCtrlReg at 0x404
PROGRESS CODE: V03040003 I0
Loading driver F9D88642-0737-49BC-81B5-6889CD57D9EA
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96A0C0
Loading driver at 0x0007A94C000 EntryPoint=0x0007A94C2C0 SmbiosDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96AED8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 03583FF6-CB36-4940-947E-B9B39F4AFAF7 7A94F710
PROGRESS CODE: V03040003 I0
Loading driver D3987D4B-971A-435F-8CAF-4967EB627241
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96A540
Loading driver at 0x0007A952000 EntryPoint=0x0007A9522C0 SerialDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96AB58
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD 7A953D50
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A953D00
PROGRESS CODE: V03040003 I0
Loading driver FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A9659C0
Loading driver at 0x0007A8C2000 EntryPoint=0x0007A8C22C0 BdsDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A965C18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 665E3FF6-46CC-11D4-9A38-0090273FC14D 7A8E8F08
PROGRESS CODE: V03040003 I0
Loading driver F2765DEC-6B41-11D5-8E71-00902707B35E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A9642C0
Loading driver at 0x0007A94A000 EntryPoint=0x0007A94A2C0 Timer.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A964DD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 26BACCB3-6F42-11D4-BCE7-0080C73C8881 7A94B730
PROGRESS CODE: V03040003 I0
Loading driver 42857F0A-13F2-4B21-8A23-53D3F714B840
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A965500
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\CapsuleRuntimeDxe\CapsuleRuntimeDxe\DEBUG\CapsuleRuntimeDxe.pdb  !!!!!!!!
Loading driver at 0x0007AB79000 EntryPoint=0x0007AB792C0 CapsuleRuntimeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A964518
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 5053697E-2CBC-4819-90D9-0580DEEE5754 0
PROGRESS CODE: V03040003 I0
Loading driver AD608272-D07F-4964-801E-7BD3B7888652
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A963C80
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\MonotonicCounterRuntimeDxe\MonotonicCounterRuntimeDxe\DEBUG\MonotonicCounterRuntimeDxe.pdbLoading driver at 0x0007AB77000 EntryPoint=0x0007AB772C0 MonotonicCounterRuntimeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A963B98
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 1DA97072-BDDC-4B30-99F1-72A0B56FFF2A 0
PROGRESS CODE: V03040003 I0
Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A951040
!!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
!!!!!!!!  Image - d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\PcAtChipsetPkg\PcatRealTimeClockRuntimeDxe\PcatRealTimeClockRuntimeDxe\DEBUG\PcRtc.pdb  !!!!!!!!
Loading driver at 0x0007AB73000 EntryPoint=0x0007AB732C0 PcRtc.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9512D8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 27CFAC87-46CC-11D4-9A38-0090273FC14D 0
PROGRESS CODE: V03040003 I0
Loading driver EBF342FE-B1D3-4EF8-957C-8048606FF671
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A951600
Loading driver at 0x0007A8A9000 EntryPoint=0x0007A8A92C0 SetupBrowser.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A951858
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: B9D4C360-BCFB-4F9B-9298-53C136982258 7A8C02E0
InstallProtocolInterface: A770C357-B693-4E6D-A6CF-D21C728E550B 7A8C0310
InstallProtocolInterface: 1F73B18D-4630-43C1-A1DE-6F80855D7DA4 7A8C02F0
PROGRESS CODE: V03040003 I0
Loading driver 0F7EC77A-1EE1-400F-A99D-7CBD1FEB181E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A950880
Loading driver at 0x0007A93C000 EntryPoint=0x0007A93C2C0 PcatPciRootBridge.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9503D8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A949FD8
InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A949030
InstallProtocolInterface: AF6AC311-84C3-11D2-8E3C-00A0C969723B 7A949C68
PROGRESS CODE: V03040003 I0
Loading driver F099D67F-71AE-4C36-B2A3-DCEB0EB2B7D8
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FC640
Loading driver at 0x0007A8F8000 EntryPoint=0x0007A8F82C0 WatchdogTimer.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8FCBD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 665E3FF5-46CC-11D4-9A38-0090273FC14D 7A8F95F0
PROGRESS CODE: V03040003 I0
Loading driver E660EA85-058E-4B55-A54B-F02F83A24707
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FC840
Loading driver at 0x0007A881000 EntryPoint=0x0007A881314 DisplayEngine.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8FCAD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 9BBE29E9-FDA1-41EC-AD52-452213742D2E 7A892650
PROGRESS CODE: V03040003 I0
Loading driver 35C0C168-2607-4E51-BB53-448E3ED1A87F
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F4E00
Loading driver at 0x0007A899000 EntryPoint=0x0007A8992C0 PciBusNoEnumerationDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A909AD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A89FFD0
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A0008
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A0020
PROGRESS CODE: V03040003 I0
Loading driver 51CCF399-4FDF-4E55-A45B-E123F84D456A
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F5E00
Loading driver at 0x0007A8A5000 EntryPoint=0x0007A8A52C0 ConPlatformDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A90BA18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8A7E20
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A7E80
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A7E98
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8A7E50
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A7E80
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A7E98
PROGRESS CODE: V03040003 I0
Loading driver 408EDCEC-CF6D-477C-A5A8-B4844E3DE281
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FAE00
Loading driver at 0x0007A871000 EntryPoint=0x0007A8712C0 ConSplitterDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A90DC18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877368
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877808
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877820
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8773F8
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877838
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877850
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877428
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877868
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877880
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877398
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877898
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8778B0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8773C8
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8778C8
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8778E0
InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7A877470
InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7A8774A0
InstallProtocolInterface: 31878C87-0B75-11D5-9A4F-0090273FC14D 7A8774F8
InstallProtocolInterface: 8D59D32B-C655-4AE9-9B15-F25904992A43 7A877550
InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A877600
InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A877710
PROGRESS CODE: V03040003 I0
Loading driver CCCB0C28-4B24-11D5-9A5A-0090273FC14D
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FA8C0
Loading driver at 0x0007A86B000 EntryPoint=0x0007A86B2C0 GraphicsConsoleDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A918BD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A870320
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A870358
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A870370
PROGRESS CODE: V03040003 I0
Loading driver 9E863906-A40F-4875-977F-5B93FF237FC6
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FBC00
Loading driver at 0x0007A863000 EntryPoint=0x0007A8632C0 TerminalDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A91BA18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A869BC8
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A869D68
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A869D80
PROGRESS CODE: V03040003 I0
Loading driver 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FBE00
Loading driver at 0x0007A87C000 EntryPoint=0x0007A87C2C0 DiskIoDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A938B58
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8808D0
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A880988
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8809A0
PROGRESS CODE: V03040003 I0
Loading driver 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7380
Loading driver at 0x0007A857000 EntryPoint=0x0007A8572C0 PartitionDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F7A98
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A85C0B0
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A85C100
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A85C118
PROGRESS CODE: V03040003 I0
Loading driver CD3BAFB6-50FB-4FE8-8E4E-AB74D2C1A600
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7580
Loading driver at 0x0007A8F0000 EntryPoint=0x0007A8F02C0 EnglishDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A93BAD8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 1D85CD7F-F43D-11D2-9A0C-0090273FC14D 7A8F1800
InstallProtocolInterface: A4C751FC-23AE-4C3E-92E9-4964CF63F349 7A8F1838
PROGRESS CODE: V03040003 I0
Loading driver 8F4CD826-A5A0-4E93-9522-CFB0AB72926C
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7780
Loading driver at 0x0007A879000 EntryPoint=0x0007A8792C0 SataController.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F7A18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A87B790
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A87B7C0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A87B7D8
PROGRESS CODE: V03040003 I0
Loading driver 19DF145A-B1D4-453F-8507-38816676D7F6
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6040
Loading driver at 0x0007A849000 EntryPoint=0x0007A8492C0 AtaBusDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A945A18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A84EAA0
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A84ECF0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A84ED08
PROGRESS CODE: V03040003 I0
Loading driver 5E523CB4-D397-4986-87BD-A6DD8B22F455
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6240
Loading driver at 0x0007A833000 EntryPoint=0x0007A8332C0 AtaAtapiPassThruDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A946C18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A83C840
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A83CA80
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A83CA98
PROGRESS CODE: V03040003 I0
Loading driver 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6CC0
Loading driver at 0x0007A85F000 EntryPoint=0x0007A85F2C0 ScsiBus.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6E98
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A862570
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8625A0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8625B8
PROGRESS CODE: V03040003 I0
Loading driver 0A66E322-3740-4CCE-AD62-BD172CECCA35
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6440
Loading driver at 0x0007A842000 EntryPoint=0x0007A8422C0 ScsiDisk.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6C18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A847D50
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A847DB0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A847DC8
PROGRESS CODE: V03040003 I0
Loading driver 961578FE-B6B7-44C3-AF35-6BC705CD2B1F
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F68C0
Loading driver at 0x0007A82C000 EntryPoint=0x0007A82C56C 
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6758
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A82C360
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A82C438
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A82C450
PROGRESS CODE: V03040003 I0
Loading driver 2FB92EFA-2EE0-4BAE-9EB6-7464125E1EF7
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F3BC0
Loading driver at 0x0007A81C000 EntryPoint=0x0007A81C2C0 UhciDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F3B18
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A822950
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A822980
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A822998
PROGRESS CODE: V03040003 I0
Loading driver BDFE430E-8F2A-4DB0-9991-6F856594777E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F3400
Loading driver at 0x0007A80A000 EntryPoint=0x0007A80A2C0 EhciDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F35D8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A811F20
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A811F50
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A811F68
PROGRESS CODE: V03040003 I0
Loading driver B7F50E91-A759-412C-ADE4-DCD03E7F7C28
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F2A80
Loading driver at 0x0007A7E6000 EntryPoint=0x0007A7E62C0 XhciDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F21D8
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A7F1758
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A7F1800
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A7F1818
PROGRESS CODE: V03040003 I0
Loading driver 240612B7-A063-11D4-9A3A-0090273FC14D
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F2480
Loading driver at 0x0007A7DC000 EntryPoint=0x0007A7DC2C0 UsbBusDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F2658
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A7E4AA8
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A7E4AD8
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A7E4AF0
PROGRESS CODE: V03040003 I0
Loading driver 2D2E62CF-9ECF-43B7-8219-94E7FC713DFE
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8EFB40
Loading driver at 0x0007A825000 EntryPoint=0x0007A8252C0 UsbKbDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8EF298
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A82AB80
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A82ABB0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A82ABC8
PROGRESS CODE: V03040003 I0
Loading driver 9FB4B4A7-42C0-4BCD-8540-9BCC6711F83E
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8EF540
Loading driver at 0x0007A816000 EntryPoint=0x0007A8162C0 UsbMassStorageDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8EF718
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A81B828
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A81B858
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A81B870
PROGRESS CODE: V03040003 I0
Loading driver 0B04B2ED-861C-42CD-A22F-C3AAFACCB896
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8A2B40
Loading driver at 0x0007A805000 EntryPoint=0x0007A8052C0 FbGop.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8A2298
PROGRESS CODE: V03040002 I0
InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A808BB0
InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A808BE0
InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A808BF8
PROGRESS CODE: V03040003 I0
PROGRESS CODE: V03041001 I0
[BdsDxe] Locate Variable Lock protocol - Not Found
PROGRESS CODE: V03051005 I0
Variable Driver Auto Update Lang, Lang:eng, PlatformLang:en
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F08
InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7EB8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F20
InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7ED0
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F38
InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7FA8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E8EF0
InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E8128
PlatformBdsPolicyBehavior
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850A98
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A850468
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850E18
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A850128
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A854FD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A854568
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850DD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851028
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898718
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851BE8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850BD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851368
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8988D8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8516A8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A851FD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824028
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A854F98
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824BE8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898918
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824368
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8981D8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8246A8
PciExp - 1 (B-0, D-1C, F-0)
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A824FD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815028
PciExp - 1 (B-0, D-1C, F-2)
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850B58
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815BE8
PciExp - 1 (B-2, D-0, F-0)
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898BD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815368
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898C18
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8156A8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A815FD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814028
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898E18
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814BE8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898CD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814368
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898E58
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8146A8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A814FD8
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813028
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898F18
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813BE8
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8A1698
InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813368
PlatformBdsGetDriverOption
Boot Mode:0
Found PCI VGA device
GOP START
PROGRESS CODE: V01030004 I0
InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A801998
FbGopCheckForVbe - Success
InstallProtocolInterface: 9042A9DE-23DC-4A38-96FB-7ADED080516A 7A801C30
InstallProtocolInterface: 1C0C34F6-D380-41FA-A049-8AD06C1A66AA 7A801C50
InstallProtocolInterface: BD8C1056-9F36-44EC-92A8-A6337F817986 7A801C60
ERROR: C00000002:V03058002 I0 FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F 7A801AD8
Found LPC Bridge device
BdsPlatform.c+140: COM1 DevPath: VenHw(BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD)/Uart(115200,8,N,1)/VenPcAnsi()
!!!! X64 Exception Type - 0000000000000000     CPU Apic ID - 00000000 !!!!
RIP  - 000000007A8061A7, CS  - 0000000000000028, RFLAGS - 0000000000010246
RAX  - 0000000000000000, RCX - 000000007A801ED8, RDX - 0000000000000000
RBX  - 000000007A801818, RSP - 000000007AC7EA40, RBP - 000000007A801C18
RSI  - 000000007AC7EAC0, RDI - 0000000000000000
R8   - 0000000000000000, R9  - 000000007A80185F, R10 - 0000000000000019
R11  - FFFFFFFF857FE128, R12 - 0000000000000000, R13 - 0000000000000001
R14  - 000000007AC7EAF4, R15 - 000000007A801798
DS   - 0000000000000008, ES  - 0000000000000008, FS  - 0000000000000008
GS   - 0000000000000008, SS  - 0000000000000008
CR0  - 0000000080000011, CR2 - 0000000000000000, CR3 - 000000007AC1D000
CR4  - 0000000000000628, CR8 - 0000000000000000
DR0  - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000
DR3  - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400
GDTR - 000000007AC0AA98 000000000000003F, LDTR - 0000000000000000
IDTR - 000000007A990018 0000000000000FFF,   TR - 0000000000000000
FXSAVE_STATE - 000000007AC7E6A0
!!!! Find PE image d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\CorebootPayloadPkg\FbGop\FbGop\DEBUG\FbGop.pdb (ImageBase=000000007A805000, EntryPoint=000000007A8052C0) !!!!







My understanding is that your coreboot does not have ACPI table, you possible 1) add ACPI support in coreboot, or 2) modify UEFI payload to remove the assert if ACPI table not exist, or 3) trying the latest coreboot package from edk2 source tree.

On Tue, Jul 7, 2015 at 2:58 AM, DM365 <1395158558 at qq.com> wrote:
Hello!
      I tested intel uefi payload instead of seabios in coreboot minnowboard max .
      It failed with "Failed to find the required acpi table ".
      If I use seabios payload ,the bios runs ok!
      I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot" to build coreboot.
      I used "https://firmware.intel.com/develop/" 2014-WW26-UEFI.coreboot.Payload.zip to builed uefi in coreboot.
      The whole terminal log is :
   POST: 0x4a
POST: 0x4b
POST: 0x4c
POST: 0x4d
POST: 0x4e
POST: 0x4f
POST: 0x39
POST: 0x80
POST: 0x70
POST: 0x71
POST: 0x72
POST: 0x24
POST: 0x25
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x24
POST: 0x25
POST: 0x55
POST: 0x55
POST: 0x73
APIC: 00 missing read_resources
PCI: 00:00.0 missing set_resources
POST: 0x74
POST: 0x75
POST: 0x75
POST: 0x93
POST: 0x9b
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
POST: 0x75
Warning: PCI Device 2 does not have an IRQ entry, skipping it
POST: 0x75
POST: 0x75
POST: 0x76
POST: 0x77
find_current_mrc_cache_local: No valid fast boot cache found.
POST: 0x79
POST: 0x9c
POST: 0x9e
POST: 0x9d
POST: 0x7a
POST: 0x7b
POST: 0xf8
PROGRESS CODE: V03020003 I0
Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi
PROGRESS CODE: V03020002 I0
0. 0000000000000000 - 0000000000000FFF [10]
1. 0000000000001000 - 000000000009FFFF [01]
2. 00000000000A0000 - 00000000000FFFFF [02]
3. 0000000000100000 - 000000007ACBCFFF [01]
4. 000000007ACBD000 - 000000007ADFFFFF [10]
5. 000000007AE00000 - 000000007FFFFFFF [02]
6. 00000000E0000000 - 00000000EFFFFFFF [02]
7. 00000000FEB00000 - 00000000FEC00FFF [02]
8. 00000000FED01000 - 00000000FED01FFF [02]
9. 00000000FED03000 - 00000000FED03FFF [02]
10. 00000000FED05000 - 00000000FED05FFF [02]
11. 00000000FED08000 - 00000000FED08FFF [02]
12. 00000000FED0C000 - 00000000FED0FFFF [02]
13. 00000000FED1C000 - 00000000FED1CFFF [02]
14. 00000000FEE00000 - 00000000FEE00FFF [02]
15. 00000000FEF00000 - 00000000FEFFFFFF [02]
16. 00000000FF800000 - 00000000FFFFFFFF [02]
Low memory 0x7ACBD000, High Memory 0x0
LowMemorySize: 0x7ACBD000.
HighMemorySize: 0x0.
PeiMemBase: 0x76CB0000.
PeiMemSize: 0x4000000.
PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
Found one valid fv : 0x820000.
Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0
The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000
Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
Actual Coreboot header: 0x7ACBD000.
Failed to find the required acpi table


PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c (338): ((BOOLEAN)(0==1))



--
 coreboot mailing list: coreboot at coreboot.org
 http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150709/e6407f4a/attachment-0001.html>

From paulepanter at users.sourceforge.net  Thu Jul  9 08:43:09 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Thu, 09 Jul 2015 08:43:09 +0200
Subject: [coreboot] Kernel couldn't find proper MAC address with
 coreboot (gigabyte ma785gmt-ud2h)
In-Reply-To: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>
References: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>
Message-ID: <1436424189.29683.20.camel@users.sourceforge.net>

Dear YongGon,


welcome to coreboot and thank you for your message!


Am Mittwoch, den 08.07.2015, 20:47 +0900 schrieb YongGon Kim:

[?]

> I have uploaded detailed information using board_status.sh
> Following is link for the information.
> http://review.coreboot.org/gitweb?p=board-status.git;a=commit;h=dedf456d25748368da19d556828c7ef95e3f3073

Your commit is marked as *dirty*, meaning that you have applied local
changes. What are these?

Additionally, could you please also upload the logs of a run with the
current code in master?


Thanks,

Paul


PS: Please just send plain text messages to mailing lists.
Additionally, pasting logs in the Google Mail Web interface is not
optimal as there is no way to turn off auto-wrapping the lines, which
is not wanted for pastes.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150709/4ab8d61c/attachment.asc>

From wangfei.jimei at gmail.com  Thu Jul  9 10:38:36 2015
From: wangfei.jimei at gmail.com (WANG FEI)
Date: Thu, 9 Jul 2015 09:38:36 +0100
Subject: [coreboot] minnowboardmax coreboot intel uefi payload :Failedto
 find the required acpi table
In-Reply-To: <tencent_3C71D443673588841038DC85@qq.com>
References: <tencent_2FD451C610CCE6504AB1172F@qq.com>
 <CAGH0wH1bpyG7AAvOsHNjfL-qXFSY48DSfPdEDtscimMrxoF8LQ@mail.gmail.com>
 <tencent_3C71D443673588841038DC85@qq.com>
Message-ID: <CAGH0wH0UNNTXVr+jHOZt0NO5u09kOPRvhatxxd3WrDA0XKgWYw@mail.gmail.com>

Not too sure what this issue is, maybe you have to debug it. It looks the
code has already run in BDS and ready to boot. The last useful message it
shows up is,

BdsPlatform.c+140: COM1 DevPath: VenHw(BB25CF6F-F1D4-11D2-9A0C-
0090273FC1FD)/Uart(115200,8,N,1)/VenPcAnsi()

You might be able to find this debug message in BdsPlatform.c.

On Thu, Jul 9, 2015 at 3:36 AM, DM365 <1395158558 at qq.com> wrote:

> I try the latest coreboot package from edk2.
> The acpi table is ok,but there is new question."ERROR: C00000002:V03058002
> I0 FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F 7A801AD8".
> The whole log is :
> POST: 0x4a
> POST: 0x4b
> POST: 0x4c
> POST: 0x4d
> POST: 0x4e
> POST: 0x4f
> POST: 0x39
> POST: 0x80
> POST: 0x70
> POST: 0x71
> POST: 0x72
> POST: 0x24
> POST: 0x25
> POST: 0x24
> POST: 0x25
> POST: 0x55
> POST: 0x24
> POST: 0x25
> POST: 0x55
> POST: 0x55
> POST: 0x73
> APIC: 00 missing read_resources
> PCI: 00:00.0 missing set_resources
> POST: 0x74
> POST: 0x75
> POST: 0x75
> POST: 0x93
> POST: 0x9b
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> POST: 0x75
> Warning: PCI Device 2 does not have an IRQ entry, skipping it
> POST: 0x75
> POST: 0x75
> POST: 0x76
> POST: 0x77
> find_current_mrc_cache_local: No valid fast boot cache found.
> POST: 0x79
> POST: 0x9c
> POST: 0x9e
> POST: 0x9d
> POST: 0x7a
> POST: 0x7b
> POST: 0xf8
> PROGRESS CODE: V03020003 I0
> Loading PEIM at 0x0000080F4A0 EntryPoint=0x0000080F700 CbSupportPeim.efi
> PROGRESS CODE: V03020002 I0
> 0. 0000000000000000 - 0000000000000FFF [10]
> 1. 0000000000001000 - 000000000009FFFF [01]
> 2. 00000000000A0000 - 00000000000FFFFF [02]
> 3. 0000000000100000 - 000000007ACBCFFF [01]
> 4. 000000007ACBD000 - 000000007ADFFFFF [10]
> 5. 000000007AE00000 - 000000007FFFFFFF [02]
> 6. 00000000E0000000 - 00000000EFFFFFFF [02]
> 7. 00000000FEB00000 - 00000000FEC00FFF [02]
> 8. 00000000FED01000 - 00000000FED01FFF [02]
> 9. 00000000FED03000 - 00000000FED03FFF [02]
> 10. 00000000FED05000 - 00000000FED05FFF [02]
> 11. 00000000FED08000 - 00000000FED08FFF [02]
> 12. 00000000FED0C000 - 00000000FED0FFFF [02]
> 13. 00000000FED1C000 - 00000000FED1CFFF [02]
> 14. 00000000FEE00000 - 00000000FEE00FFF [02]
> 15. 00000000FEF00000 - 00000000FEFFFFFF [02]
> 16. 00000000FF800000 - 00000000FFFFFFFF [02]
> Low memory 0x7ACBD000, High Memory 0x0
> LowMemorySize: 0x7ACBD000.
> HighMemorySize: 0x0.
> PeiMemBase: 0x76CB0000.
> PeiMemSize: 0x4000000.
> PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
> Found one valid fv : 0x3E000000830000.
> Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
> Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry
> point: 801C77
> The 1th FV start address is 0x00000830000, size is 0x003E0000, handle is
> 0x830000
> Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
> Actual Coreboot header: 7ACBD000.
> Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x24000
> Find CbMemTable Id 0x534D4254, base 7ACC5000, size 0x800
> Detected Acpi Table at 0x7ACD6000, length 0x24000
> Detected Smbios Table at 0x7ACC5000, length 0x800
> Create system table info guid hob
> Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x1000
> Find Rsdp at 7ACD6000
> Find Rsdt 0x7ACD6030, Xsdt 0x7ACD60E0
> PmCtrl Reg 0x404
> PmTimer Reg 0x408
> Reset Reg 0xCF9
> Reset Value 0x6
> PmEvt Reg 0x400
> PmGpeEn Reg 0x424
> Create acpi board info guid hob
> Found coreboot video frame buffer information
> physical_address: 0x0
> x_resolution: 0x0
> y_resolution: 0x0
> bits_per_pixel: 0x0
> bytes_per_line: 0x0
> red_mask_size: 0x0
> red_mask_pos: 0x0
> green_mask_size: 0x0
> green_mask_pos: 0x0
> blue_mask_size: 0x0
> blue_mask_pos: 0x0
> reserved_mask_size: 0x0
> reserved_mask_pos: 0x0
> Create frame buffer info guid hob
> PROGRESS CODE: V03020003 I0
> Temp Stack : BaseAddress=0x88000 Length=0x8000
> Temp Heap  : BaseAddress=0x80000 Length=0xD30
> Total temporary memory:    65536 bytes.
>   temporary memory stack ever used: 32768 bytes.
>   temporary memory heap used:       3376 bytes.
> Old Stack size 32768, New stack size 131072
> Stack Hob: BaseAddress=0x76CB0000 Length=0x20000
> Heap Offset = 0x76C50000 Stack Offset = 0x76C40000
> Loading PEIM at 0x0007ACA6000 EntryPoint=0x0007ACA6260 PeiCore.efi
> Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
> Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
> Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
> Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
> Loading PEIM at 0x0007ACA2000 EntryPoint=0x0007ACA2260 DxeIpl.efi
> PROGRESS CODE: V03020002 I0
> PROGRESS CODE: V03020003 I0
> Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
> Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
> DXE IPL Entry
> Loading PEIM at 0x0007AC7F000 EntryPoint=0x0007AC7F2C0 DxeCore.efi
> PROGRESS CODE: V03021001 I0
> Loading DXE CORE at 0x0007AC7F000 EntryPoint=0x0007AC7F2C0
> Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6
> PROGRESS CODE: V03040003 I0
> Loading driver F80697E9-7FD6-4665-8646-88E33EF71DFC
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A98F040
> Loading driver at 0x0007A985000 EntryPoint=0x0007A9852C0
> SecurityStubDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98FF18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 94AB2F58-1438-4EF1-9152-18941A3A0E68 7A987428
> InstallProtocolInterface: A46423E3-4617-49F1-B9FF-D1BFA9115839 7A987420
> PROGRESS CODE: V03040003 I0
> Loading driver 1A1E4886-9517-440E-9FDE-3BE44CEE2136
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A98F380
> Loading driver at 0x0007A970000 EntryPoint=0x0007A9702C0 CpuDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98FB58
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 26BACCB1-6F42-11D4-BCE7-0080C73C8881 7A979480
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
>   Flushing GCD
> Detect CPU count: 2
> Does not find any HOB stored CPU BIST information!
> InstallProtocolInterface: 3FDDA605-A76E-4F46-AD29-12F4531B3D08 7A9793A8
> PROGRESS CODE: V03040003 I0
> Loading driver C8339973-A563-4561-B858-D8476F9DEFC4
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97C040
> Loading driver at 0x0007A97A000 EntryPoint=0x0007A97A2C0 Metronome.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97CF18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 26BACCB2-6F42-11D4-BCE7-0080C73C8881 7A97BA10
> PROGRESS CODE: V03040003 I0
> Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97C380
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Core\RuntimeDxe\RuntimeDxe\DEBUG\RuntimeDxe.pdb
>  !!!!!!!!
> Loading driver at 0x0007AB83000 EntryPoint=0x0007AB832C0 RuntimeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97CDD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: B7DFB4E1-052F-449F-87BE-9818FC91B733 7AB85100
> PROGRESS CODE: V03040003 I0
> Loading driver 4B28E4C7-FF36-4E10-93CF-A82159E777C5
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97E0C0
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\ResetSystemRuntimeDxe\ResetSystemRuntimeDxe\DEBUG\ResetSystemRuntimeDxe.pdb
>  !!!!!!!!
> Loading driver at 0x0007AB80000 EntryPoint=0x0007AB802C0
> ResetSystemRuntimeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97EED8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 27CFAC88-46CC-11D4-9A38-0090273FC14D 0
> PROGRESS CODE: V03040003 I0
> Loading driver 02B01AD5-7E59-43E8-A6D8-238180613A5A
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97E540
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\Variable\EmuRuntimeDxe\EmuVariableRuntimeDxe\DEBUG\EmuVariableRuntimeDxe.pdb
>  !!!!!!!!
> Loading driver at 0x0007AB7B000 EntryPoint=0x0007AB7B2C0
> EmuVariableRuntimeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97E798
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 1E5668E2-8481-11D4-BCF1-0080C73C8881 0
> InstallProtocolInterface: 6441F818-6362-4E44-B570-7DBA31DD2453 0
> PROGRESS CODE: V03040003 I0
> Loading driver A19B1FE7-C1BC-49F8-875F-54A5D542443F
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97D2C0
> Loading driver at 0x0007A96C000 EntryPoint=0x0007A96C2C0 CpuIo2Dxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97DA58
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: AD61F191-AE5F-4C0E-B9FA-E869D288C64F 7A96DC30
> PROGRESS CODE: V03040003 I0
> Loading driver 9B680FCE-AD6B-4F3A-B60B-F59899003443
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A97D740
> Loading driver at 0x0007A954000 EntryPoint=0x0007A9542C0 DevicePathDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96FF18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 0379BE4E-D706-437D-B037-EDB82FB772A4 7A95B6E0
> InstallProtocolInterface: 8B843E20-8132-4852-90CC-551A4E4A7F1C 7A95B720
> InstallProtocolInterface: 05C99A21-C70F-4AD2-8A5F-35DF3343F51E 7A95B730
> PROGRESS CODE: V03040003 I0
> Loading driver 96B5C032-DF4C-4B6E-8232-438DCF448D0E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96F880
> Loading driver at 0x0007A968000 EntryPoint=0x0007A9682C0
> NullMemoryTestDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96F098
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 309DE7F1-7F5E-4ACE-B49C-531BE5AA95EF 7A969900
> PROGRESS CODE: V03040003 I0
> Loading driver 79CA4208-BBA1-4A9A-8456-E1E66A81484E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96E040
> Loading driver at 0x0007A966000 EntryPoint=0x0007A9662C0 Legacy8259.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96E2D8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 38321DBA-4FE0-4E17-8AEC-413055EAEDC1 7A9677E0
> PROGRESS CODE: V03040003 I0
> Loading driver 348C4D62-BFBD-4882-9ECE-C80BB1C4783B
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96EA00
> Loading driver at 0x0007A91C000 EntryPoint=0x0007A91C2C0 HiiDatabase.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96ED18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: E9CA4775-8657-47FC-97E7-7ED65A084324 7A935D68
> InstallProtocolInterface: 0FD96974-23AA-4CDC-B9CB-98D17750322A 7A935DB0
> InstallProtocolInterface: EF9FC172-A1B2-4693-B327-6D32FC416042 7A935DD8
> InstallProtocolInterface: 587E72D7-CC50-4F79-8209-CA291FC1A10F 7A935E30
> InstallProtocolInterface: 0A8BADD5-03B8-4D19-B128-7B8F0EDAA596 7A935E60
> InstallProtocolInterface: 31A6406A-6BDF-4E46-B2A2-EBAA89C40920 7A935D88
> PROGRESS CODE: V03040003 I0
> Loading driver C68DAA4E-7AB5-41E8-A91D-5954421053F3
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96B200
> Loading driver at 0x0007A960000 EntryPoint=0x0007A9602C0 CbSupportDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96B858
> PROGRESS CODE: V03040002 I0
> Install Acpi Table at 0x7ACD6000, length 0x24000
> Install Smbios Table at 0x7ACC5000, length 0x800
> PmCtrlReg at 0x404
> PROGRESS CODE: V03040003 I0
> Loading driver F9D88642-0737-49BC-81B5-6889CD57D9EA
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96A0C0
> Loading driver at 0x0007A94C000 EntryPoint=0x0007A94C2C0 SmbiosDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96AED8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 03583FF6-CB36-4940-947E-B9B39F4AFAF7 7A94F710
> PROGRESS CODE: V03040003 I0
> Loading driver D3987D4B-971A-435F-8CAF-4967EB627241
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A96A540
> Loading driver at 0x0007A952000 EntryPoint=0x0007A9522C0 SerialDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A96AB58
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD 7A953D50
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A953D00
> PROGRESS CODE: V03040003 I0
> Loading driver FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A9659C0
> Loading driver at 0x0007A8C2000 EntryPoint=0x0007A8C22C0 BdsDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A965C18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 665E3FF6-46CC-11D4-9A38-0090273FC14D 7A8E8F08
> PROGRESS CODE: V03040003 I0
> Loading driver F2765DEC-6B41-11D5-8E71-00902707B35E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A9642C0
> Loading driver at 0x0007A94A000 EntryPoint=0x0007A94A2C0 Timer.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A964DD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 26BACCB3-6F42-11D4-BCE7-0080C73C8881 7A94B730
> PROGRESS CODE: V03040003 I0
> Loading driver 42857F0A-13F2-4B21-8A23-53D3F714B840
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A965500
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\CapsuleRuntimeDxe\CapsuleRuntimeDxe\DEBUG\CapsuleRuntimeDxe.pdb
>  !!!!!!!!
> Loading driver at 0x0007AB79000 EntryPoint=0x0007AB792C0
> CapsuleRuntimeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A964518
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 5053697E-2CBC-4819-90D9-0580DEEE5754 0
> PROGRESS CODE: V03040003 I0
> Loading driver AD608272-D07F-4964-801E-7BD3B7888652
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A963C80
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\MdeModulePkg\Universal\MonotonicCounterRuntimeDxe\MonotonicCounterRuntimeDxe\DEBUG\MonotonicCounterRuntimeDxe.pdbLoading
> driver at 0x0007AB77000 EntryPoint=0x0007AB772C0
> MonotonicCounterRuntimeDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A963B98
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 1DA97072-BDDC-4B30-99F1-72A0B56FFF2A 0
> PROGRESS CODE: V03040003 I0
> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A951040
> !!!!!!!!  InsertImageRecord - Section Alignment(0x20) is not 4K  !!!!!!!!
> !!!!!!!!  Image -
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\PcAtChipsetPkg\PcatRealTimeClockRuntimeDxe\PcatRealTimeClockRuntimeDxe\DEBUG\PcRtc.pdb
>  !!!!!!!!
> Loading driver at 0x0007AB73000 EntryPoint=0x0007AB732C0 PcRtc.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9512D8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 27CFAC87-46CC-11D4-9A38-0090273FC14D 0
> PROGRESS CODE: V03040003 I0
> Loading driver EBF342FE-B1D3-4EF8-957C-8048606FF671
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A951600
> Loading driver at 0x0007A8A9000 EntryPoint=0x0007A8A92C0 SetupBrowser.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A951858
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: B9D4C360-BCFB-4F9B-9298-53C136982258 7A8C02E0
> InstallProtocolInterface: A770C357-B693-4E6D-A6CF-D21C728E550B 7A8C0310
> InstallProtocolInterface: 1F73B18D-4630-43C1-A1DE-6F80855D7DA4 7A8C02F0
> PROGRESS CODE: V03040003 I0
> Loading driver 0F7EC77A-1EE1-400F-A99D-7CBD1FEB181E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A950880
> Loading driver at 0x0007A93C000 EntryPoint=0x0007A93C2C0
> PcatPciRootBridge.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9503D8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A949FD8
> InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A949030
> InstallProtocolInterface: AF6AC311-84C3-11D2-8E3C-00A0C969723B 7A949C68
> PROGRESS CODE: V03040003 I0
> Loading driver F099D67F-71AE-4C36-B2A3-DCEB0EB2B7D8
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FC640
> Loading driver at 0x0007A8F8000 EntryPoint=0x0007A8F82C0 WatchdogTimer.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8FCBD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 665E3FF5-46CC-11D4-9A38-0090273FC14D 7A8F95F0
> PROGRESS CODE: V03040003 I0
> Loading driver E660EA85-058E-4B55-A54B-F02F83A24707
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FC840
> Loading driver at 0x0007A881000 EntryPoint=0x0007A881314 DisplayEngine.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8FCAD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 9BBE29E9-FDA1-41EC-AD52-452213742D2E 7A892650
> PROGRESS CODE: V03040003 I0
> Loading driver 35C0C168-2607-4E51-BB53-448E3ED1A87F
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F4E00
> Loading driver at 0x0007A899000 EntryPoint=0x0007A8992C0
> PciBusNoEnumerationDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A909AD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A89FFD0
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A0008
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A0020
> PROGRESS CODE: V03040003 I0
> Loading driver 51CCF399-4FDF-4E55-A45B-E123F84D456A
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F5E00
> Loading driver at 0x0007A8A5000 EntryPoint=0x0007A8A52C0 ConPlatformDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A90BA18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8A7E20
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A7E80
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A7E98
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8A7E50
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A7E80
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A7E98
> PROGRESS CODE: V03040003 I0
> Loading driver 408EDCEC-CF6D-477C-A5A8-B4844E3DE281
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FAE00
> Loading driver at 0x0007A871000 EntryPoint=0x0007A8712C0 ConSplitterDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A90DC18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877368
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877808
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877820
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8773F8
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877838
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877850
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877428
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877868
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A877880
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A877398
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A877898
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8778B0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8773C8
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8778C8
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8778E0
> InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7A877470
> InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7A8774A0
> InstallProtocolInterface: 31878C87-0B75-11D5-9A4F-0090273FC14D 7A8774F8
> InstallProtocolInterface: 8D59D32B-C655-4AE9-9B15-F25904992A43 7A877550
> InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A877600
> InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A877710
> PROGRESS CODE: V03040003 I0
> Loading driver CCCB0C28-4B24-11D5-9A5A-0090273FC14D
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FA8C0
> Loading driver at 0x0007A86B000 EntryPoint=0x0007A86B2C0
> GraphicsConsoleDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A918BD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A870320
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A870358
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A870370
> PROGRESS CODE: V03040003 I0
> Loading driver 9E863906-A40F-4875-977F-5B93FF237FC6
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FBC00
> Loading driver at 0x0007A863000 EntryPoint=0x0007A8632C0 TerminalDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A91BA18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A869BC8
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A869D68
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A869D80
> PROGRESS CODE: V03040003 I0
> Loading driver 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8FBE00
> Loading driver at 0x0007A87C000 EntryPoint=0x0007A87C2C0 DiskIoDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A938B58
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8808D0
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A880988
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8809A0
> PROGRESS CODE: V03040003 I0
> Loading driver 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7380
> Loading driver at 0x0007A857000 EntryPoint=0x0007A8572C0 PartitionDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F7A98
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A85C0B0
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A85C100
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A85C118
> PROGRESS CODE: V03040003 I0
> Loading driver CD3BAFB6-50FB-4FE8-8E4E-AB74D2C1A600
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7580
> Loading driver at 0x0007A8F0000 EntryPoint=0x0007A8F02C0 EnglishDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A93BAD8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 1D85CD7F-F43D-11D2-9A0C-0090273FC14D 7A8F1800
> InstallProtocolInterface: A4C751FC-23AE-4C3E-92E9-4964CF63F349 7A8F1838
> PROGRESS CODE: V03040003 I0
> Loading driver 8F4CD826-A5A0-4E93-9522-CFB0AB72926C
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F7780
> Loading driver at 0x0007A879000 EntryPoint=0x0007A8792C0 SataController.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F7A18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A87B790
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A87B7C0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A87B7D8
> PROGRESS CODE: V03040003 I0
> Loading driver 19DF145A-B1D4-453F-8507-38816676D7F6
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6040
> Loading driver at 0x0007A849000 EntryPoint=0x0007A8492C0 AtaBusDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A945A18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A84EAA0
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A84ECF0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A84ED08
> PROGRESS CODE: V03040003 I0
> Loading driver 5E523CB4-D397-4986-87BD-A6DD8B22F455
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6240
> Loading driver at 0x0007A833000 EntryPoint=0x0007A8332C0
> AtaAtapiPassThruDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A946C18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A83C840
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A83CA80
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A83CA98
> PROGRESS CODE: V03040003 I0
> Loading driver 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6CC0
> Loading driver at 0x0007A85F000 EntryPoint=0x0007A85F2C0 ScsiBus.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6E98
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A862570
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8625A0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8625B8
> PROGRESS CODE: V03040003 I0
> Loading driver 0A66E322-3740-4CCE-AD62-BD172CECCA35
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F6440
> Loading driver at 0x0007A842000 EntryPoint=0x0007A8422C0 ScsiDisk.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6C18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A847D50
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A847DB0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A847DC8
> PROGRESS CODE: V03040003 I0
> Loading driver 961578FE-B6B7-44C3-AF35-6BC705CD2B1F
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F68C0
> Loading driver at 0x0007A82C000 EntryPoint=0x0007A82C56C
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F6758
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A82C360
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A82C438
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A82C450
> PROGRESS CODE: V03040003 I0
> Loading driver 2FB92EFA-2EE0-4BAE-9EB6-7464125E1EF7
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F3BC0
> Loading driver at 0x0007A81C000 EntryPoint=0x0007A81C2C0 UhciDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F3B18
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A822950
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A822980
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A822998
> PROGRESS CODE: V03040003 I0
> Loading driver BDFE430E-8F2A-4DB0-9991-6F856594777E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F3400
> Loading driver at 0x0007A80A000 EntryPoint=0x0007A80A2C0 EhciDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F35D8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A811F20
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A811F50
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A811F68
> PROGRESS CODE: V03040003 I0
> Loading driver B7F50E91-A759-412C-ADE4-DCD03E7F7C28
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F2A80
> Loading driver at 0x0007A7E6000 EntryPoint=0x0007A7E62C0 XhciDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F21D8
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A7F1758
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A7F1800
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A7F1818
> PROGRESS CODE: V03040003 I0
> Loading driver 240612B7-A063-11D4-9A3A-0090273FC14D
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8F2480
> Loading driver at 0x0007A7DC000 EntryPoint=0x0007A7DC2C0 UsbBusDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8F2658
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A7E4AA8
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A7E4AD8
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A7E4AF0
> PROGRESS CODE: V03040003 I0
> Loading driver 2D2E62CF-9ECF-43B7-8219-94E7FC713DFE
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8EFB40
> Loading driver at 0x0007A825000 EntryPoint=0x0007A8252C0 UsbKbDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8EF298
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A82AB80
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A82ABB0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A82ABC8
> PROGRESS CODE: V03040003 I0
> Loading driver 9FB4B4A7-42C0-4BCD-8540-9BCC6711F83E
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8EF540
> Loading driver at 0x0007A816000 EntryPoint=0x0007A8162C0
> UsbMassStorageDxe.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8EF718
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A81B828
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A81B858
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A81B870
> PROGRESS CODE: V03040003 I0
> Loading driver 0B04B2ED-861C-42CD-A22F-C3AAFACCB896
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8A2B40
> Loading driver at 0x0007A805000 EntryPoint=0x0007A8052C0 FbGop.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8A2298
> PROGRESS CODE: V03040002 I0
> InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A808BB0
> InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A808BE0
> InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A808BF8
> PROGRESS CODE: V03040003 I0
> PROGRESS CODE: V03041001 I0
> [BdsDxe] Locate Variable Lock protocol - Not Found
> PROGRESS CODE: V03051005 I0
> Variable Driver Auto Update Lang, Lang:eng, PlatformLang:en
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F08
> InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7EB8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F20
> InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7ED0
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E7F38
> InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E7FA8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8E8EF0
> InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A8E8128
> PlatformBdsPolicyBehavior
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850A98
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A850468
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850E18
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A850128
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A854FD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A854568
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850DD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851028
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898718
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851BE8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850BD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A851368
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8988D8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8516A8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A851FD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824028
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A854F98
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824BE8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898918
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A824368
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8981D8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8246A8
> PciExp - 1 (B-0, D-1C, F-0)
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A824FD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815028
> PciExp - 1 (B-0, D-1C, F-2)
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A850B58
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815BE8
> PciExp - 1 (B-2, D-0, F-0)
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898BD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A815368
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898C18
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8156A8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A815FD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814028
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898E18
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814BE8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898CD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A814368
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898E58
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8146A8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A814FD8
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813028
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A898F18
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813BE8
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A8A1698
> InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A813368
> PlatformBdsGetDriverOption
> Boot Mode:0
> Found PCI VGA device
> GOP START
> PROGRESS CODE: V01030004 I0
> InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A801998
> FbGopCheckForVbe - Success
> InstallProtocolInterface: 9042A9DE-23DC-4A38-96FB-7ADED080516A 7A801C30
> InstallProtocolInterface: 1C0C34F6-D380-41FA-A049-8AD06C1A66AA 7A801C50
> InstallProtocolInterface: BD8C1056-9F36-44EC-92A8-A6337F817986 7A801C60
> ERROR: C00000002:V03058002 I0 FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F 7A801AD8
> Found LPC Bridge device
> BdsPlatform.c+140: COM1 DevPath:
> VenHw(BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD)/Uart(115200,8,N,1)/VenPcAnsi()
> !!!! X64 Exception Type - 0000000000000000     CPU Apic ID - 00000000 !!!!
> RIP  - 000000007A8061A7, CS  - 0000000000000028, RFLAGS - 0000000000010246
> RAX  - 0000000000000000, RCX - 000000007A801ED8, RDX - 0000000000000000
> RBX  - 000000007A801818, RSP - 000000007AC7EA40, RBP - 000000007A801C18
> RSI  - 000000007AC7EAC0, RDI - 0000000000000000
> R8   - 0000000000000000, R9  - 000000007A80185F, R10 - 0000000000000019
> R11  - FFFFFFFF857FE128, R12 - 0000000000000000, R13 - 0000000000000001
> R14  - 000000007AC7EAF4, R15 - 000000007A801798
> DS   - 0000000000000008, ES  - 0000000000000008, FS  - 0000000000000008
> GS   - 0000000000000008, SS  - 0000000000000008
> CR0  - 0000000080000011, CR2 - 0000000000000000, CR3 - 000000007AC1D000
> CR4  - 0000000000000628, CR8 - 0000000000000000
> DR0  - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000
> DR3  - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400
> GDTR - 000000007AC0AA98 000000000000003F, LDTR - 0000000000000000
> IDTR - 000000007A990018 0000000000000FFF,   TR - 0000000000000000
> FXSAVE_STATE - 000000007AC7E6A0
> !!!! Find PE image
> d:\share\e3800\edk2\Build\CorebootPayloadPkgX64\DEBUG_VS2008x86\X64\CorebootPayloadPkg\FbGop\FbGop\DEBUG\FbGop.pdb
> (ImageBase=000000007A805000, EntryPoint=000000007A8052C0) !!!!
>
>
>
> My understanding is that your coreboot does not have ACPI table, you
> possible 1) add ACPI support in coreboot, or 2) modify UEFI payload to
> remove the assert if ACPI table not exist, or 3) trying the latest coreboot
> package from edk2 source tree.
>
> On Tue, Jul 7, 2015 at 2:58 AM, DM365 <1395158558 at qq.com> wrote:
>
>> Hello!
>>       I tested intel uefi payload instead of seabios in coreboot
>> minnowboard max .
>>       It failed with "Failed to find the required acpi table ".
>>       If I use seabios payload ,the bios runs ok!
>>       I followed "http://www.elinux.org/Minnowboard:MinnowMaxCoreboot"
>> to build coreboot.
>>       I used "https://firmware.intel.com/develop/"
>> 2014-WW26-UEFI.coreboot.Payload.zip
>> <https://firmware.intel.com/sites/default/files/2014-WW26-UEFI.CoreBoot.Payload.zip> to
>> builed uefi in coreboot.
>> <https://firmware.intel.com/sites/default/files/2014-WW26-UEFI.CoreBoot.Payload.zip>
>>       The whole terminal log is :
>>    POST: 0x4a
>> POST: 0x4b
>> POST: 0x4c
>> POST: 0x4d
>> POST: 0x4e
>> POST: 0x4f
>> POST: 0x39
>> POST: 0x80
>> POST: 0x70
>> POST: 0x71
>> POST: 0x72
>> POST: 0x24
>> POST: 0x25
>> POST: 0x24
>> POST: 0x25
>> POST: 0x55
>> POST: 0x24
>> POST: 0x25
>> POST: 0x55
>> POST: 0x55
>> POST: 0x73
>> APIC: 00 missing read_resources
>> PCI: 00:00.0 missing set_resources
>> POST: 0x74
>> POST: 0x75
>> POST: 0x75
>> POST: 0x93
>> POST: 0x9b
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> POST: 0x75
>> Warning: PCI Device 2 does not have an IRQ entry, skipping it
>> POST: 0x75
>> POST: 0x75
>> POST: 0x76
>> POST: 0x77
>> find_current_mrc_cache_local: No valid fast boot cache found.
>> POST: 0x79
>> POST: 0x9c
>> POST: 0x9e
>> POST: 0x9d
>> POST: 0x7a
>> POST: 0x7b
>> POST: 0xf8
>> PROGRESS CODE: V03020003 I0
>> Loading PEIM at 0x0000080EC20 EntryPoint=0x0000080EE80 CbSupportPeim.efi
>> PROGRESS CODE: V03020002 I0
>> 0. 0000000000000000 - 0000000000000FFF [10]
>> 1. 0000000000001000 - 000000000009FFFF [01]
>> 2. 00000000000A0000 - 00000000000FFFFF [02]
>> 3. 0000000000100000 - 000000007ACBCFFF [01]
>> 4. 000000007ACBD000 - 000000007ADFFFFF [10]
>> 5. 000000007AE00000 - 000000007FFFFFFF [02]
>> 6. 00000000E0000000 - 00000000EFFFFFFF [02]
>> 7. 00000000FEB00000 - 00000000FEC00FFF [02]
>> 8. 00000000FED01000 - 00000000FED01FFF [02]
>> 9. 00000000FED03000 - 00000000FED03FFF [02]
>> 10. 00000000FED05000 - 00000000FED05FFF [02]
>> 11. 00000000FED08000 - 00000000FED08FFF [02]
>> 12. 00000000FED0C000 - 00000000FED0FFFF [02]
>> 13. 00000000FED1C000 - 00000000FED1CFFF [02]
>> 14. 00000000FEE00000 - 00000000FEE00FFF [02]
>> 15. 00000000FEF00000 - 00000000FEFFFFFF [02]
>> 16. 00000000FF800000 - 00000000FFFFFFFF [02]
>> Low memory 0x7ACBD000, High Memory 0x0
>> LowMemorySize: 0x7ACBD000.
>> HighMemorySize: 0x0.
>> PeiMemBase: 0x76CB0000.
>> PeiMemSize: 0x4000000.
>> PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
>> Found one valid fv : 0x820000.
>> Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
>> Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry
>> point: 801BC0
>> The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is
>> 0x820000
>> Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
>> Actual Coreboot header: 0x7ACBD000.
>> Failed to find the required acpi table
>>
>> PEI_ASSERT!: d:\myworkspace\CorebootModulePkg\CbSupportPei\CbSupportPei.c
>> (338): ((BOOLEAN)(0==1))
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150709/77d7aee8/attachment-0001.html>

From ilios86 at gmail.com  Thu Jul  9 12:42:38 2015
From: ilios86 at gmail.com (YongGon Kim)
Date: Thu, 9 Jul 2015 19:42:38 +0900
Subject: [coreboot] Kernel couldn't find proper MAC address with
 coreboot (gigabyte ma785gmt-ud2h)
In-Reply-To: <1436424189.29683.20.camel@users.sourceforge.net>
References: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>
 <1436424189.29683.20.camel@users.sourceforge.net>
Message-ID: <CAGFmz-wb6Lp1_gd5FGvefVdrAXOJsZrEF5xbCGSejN-5q9=_MA@mail.gmail.com>

Thank you for reply!


2015-07-09 15:43 GMT+09:00 Paul Menzel <paulepanter at users.sourceforge.net>:

> Dear YongGon,
>
>
> welcome to coreboot and thank you for your message!
>
>
> Am Mittwoch, den 08.07.2015, 20:47 +0900 schrieb YongGon Kim:
>
> [?]
>
> > I have uploaded detailed information using board_status.sh
> > Following is link for the information.
> >
> http://review.coreboot.org/gitweb?p=board-status.git;a=commit;h=dedf456d25748368da19d556828c7ef95e3f3073
>
> Your commit is marked as *dirty*, meaning that you have applied local
> changes. What are these?
>

I just changed board_status.sh to properly upload my logs.  i didn't change
anything else.



>
> Additionally, could you please also upload the logs of a run with the
> current code in master?
>

I pasted logs of master code. (revision
5d866213f42fd22aed80abb5a91d74f6d485ac3f)

As you can see, booting process stopped in the middle.
I chose the previous snapshot of coreboot since i found some valid results
in following link.
http://www.coreboot.org/Supported_Motherboards#gigabyte.2Fma785gmt






>
>
> Thanks,
>
> Paul
>
>
> PS: Please just send plain text messages to mailing lists.
> Additionally, pasting logs in the Google Mail Web interface is not
> optimal as there is no way to turn off auto-wrapping the lines, which
> is not wanted for pastes.
>

I'm sorry. I'm not clearly understanding your request.
Do you know any alternative interface for sending plain logs?

Anyway, followings are log from master coreboot.

coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 romstage
starting...
BSP Family_Model: 00100f42
*sysinfo range: [000c4100,000c7d31]
bsp_apicid = 00
cpu_init_detectedx = 00000000
CBFS @ 0 size ffc40
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 2fc0 size 3800
[microcode] patch id to apply = 0x010000db
[microcode] updated to patch id = 0x010000db success
POST: 0x33
cpuSetAMDMSR  done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
  F3x80: e600e681
  F3x84: 80e641e6
  F3xD4: c8810f24
  F3xD8: 03001816
  F3xDC: 00006322
POST: 0x36
core0 started:
start_other_cores()
init node: 00  cores: 02
Start other core - nodeid: 00  cores: 02
POST: 0x37
started ap apicid: * AP 01started
* AP 02started

POST: 0x38
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30b40093 0x40035040
POST: 0x39
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 2
readback = 2010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b40093 0x38005040
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
...WARM RESET...




coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 romstage
starting...
BSP Family_Model: 00100f42
*sysinfo range: [000c4100,000c7d31]
bsp_apicid = 00
cpu_init_detectedx = 00000000
CBFS @ 0 size ffc40
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 2fc0 size 3800
[microcode] patch id to apply = 0x010000db
[microcode] updated to patch id = 0x010000db success
POST: 0x33
cpuSetAMDMSR  done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
 event class: 02
 event: 2005
 data:  05  00  00  00  01
AMD_CB_EventNotify()
 event class: 05
 event: 2006
 data:  04  00  00  ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
  F3x80: e600e681
  F3x84: 80e641e6
  F3xD4: c8810f26
  F3xD8: 03001816
  F3xDC: 00006322
POST: 0x36
core0 started:
start_other_cores()
init node: 00  cores: 02
Start other core - nodeid: 00  cores: 02
POST: 0x37
started ap apicid: * AP 01started
* AP 02started

POST: 0x38
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30b40093 0x38005040
POST: 0x39
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b40093 0x3800240a
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
POST: 0x3b
fill_mem_ctrl()
POST: 0x40
raminit_amdmct()
raminit_amdmct begin:
 DIMMPresence: DIMMValid=2
 DIMMPresence: DIMMPresent=2
 DIMMPresence: RegDIMMPresent=0
 DIMMPresence: DimmECCPresent=0
 DIMMPresence: DimmPARPresent=0
 DIMMPresence: Dimmx4Present=0
 DIMMPresence: Dimmx8Present=2
 DIMMPresence: Dimmx16Present=0
 DIMMPresence: DimmPlPresent=0
 DIMMPresence: DimmDRPresent=2
 DIMMPresence: DimmQRPresent=0
 DIMMPresence: DATAload[0]=0
 DIMMPresence: MAload[0]=0
 DIMMPresence: MAdimms[0]=0
 DIMMPresence: DATAload[1]=2
 DIMMPresence: MAload[1]=10
 DIMMPresence: MAdimms[1]=1
 DIMMPresence: Status 1000
 DIMMPresence: ErrStatus 0
 DIMMPresence: ErrCode 0
 DIMMPresence: Done

DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 2
AutoCycTiming: Done

DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 3
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done

DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
 Node: 00  base: 00  limit: 7fffff  BottomIO: a00000
 Node: 00  base: 03  limit: 7fffff
 Node: 01  base: 00  limit: 00
 Node: 02  base: 00  limit: 00
 Node: 03  base: 00  limit: 00
 Node: 04  base: 00  limit: 00
 Node: 05  base: 00  limit: 00
 Node: 06  base: 00  limit: 00
 Node: 07  base: 00  limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
 CPUMemTyping: Cache32bTOP:800000
 CPUMemTyping: Bottom32bIO:800000
 CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done

mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1000
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done

InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done

mctAutoInitMCT_D: ECCInit_D
ECCInit: Node 00
ECCInit: Status 1000
ECCInit: ErrStatus 0
ECCInit: ErrCode 0
ECCInit: Done
mctAutoInitMCT_D Done: Global Status: 0
raminit_amdmct end:
CBMEM:
IMD: root @ 6ffff000 254 entries.
IMD: root @ 6fffec00 62 entries.
POST: 0x41
amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
POST: 0x42
Prepare CAR migration and stack regions... Fill [003fbc00-003fffff] ... Done
Copying data from cache to RAM...  Copy [000c4000-000c7d3f] to [003fc2c0 -
003fffff] ... Done
Switching to use RAM as stack... Top about 003fc2ac ... Done
Disabling cache as ram now
Prepare ramstage memory region...  Fill [00000000-003fbbff] ... Done
CBFS provider active.
CBFS @ 0 size ffc40
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 1bf40 size 19959
'fallback/ramstage' located at offset: 1bf78 size: 19959


coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 ramstage
starting...
POST: 0x39
Moving GDT to 6fffe700...ok
POST: 0x80
POST: 0x70
BS: BS_PRE_DEVICE times (us): entry 8 run 1065 exit 0
POST: 0x71
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1060 exit 0
POST: 0x72
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:18.0: enabled 1
   PCI: 00:00.0: enabled 1
   PCI: 00:01.0: enabled 1
   PCI: 00:02.0: enabled 1
   PCI: 00:03.0: enabled 1
   PCI: 00:04.0: enabled 1
   PCI: 00:05.0: enabled 0
   PCI: 00:06.0: enabled 0
   PCI: 00:07.0: enabled 0
   PCI: 00:08.0: enabled 0
   PCI: 00:09.0: enabled 1
   PCI: 00:0a.0: enabled 1
   PCI: 00:11.0: enabled 1
   PCI: 00:12.0: enabled 1
   PCI: 00:12.1: enabled 1
   PCI: 00:12.2: enabled 1
   PCI: 00:13.0: enabled 1
   PCI: 00:13.1: enabled 1
   PCI: 00:13.2: enabled 1
   PCI: 00:14.0: enabled 1
    I2C: 00:50: enabled 1
    I2C: 00:51: enabled 1
    I2C: 00:52: enabled 1
    I2C: 00:53: enabled 1
   PCI: 00:14.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00:14.3: enabled 1
    PNP: 002e.0: enabled 0
    PNP: 002e.1: enabled 1
    PNP: 002e.2: enabled 0
    PNP: 002e.3: enabled 0
    PNP: 002e.4: enabled 0
    PNP: 002e.5: enabled 1
    PNP: 002e.6: enabled 1
    PNP: 002e.7: enabled 0
    PNP: 002e.8: enabled 0
    PNP: 002e.9: enabled 0
    PNP: 002e.a: enabled 0
   PCI: 00:14.4: enabled 1
   PCI: 00:14.5: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
Mainboard MA785GMT-UD2H Enable. dev=0x0013a000
Init adt7461 end , status 0x02 fd
Dev3 is not present. GFX Configuration is One x16 slot
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
setup_uma_memory: uma size 0x10000000, memory start 0x70000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
  PCI: 00:18.3 siblings=2
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
POST: 0x25
PCI: 00:18.0 scanning...
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
POST: 0x24
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:02.0 subordinate bus PCI Express
PCI: 00:02.0 [1022/9603] enabled
PCI: Static device PCI: 00:03.0 not found, disabling it.
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/9604] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:05.0 subordinate bus PCI Express
PCI: 00:05.0 [1022/9605] disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:06.0 subordinate bus PCI Express
PCI: 00:06.0 [1022/9606] disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:07.0 subordinate bus PCI Express
PCI: 00:07.0 [1022/9607] disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:08.0 subordinate bus PCI Express
PCI: 00:08.0 [1022/960a] disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
POST: 0x25
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
POST: 0x24

(booting process stops here)
================
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150709/09863794/attachment-0001.html>

From no-reply at raptorengineeringinc.com  Fri Jul 10 08:45:36 2015
From: no-reply at raptorengineeringinc.com (Raptor Engineering Automated Coreboot Test Stand)
Date: Fri, 10 Jul 2015 01:45:36 -0500
Subject: [coreboot] ASUS KFSN4-DRE Automated Test Failure
Message-ID: <20150710064535.GA16949@cb-test-ctl>

The ASUS KFSN4-DRE fails verification as of commit 72dd90946fd472d4aebcad2952b463b868e662f2

The following tests failed:
CBMEM_TIMESTAMP_CONTENT_TRUNCATED

Commits since last successful test:


See attached log for details

This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand
Want to test on your own equipment?  Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit https://www.raptorengineeringinc.com for more information

Please contact Timothy Pearson at Raptor Engineering <tpearson at raptorengineeringinc.com> regarding any issues stemming from this notification
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 1436510721-0-automaster.log.bz2
Type: application/octet-stream
Size: 47024 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150710/e5a5f850/attachment-0001.obj>

From anatol.pomozov at gmail.com  Sat Jul 11 02:42:25 2015
From: anatol.pomozov at gmail.com (Anatol Pomozov)
Date: Fri, 10 Jul 2015 17:42:25 -0700
Subject: [coreboot] Cbfstool compilation error with gcc 5.1
In-Reply-To: <20150611013842.GB28112@coreboot.org>
References: <CAOMFOmVmy8yzndJofBVeL7Ha=Odeg_dYd3e2yO-0tKW5eHV=+A@mail.gmail.com>
 <20150611013842.GB28112@coreboot.org>
Message-ID: <CAOMFOmVnEwD8vv47i8twvHadLBermT6zLmO5v7_QyiCevMhx6w@mail.gmail.com>

Hi

Sorry for a long delay

On Wed, Jun 10, 2015 at 6:38 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> * Anatol Pomozov <anatol.pomozov at gmail.com> [150531 08:49]:
>> Hi
>>
>> I am trying to compile coreboot cbfstool on Arch where gcc 5.1 is used. And I
>> see following compilation error. I wonder if it is coreboot or gcc issue.

That's indeed looks like a false positive from GCC 5.1. And it happens
only if "-O2" flag present.

Here is what Ron proposed and it makes GCC happy again
http://review.coreboot.org/#/c/10881/

>>
>> ==> Starting build()...
>> make: Entering directory '/home/anatol/sources/archpackages/coreboot-utils-git/
>> src/coreboot/util/cbfstool'
>> mkdir -p ./
>> cc -D_FORTIFY_SOURCE=2 -D_DEFAULT_SOURCE  -D_POSIX_C_SOURCE=200809L  -Iflashmap
>> -march=x86-64 -mtune=generic -O2 -pipe -fstack-protector-strong --param=
>> ssp-buffer-size=4 -g3 -std=c99 -Werror -Wall -Wextra -Wcast-qual
>> -Wmissing-prototypes -Wredundant-decls -Wshadow -Wstrict-prototypes
>> -Wwrite-strings -c -o rmodule.o rmodule.c
>> rmodule.c: In function ?rmodule_create?:
>> rmodule.c:286:29: error: ?phdr? may be used uninitialized in this function
>> [-Werror=maybe-uninitialized]
>>         (phdr->p_vaddr + phdr->p_memsz))) {
>>                              ^
>> rmodule.c:203:14: note: ?phdr? was declared here
>>   Elf64_Phdr *phdr;
>>               ^
>> cc1: all warnings being treated as errors
>> Makefile:55: recipe for target 'rmodule.o' failed
>> make: *** [rmodule.o] Error 1
>> make: Leaving directory '/home/anatol/sources/archpackages/coreboot-utils-git/
>> src/coreboot/util/cbfstool'
>> ==> ERROR: A failure occurred in build().
>
> Looks like a false positive. ctx-phdr only gets passed on if nelements
> is 1, in which we know that phdr was set.
>
> Stefan
>


From izemmouri91 at gmail.com  Sat Jul 11 06:49:26 2015
From: izemmouri91 at gmail.com (Mohamed Zemmouri)
Date: Sat, 11 Jul 2015 05:49:26 +0100
Subject: [coreboot] Unsupported mainboard
Message-ID: <CA+1ivgS9O2nmi1Q-d55fdMR6HayH55mHkU42CL3MGWtFkZ991Q@mail.gmail.com>

Hi,

I intend to purchase a new mainboard based on Intel's new z97 chipset but
as I am a great fan of coreboot, I tried to look for the chipsets coreboot
supports and nowhere could I find Intel's z97. Now I am kind of hopping you
tell me I can't read or it got a different model name/number.
If indeed it's unsupported, do you think it will stay that way or will it
ever be ported to this chipest?

Best regards,

Iskander
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150711/b54a971f/attachment.html>

From paulepanter at users.sourceforge.net  Sat Jul 11 11:34:11 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sat, 11 Jul 2015 11:34:11 +0200
Subject: [coreboot] [HEADS UP] Time stamps for AGESA boards now measured
 relatively to start and not ramstage
Message-ID: <1436607251.2785.8.camel@users.sourceforge.net>

Dear coreboot folks,


thanks to the latest time stamp work and especially thanks to Aaron
Durbin?s latest fix up commit bd1499d3 (timestamps: don't drop ramstage
timestamps with EARLY_CBMEM_INIT) [1], the ramstage time stamps on
AGESA boards ? I only tested with the ASRock E350M1 ? seem to be
measured relative to the system start and not relatively to start of
ramstage.

Before time stamps were measured relatively to ramstage.

$ more asrock/e350m1/4.0-10267-g72dd909/2015-07-10T00\:11\:47Z/coreboot_timestamps.txt
12 entries total:

  10:start of ramstage                                 0
  30:device enumeration                                8 (8)
  40:device configuration                              94,880 (94,872)
  50:device enable                                     98,697 (3,816)
  60:device initialization                             108,662 (9,965)
  70:device setup done                                 122,998 (14,335)
  75:cbmem post                                        123,369 (371)
  80:write tables                                      123,374 (4)
  90:load payload                                      128,020 (4,646)
  15:starting LZMA decompress (ignore for x86)         128,275 (254)
  16:finished LZMA decompress (ignore for x86)         146,142 (17,866)
  99:selfboot jump                                     146,163 (21)

With the latest changes we they are measured relatively to system start.

$ more asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
12 entries total:

  10:start of ramstage                                 385,974
  30:device enumeration                                385,982 (8)
  40:device configuration                              480,233 (94,250)
  50:device enable                                     484,088 (3,855)
  60:device initialization                             494,049 (9,960)
  70:device setup done                                 508,368 (14,318)
  75:cbmem post                                        508,736 (368)
  80:write tables                                      508,741 (4)
  90:load payload                                      513,320 (4,579)
  15:starting LZMA decompress (ignore for x86)         513,574 (253)
  16:finished LZMA decompress (ignore for x86)         531,423 (17,848)
  99:selfboot jump                                     531,445 (21)

So 386 ms for romstage with AGESA is still an acceptable number. This
confirms, which was already known. AGESA does a pretty good job.

Time stamps from romstage are still not preserved though, which is a
well known limitation though.


Thanks,

Paul


[1] http://review.coreboot.org/10880
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150711/8ed77867/attachment.asc>

From adurbin at google.com  Sat Jul 11 15:00:57 2015
From: adurbin at google.com (Aaron Durbin)
Date: Sat, 11 Jul 2015 08:00:57 -0500
Subject: [coreboot] [HEADS UP] Time stamps for AGESA boards now measured
 relatively to start and not ramstage
In-Reply-To: <1436607251.2785.8.camel@users.sourceforge.net>
References: <1436607251.2785.8.camel@users.sourceforge.net>
Message-ID: <CAE2855tN3aQLV6NCMw7k_xQtK5H0B6uY4kZUt-MAX+dqGShTHQ@mail.gmail.com>

On Sat, Jul 11, 2015 at 4:34 AM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Dear coreboot folks,
>
>
> thanks to the latest time stamp work and especially thanks to Aaron
> Durbin?s latest fix up commit bd1499d3 (timestamps: don't drop ramstage
> timestamps with EARLY_CBMEM_INIT) [1], the ramstage time stamps on
> AGESA boards ? I only tested with the ASRock E350M1 ? seem to be
> measured relative to the system start and not relatively to start of
> ramstage.
>
> Before time stamps were measured relatively to ramstage.
>
> $ more asrock/e350m1/4.0-10267-g72dd909/2015-07-10T00\:11\:47Z/coreboot_timestamps.txt
> 12 entries total:
>
>   10:start of ramstage                                 0
>   30:device enumeration                                8 (8)
>   40:device configuration                              94,880 (94,872)
>   50:device enable                                     98,697 (3,816)
>   60:device initialization                             108,662 (9,965)
>   70:device setup done                                 122,998 (14,335)
>   75:cbmem post                                        123,369 (371)
>   80:write tables                                      123,374 (4)
>   90:load payload                                      128,020 (4,646)
>   15:starting LZMA decompress (ignore for x86)         128,275 (254)
>   16:finished LZMA decompress (ignore for x86)         146,142 (17,866)
>   99:selfboot jump                                     146,163 (21)
>
> With the latest changes we they are measured relatively to system start.
>
> $ more asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
> 12 entries total:
>
>   10:start of ramstage                                 385,974
>   30:device enumeration                                385,982 (8)
>   40:device configuration                              480,233 (94,250)
>   50:device enable                                     484,088 (3,855)
>   60:device initialization                             494,049 (9,960)
>   70:device setup done                                 508,368 (14,318)
>   75:cbmem post                                        508,736 (368)
>   80:write tables                                      508,741 (4)
>   90:load payload                                      513,320 (4,579)
>   15:starting LZMA decompress (ignore for x86)         513,574 (253)
>   16:finished LZMA decompress (ignore for x86)         531,423 (17,848)
>   99:selfboot jump                                     531,445 (21)
>

This is actually surprising, but I just looked into it. I see why;
it's from my most recent change. If I guard with
CONFIG_EARLY_CBMEM_INIT it'd go back to the previous way. But I
actually do like this way (though unintended). The base_time was never
properly exported it from cbmem:

>-------for (i = 0; i < tst_p->num_entries; i++) {
>------->-------const struct timestamp_entry *tse_p = tst_p->entries + i;
>------->-------timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp,
>------->------->-------i ? tse_p[-1].entry_stamp : 0);
>-------}

It always assumed 0 as a base_time. Without the diff below base_time
is actually 0 in this case so you see the accumulated time until
ramstage started. I actually think we should fix cbmem.c to not pass 0
as prev_stamp for 0th index. It should be passing base_time as well as
reporting what base_time was from an informational perspective.

If we want to change it back it's not that hard:

diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
index 7ead383..ca25093 100644
--- a/src/lib/timestamp.c
+++ b/src/lib/timestamp.c
@@ -202,7 +202,7 @@ void timestamp_init(uint64_t base)
        /* In the EARLY_CBMEM_INIT case timestamps could have already been
         * recovered. In those circumstances honor the cache which sits in BSS
         * as it has already been initialized. */
-       if (ENV_RAMSTAGE &&
+       if (ENV_RAMSTAGE && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) &&
            ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED)
                return;


> So 386 ms for romstage with AGESA is still an acceptable number. This
> confirms, which was already known. AGESA does a pretty good job.
>
> Time stamps from romstage are still not preserved though, which is a
> well known limitation though.
>
>
> Thanks,
>
> Paul
>
>
> [1] http://review.coreboot.org/10880
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From paulepanter at users.sourceforge.net  Sat Jul 11 18:52:46 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sat, 11 Jul 2015 18:52:46 +0200
Subject: [coreboot] [HEADS UP] Time stamps for AGESA boards now measured
 relatively to start and not ramstage
In-Reply-To: <CAE2855tN3aQLV6NCMw7k_xQtK5H0B6uY4kZUt-MAX+dqGShTHQ@mail.gmail.com>
References: <1436607251.2785.8.camel@users.sourceforge.net>
 <CAE2855tN3aQLV6NCMw7k_xQtK5H0B6uY4kZUt-MAX+dqGShTHQ@mail.gmail.com>
Message-ID: <1436633566.7260.7.camel@users.sourceforge.net>

Am Samstag, den 11.07.2015, 08:00 -0500 schrieb Aaron Durbin:
> On Sat, Jul 11, 2015 at 4:34 AM, Paul Menzel wrote:

[?]

> > With the latest changes we they are measured relatively to system 
> > start.
> > 
> > $ more asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
> > 12 entries total:
> > 
> >   10:start of ramstage                                 385,974
> >   30:device enumeration                                385,982 (8)
> >   40:device configuration                              480,233 (94,250)
> >   50:device enable                                     484,088 (3,855)
> >   60:device initialization                             494,049 (9,960)
> >   70:device setup done                                 508,368 (14,318)
> >   75:cbmem post                                        508,736 (368)
> >   80:write tables                                      508,741 (4)
> >   90:load payload                                      513,320 (4,579)
> >   15:starting LZMA decompress (ignore for x86)         513,574 (253)
> >   16:finished LZMA decompress (ignore for x86)         531,423 (17,848)
> >   99:selfboot jump                                     531,445 (21)
> 
> This is actually surprising, but I just looked into it. I see why;
> it's from my most recent change.

yes, I also assumed it was due to your change set [1].

> If I guard with CONFIG_EARLY_CBMEM_INIT it'd go back to the previous 
> way.

I do too.

> But I actually do like this way (though unintended). The base_time 
> was  never properly exported it from cbmem:
> 
> > -------for (i = 0; i < tst_p->num_entries; i++) {
> > ------->-------const struct timestamp_entry *tse_p = tst_p->entries + i;
> > ------->-------timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp,
> > ------->------->-------i ? tse_p[-1].entry_stamp : 0);
> > -------}
> 
> It always assumed 0 as a base_time. Without the diff below base_time
> is actually 0 in this case so you see the accumulated time until
> ramstage started. I actually think we should fix cbmem.c to not pass 0
> as prev_stamp for 0th index. It should be passing base_time as well as
> reporting what base_time was from an informational perspective.

I totally agree.

> If we want to change it back it's not that hard:

[?]

I can?t think of a reason, why we?d want to have the old behavior back.


Thanks,

Paul


> > [1] http://review.coreboot.org/10880
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150711/7b735c23/attachment.asc>

From adurbin at google.com  Sat Jul 11 19:51:12 2015
From: adurbin at google.com (Aaron Durbin)
Date: Sat, 11 Jul 2015 12:51:12 -0500
Subject: [coreboot] [HEADS UP] Time stamps for AGESA boards now measured
 relatively to start and not ramstage
In-Reply-To: <1436633566.7260.7.camel@users.sourceforge.net>
References: <1436607251.2785.8.camel@users.sourceforge.net>
 <CAE2855tN3aQLV6NCMw7k_xQtK5H0B6uY4kZUt-MAX+dqGShTHQ@mail.gmail.com>
 <1436633566.7260.7.camel@users.sourceforge.net>
Message-ID: <CAE2855vkXWmbX3T7S0-mRhqzGcLHrt7=F3Cq2pSDXS6o=Sia7g@mail.gmail.com>

On Sat, Jul 11, 2015 at 11:52 AM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Am Samstag, den 11.07.2015, 08:00 -0500 schrieb Aaron Durbin:
>> On Sat, Jul 11, 2015 at 4:34 AM, Paul Menzel wrote:
>
> [?]
>
>> > With the latest changes we they are measured relatively to system
>> > start.
>> >
>> > $ more asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
>> > 12 entries total:
>> >
>> >   10:start of ramstage                                 385,974
>> >   30:device enumeration                                385,982 (8)
>> >   40:device configuration                              480,233 (94,250)
>> >   50:device enable                                     484,088 (3,855)
>> >   60:device initialization                             494,049 (9,960)
>> >   70:device setup done                                 508,368 (14,318)
>> >   75:cbmem post                                        508,736 (368)
>> >   80:write tables                                      508,741 (4)
>> >   90:load payload                                      513,320 (4,579)
>> >   15:starting LZMA decompress (ignore for x86)         513,574 (253)
>> >   16:finished LZMA decompress (ignore for x86)         531,423 (17,848)
>> >   99:selfboot jump                                     531,445 (21)
>>
>> This is actually surprising, but I just looked into it. I see why;
>> it's from my most recent change.
>
> yes, I also assumed it was due to your change set [1].
>
>> If I guard with CONFIG_EARLY_CBMEM_INIT it'd go back to the previous
>> way.
>
> I do too.
>
>> But I actually do like this way (though unintended). The base_time
>> was  never properly exported it from cbmem:
>>
>> > -------for (i = 0; i < tst_p->num_entries; i++) {
>> > ------->-------const struct timestamp_entry *tse_p = tst_p->entries + i;
>> > ------->-------timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp,
>> > ------->------->-------i ? tse_p[-1].entry_stamp : 0);
>> > -------}
>>
>> It always assumed 0 as a base_time. Without the diff below base_time
>> is actually 0 in this case so you see the accumulated time until
>> ramstage started. I actually think we should fix cbmem.c to not pass 0
>> as prev_stamp for 0th index. It should be passing base_time as well as
>> reporting what base_time was from an informational perspective.
>
> I totally agree.

Care to test this and show the output? See what you like?  I don't
have a machine up to test against at the moment. The same information
is there, but it's shown in a different way in that base_time is
reported as an entry of '1st timestamp'. Your example would change to
something like this:

   0:1st timestamp                                     385,974
 10:start of ramstage                                 385,975 (1)
  30:device enumeration                                385,983 (8)
...

http://review.coreboot.org/10883

>
>> If we want to change it back it's not that hard:
>
> [?]
>
> I can?t think of a reason, why we?d want to have the old behavior back.
>
>
> Thanks,
>
> Paul
>
>
>> > [1] http://review.coreboot.org/10880


From adurbin at google.com  Sat Jul 11 20:43:00 2015
From: adurbin at google.com (Aaron Durbin)
Date: Sat, 11 Jul 2015 13:43:00 -0500
Subject: [coreboot] [HEADS UP] Time stamps for AGESA boards now measured
 relatively to start and not ramstage
In-Reply-To: <CAE2855vkXWmbX3T7S0-mRhqzGcLHrt7=F3Cq2pSDXS6o=Sia7g@mail.gmail.com>
References: <1436607251.2785.8.camel@users.sourceforge.net>
 <CAE2855tN3aQLV6NCMw7k_xQtK5H0B6uY4kZUt-MAX+dqGShTHQ@mail.gmail.com>
 <1436633566.7260.7.camel@users.sourceforge.net>
 <CAE2855vkXWmbX3T7S0-mRhqzGcLHrt7=F3Cq2pSDXS6o=Sia7g@mail.gmail.com>
Message-ID: <CAE2855u9dz0jT3A_tbB2Hrj44VPxbOkVqWGwOcU=rap4aVuRzQ@mail.gmail.com>

On Sat, Jul 11, 2015 at 12:51 PM, Aaron Durbin <adurbin at google.com> wrote:
> On Sat, Jul 11, 2015 at 11:52 AM, Paul Menzel
> <paulepanter at users.sourceforge.net> wrote:
>> Am Samstag, den 11.07.2015, 08:00 -0500 schrieb Aaron Durbin:
>>> On Sat, Jul 11, 2015 at 4:34 AM, Paul Menzel wrote:
>>
>> [?]
>>
>>> > With the latest changes we they are measured relatively to system
>>> > start.
>>> >
>>> > $ more asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
>>> > 12 entries total:
>>> >
>>> >   10:start of ramstage                                 385,974
>>> >   30:device enumeration                                385,982 (8)
>>> >   40:device configuration                              480,233 (94,250)
>>> >   50:device enable                                     484,088 (3,855)
>>> >   60:device initialization                             494,049 (9,960)
>>> >   70:device setup done                                 508,368 (14,318)
>>> >   75:cbmem post                                        508,736 (368)
>>> >   80:write tables                                      508,741 (4)
>>> >   90:load payload                                      513,320 (4,579)
>>> >   15:starting LZMA decompress (ignore for x86)         513,574 (253)
>>> >   16:finished LZMA decompress (ignore for x86)         531,423 (17,848)
>>> >   99:selfboot jump                                     531,445 (21)
>>>
>>> This is actually surprising, but I just looked into it. I see why;
>>> it's from my most recent change.
>>
>> yes, I also assumed it was due to your change set [1].
>>
>>> If I guard with CONFIG_EARLY_CBMEM_INIT it'd go back to the previous
>>> way.
>>
>> I do too.
>>
>>> But I actually do like this way (though unintended). The base_time
>>> was  never properly exported it from cbmem:
>>>
>>> > -------for (i = 0; i < tst_p->num_entries; i++) {
>>> > ------->-------const struct timestamp_entry *tse_p = tst_p->entries + i;
>>> > ------->-------timestamp_print_entry(tse_p->entry_id, tse_p->entry_stamp,
>>> > ------->------->-------i ? tse_p[-1].entry_stamp : 0);
>>> > -------}
>>>
>>> It always assumed 0 as a base_time. Without the diff below base_time
>>> is actually 0 in this case so you see the accumulated time until
>>> ramstage started. I actually think we should fix cbmem.c to not pass 0
>>> as prev_stamp for 0th index. It should be passing base_time as well as
>>> reporting what base_time was from an informational perspective.
>>
>> I totally agree.
>
> Care to test this and show the output? See what you like?  I don't
> have a machine up to test against at the moment. The same information
> is there, but it's shown in a different way in that base_time is
> reported as an entry of '1st timestamp'. Your example would change to
> something like this:
>
>    0:1st timestamp                                     385,974
>  10:start of ramstage                                 385,975 (1)
>   30:device enumeration                                385,983 (8)
> ...
>
> http://review.coreboot.org/10883

Sorry. You'll see 0 for '1st timestamp' w/ just that patch. However if
you test with the following patch (as my original reply) as well then
you should see the visibility as I noted above:

http://review.coreboot.org/10884

>
>>
>>> If we want to change it back it's not that hard:
>>
>> [?]
>>
>> I can?t think of a reason, why we?d want to have the old behavior back.
>>
>>
>> Thanks,
>>
>> Paul
>>
>>
>>> > [1] http://review.coreboot.org/10880


From info at gluglug.org.uk  Sun Jul 12 02:13:02 2015
From: info at gluglug.org.uk (Francis Rowe)
Date: Sun, 12 Jul 2015 01:13:02 +0100
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
Message-ID: <55A1B10E.7090503@gluglug.org.uk>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1



On 03/07/15 15:27, kroms at posteo.be wrote:
> Hello,
> 
> I allready contacted Francis from libreboot and he forwared me to
> this list, because it seems to be an issue regarding coreboot.
> 
> I have flashed a Lenovo T400 with libreboot.
> 
> The T400 has an Intel GPU and I am able to use it with an external 
> display connected to the onboard vga-port.
> 
> The issue is, that I can't use the internal display, which is an 
> 1440x900 Samusung LTN141WD-L05, EDID dump:
> 
> https://paste.debian.net/plainh/b3699c60
> 
> It seems like the internal screen is powered on while booting but
> it stays black.
> 
> Francis assumes that this is due to bugs in how coreboot handles
> the EDID.
> 
> Here is an EDID dump of a working display:
> 
> http://paste.debian.net/plainh/776705d5
> 
> Anyone is able to help?
> 
> Thanks in advance!
> 
> 
> 

Dear coreboot community,

tty0_ in #coreboot/#libreboot found a partial fix.

See:
http://libreboot.org/docs/hcl/gm45_lcd.html

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBAgAGBQJVobEOAAoJEP9Ft0z50c+UJSgH/3tj9DiBbitS1eCgJ98743Ij
sARuL4cFbUNMeT6nZmnhMEmv+O8Na9SO2yuvVb/iqcYLzbQc6gGmD8wzIln77c+c
jXZ+Tje7RSwwCJvt3gDtXG1UTvnDGthJy+qUh5JqQxyNljSNFUQNCpkZw/vhAgJa
aXcxO8w1W7eFRO5ueTR0HqF57JQXjyNBTicfCKqRpRJ/ac93ipbuKQBAIUywjjdD
+LD3a31RfEjmd8YpAzEXbvUhl3b4NWTuy0nqQj9amaQGeJKycNSAYisLKqriPZXe
r0WW9mfSUWWPTYpTtRREK8uBkKmRF0qMLKZES2B9SiDsZ3RcF0+CRAP+6UTwP+Y=
=gxaG
-----END PGP SIGNATURE-----


From peter90609 at gmail.com  Sat Jul 11 10:45:07 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Sat, 11 Jul 2015 16:45:07 +0800
Subject: [coreboot] Problems about making disk image( qemu-img ... )
Message-ID: <CACS=nFNv_QVsve8wQVkGUA3WCBuQORc-WxOq3FOVNxV_pCfSYg@mail.gmail.com>

Hello,
I want to boot linux by QEMU with coreboot ,and I have some problems in
making Linux image.
I followed the steps on QEMU Build Tutorial form coreboot.org.
(http://www.coreboot.org/QEMU_Build_Tutorial)
As the Creating a hard disk image section points out:
1.qemu-img create -f raw disk.img 200M
2.mkfs.ext2 -F disk.img
3.mkdir /mnt/rootfs
4. mount -o loop disk.img /mnt/rootfs
5.mkdir /mnt/root/boot
6.cp vmlinux /mnt/rootfs/boot/vmlinuz
7.cp *initrd.img* /mnt/rootfs/boot/initrd
8.*cp -R /* /mnt/rootfs *

I've done all the steps above, but the image doesn't work on QEMU.

What does the 8th step mean? Does it act as *filesystem*?
If so, could I only copy the directories and the root filesystem to make it
work?

I want to know how to build the image.
P.S. my Linux distribution is ubuntu 14.04

Many thanks.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150711/b3efd479/attachment-0001.html>

From paulepanter at users.sourceforge.net  Sun Jul 12 11:21:08 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 12 Jul 2015 11:21:08 +0200
Subject: [coreboot] Please turn on CBMEM console for payloads in Libreboot
 (was: T400 screen issue / EDID handling)
In-Reply-To: <1436082138.13469.47.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
Message-ID: <1436692868.11693.5.camel@users.sourceforge.net>

Dear Libreboot folks,


Am Sonntag, den 05.07.2015, 09:42 +0200 schrieb Paul Menzel:
> Am Samstag, den 04.07.2015, 11:11 +0200 schrieb kroms at posteo.be:

[?]

> > the payload -> I dont know to get or find it.
> 
> It is GRUB. Unfortunately, I do not see GRUB?s debug messages in 
> CBMEM.

Could you please enable logging to CBMEM console in your payloads? For
GRUB you?d need to enable the CBMEM console terminal by adding the line
below below your terminal setting in your `etc/grub.cfg` in CBFS.

    terminal_output --append cbmemc

Maybe Vladimir has some other suggestions.


Thanks,

Paul
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150712/7520c499/attachment.asc>

From paulepanter at users.sourceforge.net  Sun Jul 12 11:38:12 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Sun, 12 Jul 2015 11:38:12 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
Message-ID: <1436693892.11693.13.camel@users.sourceforge.net>

Dear Kroms,


I am sorry for the long delay.

Am Sonntag, den 05.07.2015, 17:05 +0200 schrieb kroms at posteo.be:

> > It might be in the revision file in CBFS.
> > 
> >     build/cbfstool build/coreboot.rom extract -n revision -f revision.txt
> 
> Please find attached the revision.txt.

Thank you! Unfortunately, it also does not contain the Git revision.

    #define COREBOOT_ORIGIN_GIT_REVISION "Unknown"

> > > and Linux -> Do you mean the output of dmesg?
> > 
> > Indeed, that?s one way of getting them. Please provide the output.
> 
> It is also attached. I hope the information will help you to get 
> closer to the solution.

Thank you! Unfortunately, no useful i915 message are in there. Three
things to try and do.

1. Try to use a newer Linux kernel. Trying to fix the Linux kernel is
much easier and more likely, if the reports are against the latest
version. Do you have a spare disk with a newer Linux kernel
installed?Debian Sid/unstable currently ships Linux 4.0.8. Linux 4.1
could be installed from the Debian experimental archives.

2. Turn on debugging of the Linux i915 module [1].

> To obtain a dmesg with debug information, add drm.debug=0xe to your
> kernel command line or, if you have display issues with kernel 4.1
> or newer, use drm.debug=0x1e log_buf_len=1M instead. Then, reboot
> and reproduce the issue again. Make sure to attach the full dmesg
> all the way from boot.

3. Please also post a log with debugging enabled when using the vendor
firmware.


Thanks,

Paul


[1] https://01.org/linuxgraphics/documentation/how-report-bugs
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150712/a9ea36f9/attachment.asc>

From kroms at posteo.be  Sun Jul 12 22:17:30 2015
From: kroms at posteo.be (kroms at posteo.be)
Date: Sun, 12 Jul 2015 22:17:30 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <1436693892.11693.13.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
 <1436693892.11693.13.camel@users.sourceforge.net>
Message-ID: <8f7e0fb7e2c7275c7e495f21efd55efc@posteo.de>

Dear Paul,

> I am sorry for the long delay.

No problem, I am very happy that you are still trying to help!

> Thank you! Unfortunately, it also does not contain the Git revision.
> 
>     #define COREBOOT_ORIGIN_GIT_REVISION "Unknown"
> 

I dont?t know if you noticed that Francis wrote in this thread on Sun 
Jul 5 16:57:30 CEST 2015:

"Libreboot builds coreboot without the .git directory, so it's not
possible to get the coreboot revision. You can find out what version
of coreboot it is by looking at
resources/scripts/helpers/download/coreboot

He is using libreboot 20150518, so the coreboot revision that he's
using is e19c8b0091022ae3f490601aed0c290cd5171b79"

> 1. Try to use a newer Linux kernel.

I updated the Kernel to 4.1.2 from Debian experimental.

> 2. Turn on debugging of the Linux i915 module [1].

> 3. Please also post a log with debugging enabled when using the vendor
> firmware.

Please find attached the two outputs (libreboot and lenovo_bios) from 
dmesg with debugging enabled.

Thanks again,

Kroms

-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: dmesg_debug_libreboot.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150712/d2e214bb/attachment-0002.txt>
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: dmesg_debug_lenovo_bios.txt
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150712/d2e214bb/attachment-0003.txt>

From info at gluglug.org.uk  Sun Jul 12 22:55:29 2015
From: info at gluglug.org.uk (Francis Rowe)
Date: Sun, 12 Jul 2015 21:55:29 +0100
Subject: [coreboot] Please turn on CBMEM console for payloads in
	Libreboot
In-Reply-To: <1436692868.11693.5.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <1436692868.11693.5.camel@users.sourceforge.net>
Message-ID: <55A2D441.5010101@gluglug.org.uk>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1



On 12/07/15 10:21, Paul Menzel wrote:
> Dear Libreboot folks,
> 
> 
> Am Sonntag, den 05.07.2015, 09:42 +0200 schrieb Paul Menzel:
>> Am Samstag, den 04.07.2015, 11:11 +0200 schrieb kroms at posteo.be:
> 
> [?]
> 
>>> the payload -> I dont know to get or find it.
>> 
>> It is GRUB. Unfortunately, I do not see GRUB?s debug messages in
>>  CBMEM.
> 
> Could you please enable logging to CBMEM console in your payloads?
> For GRUB you?d need to enable the CBMEM console terminal by adding
> the line below below your terminal setting in your `etc/grub.cfg`
> in CBFS.
> 
> terminal_output --append cbmemc
> 

Done.

http://git.savannah.gnu.org/cgit/libreboot.git/commit/?id=08b4126023fa16f1d473fa71800560e84f4684da

> Maybe Vladimir has some other suggestions.
> 

I will ask him.


-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQEcBAEBAgAGBQJVotRBAAoJEP9Ft0z50c+U7VEIAIFwkPVg9J3qtkOlFj6AMR7x
gLXZjbZKIiFF67RI36eEJDWOzeMm8mYz4ZrijfZpOYcLQ0xkvsBGXJNtPQ18uMC5
OG+BEYf5Cw1yCR8IVAmIjGl2DjKo5Hr57HKTnU0q1mNNPKftnmgaWU0cCd1BGG5x
gjJSqY/0ZX8KSGPZMM1Oj163CtYsRJOv3JLPBugdsi8exyWeJja9MWSJrh7A81KW
V8/pFLvnEOMxyiSKVyd6M6i8zHQymmQIGOIizXPTUXVP+yigVbiDhQ57lviNvk8J
2QjJDEhzYQR1kam4OAVeZ2ONsLgY7KiTTsouxZeTGCrOwKw2KgIdPBtw7/TwRYA=
=kHvy
-----END PGP SIGNATURE-----


From gaumless at gmail.com  Mon Jul 13 00:24:06 2015
From: gaumless at gmail.com (Martin Roth)
Date: Sun, 12 Jul 2015 16:24:06 -0600
Subject: [coreboot] Syntax Highlighting for ACPI ASL,
	devicetree.cb and Kconfig files
In-Reply-To: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
Message-ID: <55A2E906.4010700@gmail.com>

I've just posted syntax highlighting files for ASL, Kconfig and 
devicetree.cb for a few editors if anyone wants to try them out.

vim:
ASL - https://github.com/martinlroth/vim-acpi-asl
devicetree.cb - https://github.com/martinlroth/vim-devicetree
Kconfig is alredy supported in vim.

atom:
ASL - not done yet
devicetree.cb - https://github.com/martinlroth/language-devicetree
Kconfig - https://github.com/martinlroth/language-kconfig

Ultraedit:
ASL - https://github.com/martinlroth/wordfiles/blob/master/acpi.uew
devicetree.cb - 
https://github.com/martinlroth/wordfiles/blob/master/devicetree_cb.uew
Kconfig - https://github.com/martinlroth/wordfiles/blob/master/kconfig.uew

If there's interest in syntax highlighting for other editors,, let me 
know, and I'll see what I can do.

Martin


From paulepanter at users.sourceforge.net  Mon Jul 13 07:57:00 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Mon, 13 Jul 2015 07:57:00 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <8f7e0fb7e2c7275c7e495f21efd55efc@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
 <1436693892.11693.13.camel@users.sourceforge.net>
 <8f7e0fb7e2c7275c7e495f21efd55efc@posteo.de>
Message-ID: <1436767020.3586.53.camel@users.sourceforge.net>

Dear Kroms,


Am Sonntag, den 12.07.2015, 22:17 +0200 schrieb kroms at posteo.be:

> > Thank you! Unfortunately, it also does not contain the Git 
> > revision.
> > 
> >     #define COREBOOT_ORIGIN_GIT_REVISION "Unknown"
> > 
> 
> I dont?t know if you noticed that Francis wrote in this thread on Sun 
> 
> Jul 5 16:57:30 CEST 2015:
> 
> "Libreboot builds coreboot without the .git directory, so it's not
> possible to get the coreboot revision. You can find out what version
> of coreboot it is by looking at
> resources/scripts/helpers/download/coreboot
> 
> He is using libreboot 20150518, so the coreboot revision that he's
> using is e19c8b0091022ae3f490601aed0c290cd5171b79"

Thank you for looking this up!

    commit e19c8b0091022ae3f490601aed0c290cd5171b79
    Author:     Alexander Couzens <    lynxis at fe80.eu    >
    AuthorDate: Thu Apr 2 23:20:45 2015 +0200
    Commit:     Peter Stuge <    peter at stuge.se    >
    CommitDate: Sun Apr 5 04:07:25 2015 +0200

        acpi: protect acpi generators from PRE_RAM & SMM

> > 1. Try to use a newer Linux kernel.
> 
> I updated the Kernel to 4.1.2 from Debian experimental.
> 
> > 2. Turn on debugging of the Linux i915 module [1].
> 
> > 3. Please also post a log with debugging enabled when using the 
> > vendor firmware.
> 
> Please find attached the two outputs (libreboot and lenovo_bios) from 
> 
> dmesg with debugging enabled.

Awesome! Thank you very much.

    $ grep 'drm:' dmesg_debug_libreboot.txt
    [   11.647383] [drm:i915_dump_device_info] i915 device info: gen=4, pciid=0x2a42 rev=0x07 flags=is_mobile,need_gfx_hws,is_g4x,has_fbc,has_pipe_cxsr,has_hotplug,supports_tv,
    [   11.647410] [drm:intel_detect_pch] No PCH found.
    [   11.647416] [drm:i915_gem_gtt_init] GMADR size = 256M
    [   11.647418] [drm:i915_gem_gtt_init] GTT stolen size = 32M
    [   11.647419] [drm:i915_gem_gtt_init] ppgtt mode: 0
    [   11.648615] [drm:intel_opregion_setup] graphic opregion physical addr: 0x0
    [   11.648618] [drm:intel_opregion_setup] ACPI OpRegion not supported!
    [   11.648665] [drm:intel_device_info_runtime_init] slice total: 0
    [   11.648666] [drm:intel_device_info_runtime_init] subslice total: 0
    [   11.648668] [drm:intel_device_info_runtime_init] subslice per slice: 0
    [   11.648670] [drm:intel_device_info_runtime_init] EU total: 0
    [   11.648671] [drm:intel_device_info_runtime_init] EU per subslice: 0
    [   11.648672] [drm:intel_device_info_runtime_init] has slice power gating: n
    [   11.648674] [drm:intel_device_info_runtime_init] has subslice power gating: n
    [   11.648676] [drm:intel_device_info_runtime_init] has EU power gating: n
    [   11.648680] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz
    [   11.648684] [drm:validate_vbt] Using VBT from PCI ROM: $VBT IRONLAKE-MOBILEd
    [   11.648687] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 1 lvds_use_ssc 1 lvds_ssc_freq 96000 display_clock_mode 0 fdi_rx_polarity_inverted 0
    [   11.648689] [drm:parse_sdvo_device_mapping] No general definition block is found, unable to construct sdvo mapping.
    [   11.648691] [drm:parse_device_mapping] No general definition block is found, no devices defined.
    [   11.648693] [drm:parse_psr] No PSR BDB found.
    [   11.648700] [drm:intel_dsm_pci_probe] no _DSM method for intel device
    [   11.648707] [drm:i915_gem_init_stolen] found 33554432 bytes of stolen memory at be000000
    [   11.648710] [drm:intel_display_power_get] enabling always-on
    [   11.648744] [drm:intel_modeset_init] 2 display pipes available.
    [   11.648753] [drm:intel_modeset_init] pipe A sprite A init failed: -19
    [   11.648760] [drm:intel_modeset_init] pipe B sprite B init failed: -19
    [   11.718062] [drm:intel_lvds_init] using preferred mode from EDID: 
    [   11.718069] [drm:drm_mode_debug_printmodeline] Modeline 27:"1440x900" 60 101600 1440 1488 1520 1792 900 903 909 945 0x48 0xa
    [   11.718075] [drm:intel_lvds_init] detected single-link lvds configuration
    [   11.718147] [drm:intel_panel_setup_backlight] Connector LVDS-1 backlight initialized, enabled, brightness 98/98
    [   11.718205] [drm:intel_setup_outputs] probing SDVOB
    [   11.718209] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus dpb. force bit now 1
    [   11.727609] [drm:intel_sdvo_read_byte] i2c transfer returned -6
    [   11.727611] [drm:intel_sdvo_init] No SDVO device found on SDVOB
    [   11.727642] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus dpb. force bit now 0
    [   11.727644] [drm:intel_setup_outputs] probing HDMI on SDVOB
    [   11.727701] [drm:intel_dp_init_connector] Adding DP connector on port B
    [   11.727743] [drm:intel_dp_aux_init] registering DPDDC-B bus for card0-DP-1
    [   11.727781] [drm:intel_setup_outputs] probing SDVOC
    [   11.727783] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus dpb. force bit now 1
    [   11.737209] [drm:intel_sdvo_read_byte] i2c transfer returned -6
    [   11.737212] [drm:intel_sdvo_init] No SDVO device found on SDVOC
    [   11.740675] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus dpb. force bit now 0
    [   11.740681] [drm:intel_setup_outputs] probing HDMI on SDVOC
    [   11.740749] [drm:intel_dp_init_connector] Adding DP connector on port C
    [   11.740788] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-2
    [   11.740838] [drm:intel_dp_init_connector] Adding DP connector on port D
    [   11.740879] [drm:intel_dp_aux_init] registering DPDDC-D bus for card0-DP-3
    [   11.740927] [drm:intel_modeset_readout_hw_state] [CRTC:20] hw state readout: enabled
    [   11.740930] [drm:intel_modeset_readout_hw_state] [CRTC:23] hw state readout: disabled
    [   11.740933] [drm:intel_modeset_readout_hw_state] [ENCODER:25:LVDS-25] hw state readout: enabled, pipe A
    [   11.740935] [drm:intel_modeset_readout_hw_state] [ENCODER:32:DAC-32] hw state readout: disabled, pipe A
    [   11.740938] [drm:intel_modeset_readout_hw_state] [ENCODER:33:TMDS-33] hw state readout: disabled, pipe A
    [   11.740941] [drm:intel_modeset_readout_hw_state] [ENCODER:38:TMDS-38] hw state readout: disabled, pipe A
    [   11.740943] [drm:intel_modeset_readout_hw_state] [ENCODER:40:TMDS-40] hw state readout: disabled, pipe A
    [   11.740945] [drm:intel_modeset_readout_hw_state] [ENCODER:42:TMDS-42] hw state readout: disabled, pipe A
    [   11.740948] [drm:intel_modeset_readout_hw_state] [ENCODER:44:TMDS-44] hw state readout: disabled, pipe A
    [   11.740950] [drm:intel_modeset_readout_hw_state] [CONNECTOR:24:LVDS-1] hw state readout: enabled
    [   11.740952] [drm:intel_modeset_readout_hw_state] [CONNECTOR:31:VGA-1] hw state readout: disabled
    [   11.740955] [drm:intel_modeset_readout_hw_state] [CONNECTOR:34:HDMI-A-1] hw state readout: disabled
    [   11.740957] [drm:intel_modeset_readout_hw_state] [CONNECTOR:39:DP-1] hw state readout: disabled
    [   11.740959] [drm:intel_modeset_readout_hw_state] [CONNECTOR:41:HDMI-A-2] hw state readout: disabled
    [   11.740961] [drm:intel_modeset_readout_hw_state] [CONNECTOR:43:DP-2] hw state readout: disabled
    [   11.740963] [drm:intel_modeset_readout_hw_state] [CONNECTOR:45:DP-3] hw state readout: disabled
    [?]

With the vendor firmware the messages look like below.

    $ grep 'drm:' dmesg_debug_lenovo_bios.txt
    [   13.567790] [drm:i915_dump_device_info] i915 device info: gen=4, pciid=0x2a42 rev=0x07 flags=is_mobile,need_gfx_hws,is_g4x,has_fbc,has_pipe_cxsr,has_hotplug,supports_tv,
    [   13.567817] [drm:intel_detect_pch] No PCH found.
    [   13.567822] [drm:i915_gem_gtt_init] GMADR size = 256M
    [   13.567824] [drm:i915_gem_gtt_init] GTT stolen size = 32M
    [   13.567825] [drm:i915_gem_gtt_init] ppgtt mode: 0
    [   13.569564] [drm:intel_opregion_setup] graphic opregion physical addr: 0xbdb6b0fa
    [   13.569573] [drm:intel_opregion_setup] Public ACPI methods supported
    [   13.569574] [drm:intel_opregion_setup] SWSCI supported
    [   13.575637] [drm:swsci_setup] SWSCI BIOS requested (00010673) SBCB callbacks that are not supported (00080673)
    [   13.575640] [drm:swsci_setup] SWSCI GBDA callbacks 00000cf3, SBCB callbacks 00010673
    [   13.575641] [drm:intel_opregion_setup] ASLE supported
    [   13.575697] [drm:intel_device_info_runtime_init] slice total: 0
    [   13.575698] [drm:intel_device_info_runtime_init] subslice total: 0
    [   13.575700] [drm:intel_device_info_runtime_init] subslice per slice: 0
    [   13.575701] [drm:intel_device_info_runtime_init] EU total: 0
    [   13.575702] [drm:intel_device_info_runtime_init] EU per subslice: 0
    [   13.575703] [drm:intel_device_info_runtime_init] has slice power gating: n
    [   13.575705] [drm:intel_device_info_runtime_init] has subslice power gating: n
    [   13.575706] [drm:intel_device_info_runtime_init] has EU power gating: n
    [   13.575711] [drm:init_vbt_defaults] Set default to SSC at 100000 kHz
    [   13.575714] [drm:validate_vbt] Using VBT from OpRegion: $VBT CANTIGA        d
    [   13.575716] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 1 lvds_use_ssc 1 lvds_ssc_freq 100000 display_clock_mode 0 fdi_rx_polarity_inverted 0
    [   13.575718] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
    [   13.575720] [drm:parse_lfp_panel_data] DRRS supported mode is static
    [   13.575723] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
    [   13.575726] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 0 101600 1440 1488 1520 1792 900 903 909 945 0x8 0xa
    [   13.575728] [drm:parse_lfp_panel_data] VBT initial LVDS value 4230033c
    [   13.575730] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 220 Hz, active high, min brightness 0, level 0
    [   13.575732] [drm:parse_sdvo_panel_data] Found SDVO panel mode in BIOS VBT tables:
    [   13.575735] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
    [   13.575737] [drm:parse_sdvo_device_mapping] No SDVO device info is found in VBT
    [   13.575739] [drm:parse_driver_features] DRRS State Enabled:0
    [   13.575740] [drm:parse_psr] No PSR BDB found.
    [   13.575750] [drm:intel_dsm_pci_probe] no _DSM method for intel device
    [   13.575760] [drm:i915_gem_init_stolen] found 33554432 bytes of stolen memory at be000000
    [   13.575763] [drm:intel_display_power_get] enabling always-on
    [   13.575801] [drm:intel_modeset_init] 2 display pipes available.
    [   13.575813] [drm:intel_modeset_init] pipe A sprite A init failed: -19
    [   13.575819] [drm:intel_modeset_init] pipe B sprite B init failed: -19
    [   13.646058] [drm:intel_lvds_init] using preferred mode from EDID: 
    [   13.646063] [drm:drm_mode_debug_printmodeline] Modeline 27:"1440x900" 60 101600 1440 1488 1520 1792 900 903 909 945 0x48 0xa
    [   13.646068] [drm:intel_lvds_init] detected dual-link lvds configuration
    [   13.646215] [drm:intel_panel_setup_backlight] Connector LVDS-1 backlight initialized, enabled, brightness 481695/2408475
    [   13.646327] [drm:intel_setup_outputs] probing SDVOB
    [   13.646331] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus dpb. force bit now 1
    [   13.655959] [drm:intel_sdvo_read_byte] i2c transfer returned -6
    [   13.655961] [drm:intel_sdvo_init] No SDVO device found on SDVOB
    [   13.655990] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus dpb. force bit now 0
    [   13.655992] [drm:intel_setup_outputs] probing HDMI on SDVOB
    [   13.656064] [drm:intel_dp_init_connector] Adding DP connector on port B
    [   13.656108] [drm:intel_dp_aux_init] registering DPDDC-B bus for card0-DP-1
    [   13.656144] [drm:intel_setup_outputs] probing SDVOC
    [   13.656148] [drm:intel_gmbus_force_bit] enabling bit-banging on i915 gmbus dpb. force bit now 1
    [   13.665729] [drm:intel_sdvo_read_byte] i2c transfer returned -6
    [   13.665731] [drm:intel_sdvo_init] No SDVO device found on SDVOC
    [   13.665758] [drm:intel_gmbus_force_bit] disabling bit-banging on i915 gmbus dpb. force bit now 0
    [   13.665760] [drm:intel_setup_outputs] probing HDMI on SDVOC
    [   13.665808] [drm:intel_dp_init_connector] Adding DP connector on port C
    [   13.665845] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-2
    [   13.665888] [drm:intel_dp_init_connector] Adding DP connector on port D
    [   13.665927] [drm:intel_dp_aux_init] registering DPDDC-D bus for card0-DP-3
    [   13.665964] [drm:intel_tv_init] Integrated TV is not present.
    [   13.665970] [drm:intel_modeset_readout_hw_state] [CRTC:20] hw state readout: disabled
    [   13.665977] [drm:intel_modeset_readout_hw_state] [CRTC:23] hw state readout: enabled
    [   13.665980] [drm:intel_modeset_readout_hw_state] [ENCODER:25:LVDS-25] hw state readout: enabled, pipe B
    [   13.665982] [drm:intel_modeset_readout_hw_state] [ENCODER:32:DAC-32] hw state readout: disabled, pipe A
    [   13.665984] [drm:intel_modeset_readout_hw_state] [ENCODER:33:TMDS-33] hw state readout: disabled, pipe A
    [   13.665986] [drm:intel_modeset_readout_hw_state] [ENCODER:38:TMDS-38] hw state readout: disabled, pipe A
    [   13.665988] [drm:intel_modeset_readout_hw_state] [ENCODER:40:TMDS-40] hw state readout: disabled, pipe A
    [   13.665990] [drm:intel_modeset_readout_hw_state] [ENCODER:42:TMDS-42] hw state readout: disabled, pipe A
    [   13.665992] [drm:intel_modeset_readout_hw_state] [ENCODER:44:TMDS-44] hw state readout: disabled, pipe A
    [   13.665994] [drm:intel_modeset_readout_hw_state] [CONNECTOR:24:LVDS-1] hw state readout: enabled
    [   13.665995] [drm:intel_modeset_readout_hw_state] [CONNECTOR:31:VGA-1] hw state readout: disabled
    [   13.665997] [drm:intel_modeset_readout_hw_state] [CONNECTOR:34:HDMI-A-1] hw state readout: disabled
    [   13.665999] [drm:intel_modeset_readout_hw_state] [CONNECTOR:39:DP-1] hw state readout: disabled
    [   13.666001] [drm:intel_modeset_readout_hw_state] [CONNECTOR:41:HDMI-A-2] hw state readout: disabled
    [   13.666002] [drm:intel_modeset_readout_hw_state] [CONNECTOR:43:DP-2] hw state readout: disabled
    [   13.666004] [drm:intel_modeset_readout_hw_state] [CONNECTOR:45:DP-3] hw state readout: disabled
    [?]

As you can see, the vendor firmware detects a dual-link LVDS
configuration.

    [drm:intel_lvds_init] detected dual-link lvds configuration

With coreboot a single-link LVDS configuration is detected.

    [drm:intel_lvds_init] detected single-link lvds configuration

Francis Rowe wrote to the list, that this is configured during compile
time in coreboot [1][2]. You?d need to rebuild your image. Then you
should have at least graphics when Linux started.

There are two more things two do.

1. Contact the Linux i915 folks and ask them, if the module is able to
detect the configuration itself and does not rely on the firmware or if
there is a way to override that setting from the Linux command line.

2. Improve coreboot so that the LVDS link configuration is detected
during runtime as the vendor firmware (VGA Option ROM/Video BIOS(?))
does.


Thanks,

Paul


[1] http://coreboot.org/pipermail/coreboot/2015-July/080109.html
[2] http://libreboot.org/docs/hcl/gm45_lcd.html
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150713/cdb5139c/attachment.asc>

From kroms at posteo.be  Mon Jul 13 09:43:56 2015
From: kroms at posteo.be (kroms at posteo.be)
Date: Mon, 13 Jul 2015 09:43:56 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <1436767020.3586.53.camel@users.sourceforge.net>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
 <1436693892.11693.13.camel@users.sourceforge.net>
 <8f7e0fb7e2c7275c7e495f21efd55efc@posteo.de>
 <1436767020.3586.53.camel@users.sourceforge.net>
Message-ID: <599a35e62901e3222a034f4a468fac95@posteo.de>

 

Dear Paul,

> As you can see, the vendor firmware detects a dual-link LVDS
> configuration.
> 
> [drm:intel_lvds_init] detected dual-link lvds configuration
> 
> With coreboot a single-link LVDS configuration is detected.
> 
> [drm:intel_lvds_init] detected single-link lvds configuration

Thank you for checking the logs!

> Francis Rowe wrote to the list, that this is configured during compile
> time in coreboot [1][2]. You'd need to rebuild your image. Then you
> should have at least graphics when Linux started.

Yes, I am very happy that they found a workaround. This is the next
thing I am going to do.
Because I re-flashed the Lenovo Bios I have to disassemble the T400
again to reach the flash chip.
I wanted to provide you with the logs first. 

> There are two more things two do.
> 
> 1. Contact the Linux i915 folks and ask them, if the module is able to
> detect the configuration itself and does not rely on the firmware or if
> there is a way to override that setting from the Linux command line.

Who is going to do this? Is this [1 [1]] the right community? I am not
sure, if I am able to explain it right.
If you want me to do this, what do you mean exactly with "the module",
is it "i915"? 

On [2 [2]], is written:
"Linux (kernel) has its own init code (including EDID parsing). The
current suspicion is that coreboot's
own initialization code has buggy EDID parsing in some way, such that
the proper settings for the panel
are not used, leading to the failure."

Please tell me, if I understand it right:
The kernel module should not rely on coreboot concerning the settings
for the display and you want to know, 
if the kernel module is able to get the needed information direct from
the display (EDID)? If this is possible, you want to know,
if this is cofigurable with the Linux command line? Means "Linux command
line" the same as "kernel command line"?

> 2. Improve coreboot so that the LVDS link configuration is detected
> during runtime as the vendor firmware (VGA Option ROM/Video BIOS(?))
> does.

While I am learning a lot of things working on this issue, this is far
above my skills.

Best regards,

Kroms

[1] https://01.org/linuxgraphics/community/kernel
 [1][2] http://libreboot.org/docs/hcl/gm45_lcd.html [2]
 [1]
 

Links:
------
[1] https://01.org/linuxgraphics/community/kernel
[2] http://libreboot.org/docs/hcl/gm45_lcd.html
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150713/6159c06a/attachment-0001.html>

From nochristrequired at gmail.com  Mon Jul 13 12:05:06 2015
From: nochristrequired at gmail.com (Nick)
Date: Mon, 13 Jul 2015 03:05:06 -0700
Subject: [coreboot] Handling NMIs?
Message-ID: <CAJH+5fvHWoZ3vrKOhgRwiqJ+Zw933gowFOpgtqqzzNtLvDPGFA@mail.gmail.com>

Hi guys,

Question - Does Coreboot have a facility for catching and handling NMIs?

Background: I have a problematic PCI bridge that throws a NMI when enabling
it. When this happens, firmware code stops executing. Otherwise, the bridge
works.

Simply disabling NMIs when enabling this particular device might cause a
miss of some other failure and seems like the wrong thing to do.

Any suggestions?

Thanks!

Nick
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150713/a960031f/attachment.html>

From opdecirkel at gmail.com  Mon Jul 13 19:36:54 2015
From: opdecirkel at gmail.com (Pi Van Den Cirkel)
Date: Mon, 13 Jul 2015 13:36:54 -0400
Subject: [coreboot] T400 screen issue / EDID handling
Message-ID: <CAAfzpjg_pXzAxEXy5Y8e=JcGgKEai5peLw-0vO6G+U-J5ndfzQ@mail.gmail.com>

> Dear coreboot community,
>
> tty0_ in #coreboot/#libreboot found a partial fix.
>
> See:
> http://libreboot.org/docs/hcl/gm45_lcd.html

Setting  gfx.lvds_dual_channel = 1 is a workaround so that the kernel
driver (i915) pickups the right value that coreboot had set. But there
are few things to be fixed:

1) No video (fb) during payload(grub) for gm45 (T500) with lcd with
dual channel lvds, up to the point where the kernel installs the i915
driver at which point i get working screen. (For single channel lvds
controllers all works ok - there is video during payload).

2) There are devices with same model that come both variants (i.e
T500) with a single or dual channel lvds . I dont know if there is
(currently) way in coreboot (without using the vbios blob) to detect
this dynamically (in runtime) instead of setting it in the devicetree.

I am willing to work on this problems, but my knowledge is limited in
this area. So, any hints on how to proceed, links to specs/docs, etc
are welcome.


From pgeorgi at google.com  Mon Jul 13 22:05:12 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Mon, 13 Jul 2015 22:05:12 +0200
Subject: [coreboot] Announcing coreboot 4.1
Message-ID: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>

Dear coreboot community,

It has been more than 5 years since we have ?released? coreboot ?4.0?.
That last release marked some very important milestones that we
originally prototyped in the abandoned LinuxBIOS v3 efforts, like the
coreboot filesystem (CBFS), Kconfig support, and (strictly) separate
device trees, build logic and configuration.

Since then there have been as many significant original developments,
such as support for many new architectures (ARM, ARM64, MIPS, RISC-V),
and related architectural changes like access to non-memory mapped SPI
flash, or better insight about the internals of coreboot at runtime
through the cbmem console, timestamp collection, or code coverage
support.

It became clear that a new release is overdue. With our new release
process only slowly getting in shape, I decided to take a random
commit and call it ?4.1?.

The release itself happens at an arbitrary point in time, but will
serve as a starting point for other activities that require some kind
of ?starting point? to build on, described below.

Future releases will happen more frequently, and with more guarantees
about the state of the release, like having a cool down phase where
boards can be tested and so on. I plan to create a release every three
months, so the changes between any two release don?t become too
overwhelming.

With the release of coreboot 4.1, you get an announcement (this
email), a git tag (4.1), and tar archives at
http://www.coreboot.org/releases/, for the coreboot sources and the
redistributable blobs.

Starting with coreboot 4.1, we will maintain a high level changelog
and ?flag days? document. The latter will provide a concise list of
changes which went into coreboot that require chipset or mainboard
code to change to keep it working with the latest upstream coreboot.

For the time being, I will run these efforts, but I?ll happily share
documentation duties with somebody else - it is a great opportunity to
keep track of things, learn about the project and its design and
various internals, while contributing to the project without the need
to code.

Please contact me (for example by email or on IRC) if you?re
interested, and we?ll work out how to collaborate on this.

The process should enable users of coreboot to follow releases if they
want a more static base to build on, while making it easier to follow
along with new developments by providing upgrade documentation.

Since moving away from a rolling (non-)release model is new for
coreboot, things may still be a bit rough around the edges, but I?ll
provide support for any issues that arise from the release process.


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From peter at stuge.se  Tue Jul 14 01:21:10 2015
From: peter at stuge.se (Peter Stuge)
Date: Tue, 14 Jul 2015 01:21:10 +0200
Subject: [coreboot] Announcing coreboot 4.1
In-Reply-To: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>
References: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>
Message-ID: <20150713232110.14944.qmail@stuge.se>

Patrick Georgi wrote:
> I decided to take a random commit and call it ?4.1?.

Well done. Thanks!


//Peter


From marcj303 at gmail.com  Tue Jul 14 06:57:40 2015
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 14 Jul 2015 04:57:40 +0000
Subject: [coreboot] Announcing coreboot 4.1
In-Reply-To: <20150713232110.14944.qmail@stuge.se>
References: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>
 <20150713232110.14944.qmail@stuge.se>
Message-ID: <CALrs_3jeJ8Ou=sWfehxDg-K_VpppJHswEWp1Cp08O0YisCktJA@mail.gmail.com>

Woot! While the milestone is somewhat  arbitrary, the effort of the
community since the release of 4.0 is noteworthy.

Congratulations coreboot!

Marc

On Mon, Jul 13, 2015, 5:22 PM Peter Stuge <peter at stuge.se> wrote:

> Patrick Georgi wrote:
> > I decided to take a random commit and call it ?4.1?.
>
> Well done. Thanks!
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150714/9db784b9/attachment.html>

From paulepanter at users.sourceforge.net  Tue Jul 14 07:55:19 2015
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 14 Jul 2015 07:55:19 +0200
Subject: [coreboot] T400 screen issue / EDID handling
In-Reply-To: <599a35e62901e3222a034f4a468fac95@posteo.de>
References: <f38b9c7573a03886f0211dbf42b3210f@posteo.de>
 <1435958386.5493.61.camel@users.sourceforge.net>
 <44e753be1d353223502ddde14a9b668e@posteo.de>
 <1436082138.13469.47.camel@users.sourceforge.net>
 <dd2e36711d80d9165cf59e7df2cd5e4d@posteo.de>
 <1436693892.11693.13.camel@users.sourceforge.net>
 <8f7e0fb7e2c7275c7e495f21efd55efc@posteo.de>
 <1436767020.3586.53.camel@users.sourceforge.net>
 <599a35e62901e3222a034f4a468fac95@posteo.de>
Message-ID: <1436853319.3019.84.camel@users.sourceforge.net>

Dear Kroms,


Am Montag, den 13.07.2015, 09:43 +0200 schrieb kroms at posteo.be:

[?]

> > There are two more things two do.
> > 
> > 1. Contact the Linux i915 folks and ask them, if the module is able 
> > to detect the configuration itself and does not rely on the 
> > firmware or if there is a way to override that setting from the 
> > Linux command line.
> 
> Who is going to do this? Is this [1] the right community? I am not
> sure, if I am able to explain it right.
> If you want me to do this, what do you mean exactly with "the 
> module", is it "i915"?

Yes i915 and it?d be great if you could do it.

At least the second question should be answered. Looking at
`/sbin/modinfo i915` it shows that there is such an option already.

    parm:           lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel) (int)

So you could add `i915.lvds_channel_mode=2`, I think, to the Linux
command line and see if Linux is able to initialize your system.

> On [2], is written:
> "Linux (kernel) has its own init code (including EDID parsing). The
> current suspicion is that coreboot's own initialization code has 
> buggy EDID parsing in some way, such that the proper settings for the 
> panel are not used, leading to the failure."
> 
> Please tell me, if I understand it right:
> The kernel module should not rely on coreboot concerning the settings
> for the display and you want to know, 
> if the kernel module is able to get the needed information direct 
> from the display (EDID)? If this is possible, you want to know,
> if this is configurable with the Linux command line? Means "Linux 
> command line" the same as "kernel command line"?

Yes. But I am not sure if it?s related to EDID parsing at all. coreboot
just hard codes it.

> > 2. Improve coreboot so that the LVDS link configuration is detected
> > during runtime as the vendor firmware (VGA Option ROM/Video 
> > BIOS(?))
> > does.
> 
> While I am learning a lot of things working on this issue, this is 
> far above my skills.

No problem. Maybe somebody else will do it.


Thanks,

Paul


> [1] https://01.org/linuxgraphics/community/kernel
> [2] http://libreboot.org/docs/hcl/gm45_lcd.html
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 181 bytes
Desc: This is a digitally signed message part
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150714/9c20d3b8/attachment.asc>

From wordpress at blogs.coreboot.org  Mon Jul 13 22:32:02 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Mon, 13 Jul 2015 20:32:02 +0000
Subject: [coreboot] New on blogs.coreboot.org: [GSoC] EC/H8S firmware week #6
Message-ID: <578a73f26466fca56fda2a5530f5d371@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150713/4ebe0e1e/attachment-0001.html>

From wordpress at blogs.coreboot.org  Mon Jul 13 23:37:01 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Mon, 13 Jul 2015 21:37:01 +0000
Subject: [coreboot] =?utf-8?q?New_on_blogs=2Ecoreboot=2Eorg=3A_=5BGSoC=5D_?=
	=?utf-8?q?coreboot_for_ARM64_Qemu_=E2=80=93_Week_=236?=
Message-ID: <5f1a75c8de27268ae0deb7307af8cb26@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150713/c7d5aaca/attachment-0001.html>

From ilios86 at gmail.com  Tue Jul 14 09:48:02 2015
From: ilios86 at gmail.com (YongGon Kim)
Date: Tue, 14 Jul 2015 16:48:02 +0900
Subject: [coreboot] Kernel couldn't find proper MAC address with
 coreboot (gigabyte ma785gmt-ud2h)
In-Reply-To: <CAGFmz-wb6Lp1_gd5FGvefVdrAXOJsZrEF5xbCGSejN-5q9=_MA@mail.gmail.com>
References: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>
 <1436424189.29683.20.camel@users.sourceforge.net>
 <CAGFmz-wb6Lp1_gd5FGvefVdrAXOJsZrEF5xbCGSejN-5q9=_MA@mail.gmail.com>
Message-ID: <CAGFmz-znB2VSJ_-UfuzS9GHEB7gESXYniOtqwAOyNQeG8NTNzQ@mail.gmail.com>

Off topic.

There was a request to find revision in upstream which hinders my ma785gmt
to boot.
I found that after the revision 13e4182119bcfcf09bdd9fa2b0cc5d09cd3550c2
coreboot fails to boot.

I think AMD_RS790 in src/southbridge/amd/rs780/Makefile.inc is typo of
AMD_RS780.
The correction of it makes coreboot to successfully boot.



2015-07-09 19:42 GMT+09:00 YongGon Kim <ilios86 at gmail.com>:

> Thank you for reply!
>
>
> 2015-07-09 15:43 GMT+09:00 Paul Menzel <paulepanter at users.sourceforge.net>
> :
>
>> Dear YongGon,
>>
>>
>> welcome to coreboot and thank you for your message!
>>
>>
>> Am Mittwoch, den 08.07.2015, 20:47 +0900 schrieb YongGon Kim:
>>
>> [?]
>>
>> > I have uploaded detailed information using board_status.sh
>> > Following is link for the information.
>> >
>> http://review.coreboot.org/gitweb?p=board-status.git;a=commit;h=dedf456d25748368da19d556828c7ef95e3f3073
>>
>> Your commit is marked as *dirty*, meaning that you have applied local
>> changes. What are these?
>>
>
> I just changed board_status.sh to properly upload my logs.  i didn't
> change anything else.
>
>
>
>>
>> Additionally, could you please also upload the logs of a run with the
>> current code in master?
>>
>
> I pasted logs of master code. (revision
> 5d866213f42fd22aed80abb5a91d74f6d485ac3f)
>
> As you can see, booting process stopped in the middle.
> I chose the previous snapshot of coreboot since i found some valid results
> in following link.
> http://www.coreboot.org/Supported_Motherboards#gigabyte.2Fma785gmt
>
>
>
>
>
>
>>
>>
>> Thanks,
>>
>> Paul
>>
>>
>> PS: Please just send plain text messages to mailing lists.
>> Additionally, pasting logs in the Google Mail Web interface is not
>> optimal as there is no way to turn off auto-wrapping the lines, which
>> is not wanted for pastes.
>>
>
> I'm sorry. I'm not clearly understanding your request.
> Do you know any alternative interface for sending plain logs?
>
> Anyway, followings are log from master coreboot.
>
> coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 romstage
> starting...
> BSP Family_Model: 00100f42
> *sysinfo range: [000c4100,000c7d31]
> bsp_apicid = 00
> cpu_init_detectedx = 00000000
> CBFS @ 0 size ffc40
> CBFS: Locating 'cpu_microcode_blob.bin'
> CBFS: Found @ offset 2fc0 size 3800
> [microcode] patch id to apply = 0x010000db
> [microcode] updated to patch id = 0x010000db success
> POST: 0x33
> cpuSetAMDMSR  done
> POST: 0x34
> Enter amd_ht_init()
> AMD_CB_EventNotify()
>  event class: 02
>  event: 2005
>  data:  05  00  00  00  01
> AMD_CB_EventNotify()
>  event class: 05
>  event: 2006
>  data:  04  00  00  ff
> Exit amd_ht_init()
> POST: 0x35
> cpuSetAMDPCI 00 done
> Prep FID/VID Node:00
>   F3x80: e600e681
>   F3x84: 80e641e6
>   F3xD4: c8810f24
>   F3xD8: 03001816
>   F3xDC: 00006322
> POST: 0x36
> core0 started:
> start_other_cores()
> init node: 00  cores: 02
> Start other core - nodeid: 00  cores: 02
> POST: 0x37
> started ap apicid: * AP 01started
> * AP 02started
>
> POST: 0x38
> rs780_early_setup()
> fam10_optimization()
> rs780_por_init
> sb700_early_setup()
> sb700_devices_por_init()
> sb700_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is A14
> sb700_devices_por_init(): IDE Device, BDF:0-20-1
> sb700_devices_por_init(): LPC Device, BDF:0-20-3
> sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb700_devices_por_init(): SATA Device, BDF:0-18-0
> sb700_pmio_por_init()
>
> Begin FIDVID MSR 0xc0010071 0x30b40093 0x40035040
> POST: 0x39
> FIDVID on BSP, APIC_id: 00
> BSP fid = 10600
> Wait for AP stage 1: ap_apicid = 1
> readback = 1010601
> common_fid(packed) = 10600
> Wait for AP stage 1: ap_apicid = 2
> readback = 2010601
> common_fid(packed) = 10600
> common_fid = 10600
> FID Change Node:00, F3xD4: c8810f26
> POST: 0x3a
> End FIDVIDMSR 0xc0010071 0x30b40093 0x38005040
> rs780_htinit cpu_ht_freq=0.
> rs780_htinit: HT1 mode
> ...WARM RESET...
>
>
>
>
> coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 romstage
> starting...
> BSP Family_Model: 00100f42
> *sysinfo range: [000c4100,000c7d31]
> bsp_apicid = 00
> cpu_init_detectedx = 00000000
> CBFS @ 0 size ffc40
> CBFS: Locating 'cpu_microcode_blob.bin'
> CBFS: Found @ offset 2fc0 size 3800
> [microcode] patch id to apply = 0x010000db
> [microcode] updated to patch id = 0x010000db success
> POST: 0x33
> cpuSetAMDMSR  done
> POST: 0x34
> Enter amd_ht_init()
> AMD_CB_EventNotify()
>  event class: 02
>  event: 2005
>  data:  05  00  00  00  01
> AMD_CB_EventNotify()
>  event class: 05
>  event: 2006
>  data:  04  00  00  ff
> Exit amd_ht_init()
> POST: 0x35
> cpuSetAMDPCI 00 done
> Prep FID/VID Node:00
>   F3x80: e600e681
>   F3x84: 80e641e6
>   F3xD4: c8810f26
>   F3xD8: 03001816
>   F3xDC: 00006322
> POST: 0x36
> core0 started:
> start_other_cores()
> init node: 00  cores: 02
> Start other core - nodeid: 00  cores: 02
> POST: 0x37
> started ap apicid: * AP 01started
> * AP 02started
>
> POST: 0x38
> rs780_early_setup()
> fam10_optimization()
> rs780_por_init
> sb700_early_setup()
> sb700_devices_por_init()
> sb700_devices_por_init(): SMBus Device, BDF:0-20-0
> SMBus controller enabled, sb revision is A14
> sb700_devices_por_init(): IDE Device, BDF:0-20-1
> sb700_devices_por_init(): LPC Device, BDF:0-20-3
> sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
> sb700_devices_por_init(): SATA Device, BDF:0-18-0
> sb700_pmio_por_init()
>
> Begin FIDVID MSR 0xc0010071 0x30b40093 0x38005040
> POST: 0x39
> POST: 0x3a
> End FIDVIDMSR 0xc0010071 0x30b40093 0x3800240a
> rs780_htinit cpu_ht_freq=0.
> rs780_htinit: HT1 mode
> POST: 0x3b
> fill_mem_ctrl()
> POST: 0x40
> raminit_amdmct()
> raminit_amdmct begin:
>  DIMMPresence: DIMMValid=2
>  DIMMPresence: DIMMPresent=2
>  DIMMPresence: RegDIMMPresent=0
>  DIMMPresence: DimmECCPresent=0
>  DIMMPresence: DimmPARPresent=0
>  DIMMPresence: Dimmx4Present=0
>  DIMMPresence: Dimmx8Present=2
>  DIMMPresence: Dimmx16Present=0
>  DIMMPresence: DimmPlPresent=0
>  DIMMPresence: DimmDRPresent=2
>  DIMMPresence: DimmQRPresent=0
>  DIMMPresence: DATAload[0]=0
>  DIMMPresence: MAload[0]=0
>  DIMMPresence: MAdimms[0]=0
>  DIMMPresence: DATAload[1]=2
>  DIMMPresence: MAload[1]=10
>  DIMMPresence: MAdimms[1]=1
>  DIMMPresence: Status 1000
>  DIMMPresence: ErrStatus 0
>  DIMMPresence: ErrCode 0
>  DIMMPresence: Done
>
> DCTInit_D: mct_DIMMPresence Done
> SPDCalcWidth: Status 1000
> SPDCalcWidth: ErrStatus 0
> SPDCalcWidth: ErrCode 0
> SPDCalcWidth: Done
> DCTInit_D: mct_SPDCalcWidth Done
> SPDGetTCL_D: DIMMCASL 4
> SPDGetTCL_D: DIMMAutoSpeed 4
> SPDGetTCL_D: Status 1000
> SPDGetTCL_D: ErrStatus 0
> SPDGetTCL_D: ErrCode 0
> SPDGetTCL_D: Done
>
> AutoCycTiming: Status 1000
> AutoCycTiming: ErrStatus 0
> AutoCycTiming: ErrCode 2
> AutoCycTiming: Done
>
> DCTInit_D: mct_DIMMPresence Done
> SPDCalcWidth: Status 1000
> SPDCalcWidth: ErrStatus 0
> SPDCalcWidth: ErrCode 0
> SPDCalcWidth: Done
> DCTInit_D: mct_SPDCalcWidth Done
> AutoCycTiming: Status 1000
> AutoCycTiming: ErrStatus 0
> AutoCycTiming: ErrCode 0
> AutoCycTiming: Done
>
> DCTInit_D: AutoCycTiming_D Done
> SPDSetBanks: CSPresent 3
> SPDSetBanks: Status 1000
> SPDSetBanks: ErrStatus 0
> SPDSetBanks: ErrCode 0
> SPDSetBanks: Done
>
> AfterStitch pDCTstat->NodeSysBase = 0
> mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
> StitchMemory: Status 1000
> StitchMemory: ErrStatus 0
> StitchMemory: ErrCode 0
> StitchMemory: Done
>
> InterleaveBanks_D: Status 1000
> InterleaveBanks_D: ErrStatus 0
> InterleaveBanks_D: ErrCode 0
> InterleaveBanks_D: Done
>
> AutoConfig_D: DramControl: 2a06
> AutoConfig_D: DramTimingLo: 90092
> AutoConfig_D: DramConfigMisc: 0
> AutoConfig_D: DramConfigMisc2: 0
> AutoConfig_D: DramConfigLo: 10000
> AutoConfig_D: DramConfigHi: f48000b
> AutoConfig: Status 1000
> AutoConfig: ErrStatus 0
> AutoConfig: ErrCode 0
> AutoConfig: Done
>
> DCTInit_D: AutoConfig_D Done
> DCTInit_D: PlatformSpec_D Done
> DCTInit_D: StartupDCT_D
> mctAutoInitMCT_D: SyncDCTsReady_D
> mctAutoInitMCT_D: HTMemMapInit_D
>  Node: 00  base: 00  limit: 7fffff  BottomIO: a00000
>  Node: 00  base: 03  limit: 7fffff
>  Node: 01  base: 00  limit: 00
>  Node: 02  base: 00  limit: 00
>  Node: 03  base: 00  limit: 00
>  Node: 04  base: 00  limit: 00
>  Node: 05  base: 00  limit: 00
>  Node: 06  base: 00  limit: 00
>  Node: 07  base: 00  limit: 00
> mctAutoInitMCT_D: CPUMemTyping_D
>  CPUMemTyping: Cache32bTOP:800000
>  CPUMemTyping: Bottom32bIO:800000
>  CPUMemTyping: Bottom40bIO:0
> mctAutoInitMCT_D: DQSTiming_D
> TrainRcvrEn: Status 1000
> TrainRcvrEn: ErrStatus 0
> TrainRcvrEn: ErrCode 0
> TrainRcvrEn: Done
>
> TrainDQSRdWrPos: Status 1000
> TrainDQSRdWrPos: TrainErrors 0
> TrainDQSRdWrPos: ErrStatus 0
> TrainDQSRdWrPos: ErrCode 0
> TrainDQSRdWrPos: Done
>
> TrainDQSRdWrPos: Status 1000
> TrainDQSRdWrPos: TrainErrors 0
> TrainDQSRdWrPos: ErrStatus 0
> TrainDQSRdWrPos: ErrCode 0
> TrainDQSRdWrPos: Done
>
> TrainDQSRdWrPos: Status 1000
> TrainDQSRdWrPos: TrainErrors 0
> TrainDQSRdWrPos: ErrStatus 0
> TrainDQSRdWrPos: ErrCode 0
> TrainDQSRdWrPos: Done
>
> TrainDQSRdWrPos: Status 1000
> TrainDQSRdWrPos: TrainErrors 0
> TrainDQSRdWrPos: ErrStatus 0
> TrainDQSRdWrPos: ErrCode 0
> TrainDQSRdWrPos: Done
>
> mctAutoInitMCT_D: UMAMemTyping_D
> mctAutoInitMCT_D: :OtherTiming
> InterleaveNodes_D: Status 1000
> InterleaveNodes_D: ErrStatus 0
> InterleaveNodes_D: ErrCode 0
> InterleaveNodes_D: Done
>
> InterleaveChannels_D: Node 0
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 1
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 2
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 3
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 4
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 5
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 6
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Node 7
> InterleaveChannels_D: Status 1000
> InterleaveChannels_D: ErrStatus 0
> InterleaveChannels_D: ErrCode 0
> InterleaveChannels_D: Done
>
> mctAutoInitMCT_D: ECCInit_D
> ECCInit: Node 00
> ECCInit: Status 1000
> ECCInit: ErrStatus 0
> ECCInit: ErrCode 0
> ECCInit: Done
> mctAutoInitMCT_D Done: Global Status: 0
> raminit_amdmct end:
> CBMEM:
> IMD: root @ 6ffff000 254 entries.
> IMD: root @ 6fffec00 62 entries.
> POST: 0x41
> amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
> POST: 0x42
> Prepare CAR migration and stack regions... Fill [003fbc00-003fffff] ...
> Done
> Copying data from cache to RAM...  Copy [000c4000-000c7d3f] to [003fc2c0 -
> 003fffff] ... Done
> Switching to use RAM as stack... Top about 003fc2ac ... Done
> Disabling cache as ram now
> Prepare ramstage memory region...  Fill [00000000-003fbbff] ... Done
> CBFS provider active.
> CBFS @ 0 size ffc40
> CBFS: Locating 'fallback/ramstage'
> CBFS: Found @ offset 1bf40 size 19959
> 'fallback/ramstage' located at offset: 1bf78 size: 19959
>
>
> coreboot-4.0-10265-g5d86621-dirty Thu Jul  9 06:47:41 UTC 2015 ramstage
> starting...
> POST: 0x39
> Moving GDT to 6fffe700...ok
> POST: 0x80
> POST: 0x70
> BS: BS_PRE_DEVICE times (us): entry 8 run 1065 exit 0
> POST: 0x71
> BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1060 exit 0
> POST: 0x72
> Enumerating buses...
> Show all devs... Before device enumeration.
> Root Device: enabled 1
> CPU_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> DOMAIN: 0000: enabled 1
> PCI: 00:18.0: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:02.0: enabled 1
> PCI: 00:03.0: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:09.0: enabled 1
> PCI: 00:0a.0: enabled 1
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 1
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 1
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> I2C: 00:52: enabled 1
> I2C: 00:53: enabled 1
> PCI: 00:14.1: enabled 1
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 002e.0: enabled 0
> PNP: 002e.1: enabled 1
> PNP: 002e.2: enabled 0
> PNP: 002e.3: enabled 0
> PNP: 002e.4: enabled 0
> PNP: 002e.5: enabled 1
> PNP: 002e.6: enabled 1
> PNP: 002e.7: enabled 0
> PNP: 002e.8: enabled 0
> PNP: 002e.9: enabled 0
> PNP: 002e.a: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> Compare with tree...
> Root Device: enabled 1
>  CPU_CLUSTER: 0: enabled 1
>   APIC: 00: enabled 1
>  DOMAIN: 0000: enabled 1
>   PCI: 00:18.0: enabled 1
>    PCI: 00:00.0: enabled 1
>    PCI: 00:01.0: enabled 1
>    PCI: 00:02.0: enabled 1
>    PCI: 00:03.0: enabled 1
>    PCI: 00:04.0: enabled 1
>    PCI: 00:05.0: enabled 0
>    PCI: 00:06.0: enabled 0
>    PCI: 00:07.0: enabled 0
>    PCI: 00:08.0: enabled 0
>    PCI: 00:09.0: enabled 1
>    PCI: 00:0a.0: enabled 1
>    PCI: 00:11.0: enabled 1
>    PCI: 00:12.0: enabled 1
>    PCI: 00:12.1: enabled 1
>    PCI: 00:12.2: enabled 1
>    PCI: 00:13.0: enabled 1
>    PCI: 00:13.1: enabled 1
>    PCI: 00:13.2: enabled 1
>    PCI: 00:14.0: enabled 1
>     I2C: 00:50: enabled 1
>     I2C: 00:51: enabled 1
>     I2C: 00:52: enabled 1
>     I2C: 00:53: enabled 1
>    PCI: 00:14.1: enabled 1
>    PCI: 00:14.2: enabled 1
>    PCI: 00:14.3: enabled 1
>     PNP: 002e.0: enabled 0
>     PNP: 002e.1: enabled 1
>     PNP: 002e.2: enabled 0
>     PNP: 002e.3: enabled 0
>     PNP: 002e.4: enabled 0
>     PNP: 002e.5: enabled 1
>     PNP: 002e.6: enabled 1
>     PNP: 002e.7: enabled 0
>     PNP: 002e.8: enabled 0
>     PNP: 002e.9: enabled 0
>     PNP: 002e.a: enabled 0
>    PCI: 00:14.4: enabled 1
>    PCI: 00:14.5: enabled 1
>   PCI: 00:18.1: enabled 1
>   PCI: 00:18.2: enabled 1
>   PCI: 00:18.3: enabled 1
>   PCI: 00:18.4: enabled 1
> Mainboard MA785GMT-UD2H Enable. dev=0x0013a000
> Init adt7461 end , status 0x02 fd
> Dev3 is not present. GFX Configuration is One x16 slot
> Root Device scanning...
> root_dev_scan_bus for Root Device
> setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
> setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
> setup_uma_memory: uma size 0x10000000, memory start 0x70000000
> CPU_CLUSTER: 0 enabled
> DOMAIN: 0000 enabled
> CPU_CLUSTER: 0 scanning...
>   PCI: 00:18.3 siblings=2
> CPU: APIC: 00 enabled
> CPU: APIC: 01 enabled
> CPU: APIC: 02 enabled
> DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> POST: 0x24
> PCI: 00:18.0 [1022/1200] bus ops
> PCI: 00:18.0 [1022/1200] enabled
> PCI: 00:18.1 [1022/1201] enabled
> PCI: 00:18.2 [1022/1202] enabled
> PCI: 00:18.3 [1022/1203] ops
> PCI: 00:18.3 [1022/1203] enabled
> PCI: 00:18.4 [1022/1204] enabled
> POST: 0x25
> PCI: 00:18.0 scanning...
> PCI: 00:00.0 [1022/9601] enabled
> Capability: type 0x08 @ 0xc4
> flags: 0x0181
> PCI: pci_scan_bus for bus 00
> PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
> PCI: pci_scan_bus upper limit too big. Using 0xff.
> POST: 0x24
> PCI: 00:00.0 [1022/9601] enabled
> Capability: type 0x08 @ 0x44
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0x44
> Capability: type 0x08 @ 0x44
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0x44
> Capability: type 0x0d @ 0xb0
> PCI: 00:01.0 [1022/9602] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:02.0 subordinate bus PCI Express
> PCI: 00:02.0 [1022/9603] enabled
> PCI: Static device PCI: 00:03.0 not found, disabling it.
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:04.0 subordinate bus PCI Express
> PCI: 00:04.0 [1022/9604] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:05.0 subordinate bus PCI Express
> PCI: 00:05.0 [1022/9605] disabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:06.0 subordinate bus PCI Express
> PCI: 00:06.0 [1022/9606] disabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:07.0 subordinate bus PCI Express
> PCI: 00:07.0 [1022/9607] disabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:08.0 subordinate bus PCI Express
> PCI: 00:08.0 [1022/960a] disabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:09.0 subordinate bus PCI Express
> PCI: 00:09.0 [1022/9608] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:0a.0 subordinate bus PCI Express
> PCI: 00:0a.0 [1022/9609] enabled
> sb7xx_51xx_enable()
> PCI: 00:11.0 [1002/4390] ops
> PCI: 00:11.0 [1002/4390] enabled
> sb7xx_51xx_enable()
> PCI: 00:12.0 [1002/4397] ops
> PCI: 00:12.0 [1002/4397] enabled
> sb7xx_51xx_enable()
> PCI: 00:12.1 [1002/4398] ops
> PCI: 00:12.1 [1002/4398] enabled
> sb7xx_51xx_enable()
> PCI: 00:12.2 [1002/4396] ops
> PCI: 00:12.2 [1002/4396] enabled
> sb7xx_51xx_enable()
> PCI: 00:13.0 [1002/4397] ops
> PCI: 00:13.0 [1002/4397] enabled
> sb7xx_51xx_enable()
> PCI: 00:13.1 [1002/4398] ops
> PCI: 00:13.1 [1002/4398] enabled
> sb7xx_51xx_enable()
> PCI: 00:13.2 [1002/4396] ops
> PCI: 00:13.2 [1002/4396] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.0 [1002/4385] bus ops
> PCI: 00:14.0 [1002/4385] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.1 [1002/439c] ops
> PCI: 00:14.1 [1002/439c] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.2 [1002/4383] ops
> PCI: 00:14.2 [1002/4383] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.3 [1002/439d] bus ops
> PCI: 00:14.3 [1002/439d] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.4 [1002/4384] bus ops
> PCI: 00:14.4 [1002/4384] enabled
> sb7xx_51xx_enable()
> PCI: 00:14.5 [1002/4399] ops
> PCI: 00:14.5 [1002/4399] enabled
> PCI: 00:18.0 [1022/1200] bus ops
> PCI: 00:18.0 [1022/1200] enabled
> PCI: 00:18.1 [1022/1201] enabled
> PCI: 00:18.2 [1022/1202] enabled
> PCI: 00:18.3 [1022/1203] ops
> PCI: 00:18.3 [1022/1203] enabled
> PCI: 00:18.4 [1022/1204] enabled
> POST: 0x25
> PCI: 00:01.0 scanning...
> do_pci_scan_bridge for PCI: 00:01.0
> PCI: pci_scan_bus for bus 01
> POST: 0x24
>
> (booting process stops here)
> ================
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150714/12115a86/attachment-0001.html>

From pgeorgi at google.com  Tue Jul 14 10:13:36 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Tue, 14 Jul 2015 10:13:36 +0200
Subject: [coreboot] Kernel couldn't find proper MAC address with
 coreboot (gigabyte ma785gmt-ud2h)
In-Reply-To: <CAGFmz-znB2VSJ_-UfuzS9GHEB7gESXYniOtqwAOyNQeG8NTNzQ@mail.gmail.com>
References: <CAGFmz-xpx9V7y=HaGFhAKGV3P5F0p6fbRMbH2ZM5i1pEKv9BtA@mail.gmail.com>
 <1436424189.29683.20.camel@users.sourceforge.net>
 <CAGFmz-wb6Lp1_gd5FGvefVdrAXOJsZrEF5xbCGSejN-5q9=_MA@mail.gmail.com>
 <CAGFmz-znB2VSJ_-UfuzS9GHEB7gESXYniOtqwAOyNQeG8NTNzQ@mail.gmail.com>
Message-ID: <CAE-gjdXXqkHdExvAQmvtDBMc5spxJA5a+Q1p3Ad0nuHxyJdW9w@mail.gmail.com>

2015-07-14 9:48 GMT+02:00 YongGon Kim <ilios86 at gmail.com>:
> I think AMD_RS790 in src/southbridge/amd/rs780/Makefile.inc is typo of
> AMD_RS780.
> The correction of it makes coreboot to successfully boot.
Thanks, http://review.coreboot.org/#/c/10914/


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From pgeorgi at google.com  Tue Jul 14 15:16:22 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Tue, 14 Jul 2015 15:16:22 +0200
Subject: [coreboot] build coreboot for Braswell soc
In-Reply-To: <CAJYP-=BBE_1T5wnzH3mjM05cE2Y3Q-P19yBbuwR2Jh7rqYFp9Q@mail.gmail.com>
References: <CAJYP-=DjEoLxduVS6WFxVOaL9uP1ZHPePqB060oNU7gx8yHrHw@mail.gmail.com>
 <CAE-gjdXp=Vwj58ue9XasOO6dsdeghZupbfSVP63nq1OTE20=bg@mail.gmail.com>
 <CAJYP-=BBE_1T5wnzH3mjM05cE2Y3Q-P19yBbuwR2Jh7rqYFp9Q@mail.gmail.com>
Message-ID: <CAE-gjdUN+SSSmSuMwunLLOeGJ-y7urH5W5S1A-1vstyZbJAd7w@mail.gmail.com>

2015-07-08 16:57 GMT+02:00 philby john <philbyjohn at gmail.com>:
> In my understanding, denoting /*/*/ does not actually point to those
> directories,
> unless you substitute it with the actual path in src/Kconfig. For example:
> src/soc/intel/baytrail/Kconfig
> src/soc/intel/braswell/Kconfig etc...
We extended Kconfig to interpret these wildcards.
Since they're used for mainboards, northbridges, southbridges, SoCs,
and superios, I'd expect coreboot to be rather useless if these
weren't working.


Patrick


From vbendeb at chromium.org  Tue Jul 14 17:08:43 2015
From: vbendeb at chromium.org (Vadim Bendebury)
Date: Tue, 14 Jul 2015 08:08:43 -0700
Subject: [coreboot] Announcing coreboot 4.1
In-Reply-To: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>
References: <CAE-gjdXxQMa0BHNhaBq4penJRXUebPPcFOgFYY+W0WGgd1_Aog@mail.gmail.com>
Message-ID: <CAC3GErFRE+ynQPEQ0w-Aq4_ts6yVi8DHL2-S4UAm1ub7+2XDag@mail.gmail.com>

.1 version increase after five years and such dramatic changes in the
product? You should have bumped it by at least 1.0 :)

--vb


On Mon, Jul 13, 2015 at 1:05 PM, Patrick Georgi <pgeorgi at google.com> wrote:
> Dear coreboot community,
>
> It has been more than 5 years since we have ?released? coreboot ?4.0?.
> That last release marked some very important milestones that we
> originally prototyped in the abandoned LinuxBIOS v3 efforts, like the
> coreboot filesystem (CBFS), Kconfig support, and (strictly) separate
> device trees, build logic and configuration.
>
> Since then there have been as many significant original developments,
> such as support for many new architectures (ARM, ARM64, MIPS, RISC-V),
> and related architectural changes like access to non-memory mapped SPI
> flash, or better insight about the internals of coreboot at runtime
> through the cbmem console, timestamp collection, or code coverage
> support.
>
> It became clear that a new release is overdue. With our new release
> process only slowly getting in shape, I decided to take a random
> commit and call it ?4.1?.
>
> The release itself happens at an arbitrary point in time, but will
> serve as a starting point for other activities that require some kind
> of ?starting point? to build on, described below.
>
> Future releases will happen more frequently, and with more guarantees
> about the state of the release, like having a cool down phase where
> boards can be tested and so on. I plan to create a release every three
> months, so the changes between any two release don?t become too
> overwhelming.
>
> With the release of coreboot 4.1, you get an announcement (this
> email), a git tag (4.1), and tar archives at
> http://www.coreboot.org/releases/, for the coreboot sources and the
> redistributable blobs.
>
> Starting with coreboot 4.1, we will maintain a high level changelog
> and ?flag days? document. The latter will provide a concise list of
> changes which went into coreboot that require chipset or mainboard
> code to change to keep it working with the latest upstream coreboot.
>
> For the time being, I will run these efforts, but I?ll happily share
> documentation duties with somebody else - it is a great opportunity to
> keep track of things, learn about the project and its design and
> various internals, while contributing to the project without the need
> to code.
>
> Please contact me (for example by email or on IRC) if you?re
> interested, and we?ll work out how to collaborate on this.
>
> The process should enable users of coreboot to follow releases if they
> want a more static base to build on, while making it easier to follow
> along with new developments by providing upgrade documentation.
>
> Since moving away from a rolling (non-)release model is new for
> coreboot, things may still be a bit rough around the edges, but I?ll
> provide support for any issues that arise from the release process.
>
>
> Patrick
> --
> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
> Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From jwerner at chromium.org  Tue Jul 14 20:42:28 2015
From: jwerner at chromium.org (Julius Werner)
Date: Tue, 14 Jul 2015 11:42:28 -0700
Subject: [coreboot]
	=?utf-8?q?New_on_blogs=2Ecoreboot=2Eorg=3A_=5BGSoC=5D_?=
	=?utf-8?q?coreboot_for_ARM64_Qemu_=E2=80=93_Week_=236?=
In-Reply-To: <5f1a75c8de27268ae0deb7307af8cb26@blogs.coreboot.org>
References: <5f1a75c8de27268ae0deb7307af8cb26@blogs.coreboot.org>
Message-ID: <CAODwPW9XypqpYvNBu67SWESSgqqeLBEbjr0uq-96++EAEkkheg@mail.gmail.com>

Hi Naman,

Just some pointers to make sure we don't try to pull in different directions:

> Next up, was another hitch. During the build, ?mmu_enable()? and
> ?arch_secondary_cpu_init()? function calls are happening for all stages but
> the definitions for these functions are getting compiled only for ramstage.
> So this gave recurrent errors since the compiler couldn?t find these
> definitions. While attempting to sort this, I stumbled across something on
> the chromium tree. There was a patch which dealt with some of the issues,
> similar to mine. I had to cherry pick and apply this change.

That patch from the Exynos7 series was just a hack to get stuff
working, it's not really solving anything. The whole stage_entry()
code is still really screwed up, it shouldn't run all of that in every
stage. We want to switch to a model where the MMU is only enabled once
in the bootblock and then just stays on, being able to add new
mappings later if necessary (similar to how ARMv7 works). A small
start of that has happened with http://review.coreboot.org/10304 but
there are still more issues to solve, unfortunately.

> Another aspect in question is the bootblock
> initialisation. The src/arch/arm64/armv8/bootblock_simple.c calls for an
> appropriate bootblock_cpu_init(). This is another thing I will be working on
> in the coming days.

armv8/bootblock_simple.c and armv8/bootblock.S are currently
completely broken (i.e. they may happen to work for you, but not as
intended). They should instead look very similar to the armv7 code...
a small assembly stub to initialize stack and caches, and the main
bootblock function with all the advances that we've made to the ARMv7
model since they split (e.g. bootblock_cpu_init() should be renamed to
bootblock_soc_init(), and it should be a normally linked function with
a weak default implementation instead of that weird #including a whole
.c file with CONFIG_BOOTBLOCK_CPU_INIT).

Sorry that everything's so broken and not moving faster.


From 1395158558 at qq.com  Thu Jul 16 11:38:04 2015
From: 1395158558 at qq.com (=?ISO-8859-1?B?RE0zNjU=?=)
Date: Thu, 16 Jul 2015 17:38:04 +0800
Subject: [coreboot] coreboot+intel uefi payload can not find emmc device
Message-ID: <tencent_24E3DBBE66F64CA335C3E553@qq.com>

My board:e3825+emmc.
I want to use coreboot+intel uefi payload to install ubuntu to emmc device.
If I use intel bios "MinnowBoard MAX 0.81 64-Bit:  Debug" from "https://firmware.intel.com/projects/minnowboard-max",
the intel bios can find emmc device,and I can install ubuntu to emmc device.
But if I use my bios,it can not find emmc device.
I run shell "pci",it shows:
"00   00   17    00 ==> Base System Peripherals - UNDEFINED 
Vendor 8086 Device 0F50 Prog Interface 1 " .
And if I use intel bios,it shows:
"00   00   17    00 ==> Base System Peripherals - SD Host controller
Vendor 8086 Device 0F50 Prog Interface 1 " .


The whole log is :
POST: 0x4a
 romstage_main_continue status: 0  hob_list_ptr: 7ae20000
 FSP Status: 0x0
 PM1_STS = 0x0 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808
 romstage_main_continue: prev_sleep_state = S0
 Baytrail Chip Variant: Bay Trail-I (ISG/embedded)
 MRC v0.100
 1 channels of DDR3 @ 1066MHz
 POST: 0x4b
 POST: 0x4c
 POST: 0x4d
 CBMEM:
 IMD: root @ 7adff000 254 entries.
 IMD: root @ 7adfec00 62 entries.
 POST: 0x4e
 POST: 0x4f
 CBFS provider active.
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'fallback/ramstage'
 CBFS: Found @ offset 1a340 size d88b
 'fallback/ramstage' located at offset: 51a378 size: d88b
 
 
 coreboot-4.0-10090-g3e5bc1f-dirty Thu Jun 25 22:01:57 UTC 2015 ramstage starting...
 POST: 0x39
 Moving GDT to 7adfe9c0...ok
 POST: 0x80
 Normal boot.
 POST: 0x70
 BS: BS_PRE_DEVICE times (us): entry 0 run 1166 exit 0
 POST: 0x71
 CPUID: 00030679
 Cores: 2
 Revision ID: 11
 Stepping: ??
 msr(17) = 0000000c90040a35
 msr(ce) = 0000040000000a00
 Initializing sideband SCC registers.
 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 16248 exit 0
 POST: 0x72
 Enumerating buses...
 Show all devs... Before device enumeration.
 Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
 APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
 PCI: 00:00.0: enabled 1
 PCI: 00:02.0: enabled 1
 PCI: 00:03.0: enabled 0
 PCI: 00:10.0: enabled 1
 PCI: 00:11.0: enabled 1
 PCI: 00:12.0: enabled 1
 PCI: 00:13.0: enabled 1
 PCI: 00:14.0: enabled 1
 PCI: 00:15.0: enabled 1
 PCI: 00:17.0: enabled 1
 PCI: 00:18.0: enabled 1
 PCI: 00:18.1: enabled 1
 PCI: 00:18.2: enabled 1
 PCI: 00:18.3: enabled 1
 PCI: 00:18.4: enabled 1
 PCI: 00:18.5: enabled 1
 PCI: 00:18.6: enabled 1
 PCI: 00:18.7: enabled 1
 PCI: 00:1a.0: enabled 1
 PCI: 00:1b.0: enabled 0
 PCI: 00:1c.0: enabled 1
 PCI: 00:1c.1: enabled 1
 PCI: 00:1c.2: enabled 1
 PCI: 00:1c.3: enabled 1
 PCI: 00:1d.0: enabled 1
 PCI: 00:1e.0: enabled 1
 PCI: 00:1e.1: enabled 1
 PCI: 00:1e.2: enabled 1
 PCI: 00:1e.3: enabled 1
 PCI: 00:1e.4: enabled 1
 PCI: 00:1e.5: enabled 1
 PCI: 00:1f.0: enabled 1
 PCI: 00:1f.3: enabled 1
 Compare with tree...
 Root Device: enabled 1
  CPU_CLUSTER: 0: enabled 1
   APIC: 00: enabled 1
  DOMAIN: 0000: enabled 1
   PCI: 00:00.0: enabled 1
   PCI: 00:02.0: enabled 1
   PCI: 00:03.0: enabled 0
   PCI: 00:10.0: enabled 1
   PCI: 00:11.0: enabled 1
   PCI: 00:12.0: enabled 1
   PCI: 00:13.0: enabled 1
   PCI: 00:14.0: enabled 1
   PCI: 00:15.0: enabled 1
   PCI: 00:17.0: enabled 1
   PCI: 00:18.0: enabled 1
   PCI: 00:18.1: enabled 1
   PCI: 00:18.2: enabled 1
   PCI: 00:18.3: enabled 1
   PCI: 00:18.4: enabled 1
   PCI: 00:18.5: enabled 1
   PCI: 00:18.6: enabled 1
   PCI: 00:18.7: enabled 1
   PCI: 00:1a.0: enabled 1
   PCI: 00:1b.0: enabled 0
   PCI: 00:1c.0: enabled 1
   PCI: 00:1c.1: enabled 1
   PCI: 00:1c.2: enabled 1
   PCI: 00:1c.3: enabled 1
   PCI: 00:1d.0: enabled 1
   PCI: 00:1e.0: enabled 1
   PCI: 00:1e.1: enabled 1
   PCI: 00:1e.2: enabled 1
   PCI: 00:1e.3: enabled 1
   PCI: 00:1e.4: enabled 1
   PCI: 00:1e.5: enabled 1
   PCI: 00:1f.0: enabled 1
   PCI: 00:1f.3: enabled 1
 Root Device scanning...
 root_dev_scan_bus for Root Device
 enable_dev(Intel BayTrail SoC, 7)
 CPU_CLUSTER: 0 enabled
 enable_dev(Intel BayTrail SoC, 6)
 DOMAIN: 0000 enabled
 DOMAIN: 0000 scanning...
 PCI: pci_scan_bus for bus 00
 POST: 0x24
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:00.0 [8086/0f00] ops
 fsp_header_ptr: fffc0094
 FSP Header Version: 1
 FSP Revision: 3.3
 PCI: 00:00.0 [8086/0f00] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:02.0 [8086/0f31] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:03.0: Disabling device: 03.0
 Capability: type 0xff @ 0xfc
 Power management CAP offset 0x80.
 enable_dev(Intel BayTrail SoC, 2)
 PCI: Static device PCI: 00:10.0 not found, disabling it.
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:11.0 [8086/0f15] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:12.0 [8086/0f16] ops
 PCI: 00:12.0 [8086/0f16] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:13.0 [8086/0f23] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: Static device PCI: 00:14.0 not found, disabling it.
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:15.0 [8086/0f28] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:17.0 [8086/0f50] ops
 PCI: 00:17.0 [8086/0f50] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.0 [8086/0000] ops
 PCI: 00:18.0 [8086/0f40] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.1 [8086/0000] ops
 PCI: 00:18.1 [8086/0f41] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.2 [8086/0000] ops
 PCI: 00:18.2 [8086/0f42] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.3 [8086/0000] ops
 PCI: 00:18.3 [8086/0f43] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.4 [8086/0000] ops
 PCI: 00:18.4 [8086/0f44] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.5 [8086/0000] ops
 PCI: 00:18.5 [8086/0f45] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.6 [8086/0000] ops
 PCI: 00:18.6 [8086/0f46] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:18.7 [8086/0000] ops
 PCI: 00:18.7 [8086/0f47] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1a.0 [8086/0f18] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1b.0: Disabling device: 1b.0
 enable_dev(Intel BayTrail SoC, 2)
 Capability: type 0x10 @ 0x40
 Capability: type 0x05 @ 0x80
 Capability: type 0x0d @ 0x90
 Capability: type 0x01 @ 0xa0
 Capability: type 0x10 @ 0x40
 PCI: 00:1c.0 subordinate bus PCI Express
 PCI: 00:1c.0 [8086/0f48] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: Static device PCI: 00:1c.1 not found, disabling it.
 enable_dev(Intel BayTrail SoC, 2)
 Capability: type 0x10 @ 0x40
 Capability: type 0x05 @ 0x80
 Capability: type 0x0d @ 0x90
 Capability: type 0x01 @ 0xa0
 Capability: type 0x10 @ 0x40
 PCI: 00:1c.2 subordinate bus PCI Express
 PCI: 00:1c.2 [8086/0f4c] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: Static device PCI: 00:1c.3 not found, disabling it.
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1d.0 [8086/0f34] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.0 [8086/0000] ops
 PCI: 00:1e.0 [8086/0f06] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.1 [8086/0000] ops
 PCI: 00:1e.1 [8086/0f08] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.2 [8086/0000] ops
 PCI: 00:1e.2 [8086/0f09] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.3 [8086/0000] ops
 PCI: 00:1e.3 [8086/0f0a] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.4 [8086/0000] ops
 PCI: 00:1e.4 [8086/0f0c] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1e.5 [8086/0000] ops
 PCI: 00:1e.5 [8086/0f0e] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1f.0 [8086/0f1c] bus ops
 PCI: 00:1f.0 [8086/0f1c] enabled
 enable_dev(Intel BayTrail SoC, 2)
 PCI: 00:1f.3 [8086/0f12] enabled
 POST: 0x25
 PCI: 00:1c.0 scanning...
 do_pci_scan_bridge for PCI: 00:1c.0
 PCI: pci_scan_bus for bus 01
 POST: 0x24
 POST: 0x25
 POST: 0x55
 PCI: 00:1c.2 scanning...
 do_pci_scan_bridge for PCI: 00:1c.2
 PCI: pci_scan_bus for bus 02
 POST: 0x24
 PCI: 02:00.0 [8086/1531] enabled
 POST: 0x25
 POST: 0x55
 Capability: type 0x01 @ 0x40
 Capability: type 0x05 @ 0x50
 Capability: type 0x11 @ 0x70
 Capability: type 0x10 @ 0xa0
 Capability: type 0x10 @ 0x40
 PCI: 00:1f.0 scanning...
 scan_lpc_bus for PCI: 00:1f.0
 scan_lpc_bus for PCI: 00:1f.0 done
 POST: 0x55
 root_dev_scan_bus for Root Device done
 done
 BS: BS_DEV_ENUMERATE times (us): entry 0 run 613295 exit 0
 POST: 0x73
 found VGA at PCI: 00:02.0
 Setting up VGA for PCI: 00:02.0
 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
 Allocating resources...
 Reading resources...
 Root Device read_resources bus 0 link: 0
 CPU_CLUSTER: 0 read_resources bus 0 link: 0
 APIC: 00 missing read_resources
 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
 DOMAIN: 0000 read_resources bus 0 link: 0
 UMA, GTT & SMM memory location: 0x7b000000
 UMA, GTT & SMM memory size: 80M
 FSP memory location: 0x7ae00000
 FSP memory size: 2M
 Available memory below 4GB: 0x7ae00000 (1966M)
 Available memory above 4GB: 0M
 Adding PCIe config bar base=0xe0000000 size=0x10000000
 PCI: 00:1c.0 read_resources bus 1 link: 0
 PCI: 00:1c.0 read_resources bus 1 link: 0 done
 PCI: 00:1c.2 read_resources bus 2 link: 0
 PCI: 00:1c.2 read_resources bus 2 link: 0 done
 DOMAIN: 0000 read_resources bus 0 link: 0 done
 Root Device read_resources bus 0 link: 0 done
 Done reading resources.
 Show resources in subtree (Root Device)...After reading.
  Root Device child on link 0 CPU_CLUSTER: 0
   CPU_CLUSTER: 0 child on link 0 APIC: 00
    APIC: 00
   DOMAIN: 0000 child on link 0 PCI: 00:00.0
   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
    PCI: 00:00.0
    PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
    PCI: 00:00.0 resource base 100000 size 7ad00000 align 0 gran 0 limit 0 flags e0004200 index 1
    PCI: 00:00.0 resource base 7ae00000 size 5200000 align 0 gran 0 limit 0 flags f0000200 index 2
    PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 3
    PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
    PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 5
    PCI: 00:02.0
    PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffff flags 200 index 10
    PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18
    PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20
    PCI: 00:03.0
    PCI: 00:10.0
    PCI: 00:11.0
    PCI: 00:11.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:11.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:12.0
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:13.0
    PCI: 00:13.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:13.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:13.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:13.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:13.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
    PCI: 00:13.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
    PCI: 00:14.0
    PCI: 00:15.0
    PCI: 00:15.0 resource base 0 size 200000 align 21 gran 21 limit ffffffff flags 200 index 10
    PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:17.0
    PCI: 00:17.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:17.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.0
    PCI: 00:18.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 00:18.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.1
    PCI: 00:18.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.2
    PCI: 00:18.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.3
    PCI: 00:18.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.4
    PCI: 00:18.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.5
    PCI: 00:18.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.6
    PCI: 00:18.6 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.6 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:18.7
    PCI: 00:18.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1a.0
    PCI: 00:1a.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 10
    PCI: 00:1a.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 14
    PCI: 00:1b.0
    PCI: 00:1c.0
    PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 00:1c.1
    PCI: 00:1c.2 child on link 0 PCI: 02:00.0
    PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
     PCI: 02:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
     PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
    PCI: 00:1c.3
    PCI: 00:1d.0
    PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
    PCI: 00:1e.0
    PCI: 00:1e.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1e.1
    PCI: 00:1e.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:1e.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1e.2
    PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1e.3
    PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1e.4
    PCI: 00:1e.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:1e.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1e.5
    PCI: 00:1e.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:1e.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 00:1f.0
    PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb
    PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44
    PCI: 00:1f.0 resource base fed0c000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4c
    PCI: 00:1f.0 resource base fed08000 size 400 align 0 gran 0 limit 0 flags f0000200 index 50
    PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54
    PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58
    PCI: 00:1f.0 resource base fed05000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c
    PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0
    PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff
    PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec
    PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:1f.3
    PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffffffff flags 200 index 10
    PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
 PCI: 02:00.0 18 *  [0x0 - 0x1f] io
 PCI: 00:1c.2 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.2 1c *  [0x0 - 0xfff] io
 PCI: 00:13.0 20 *  [0x1000 - 0x101f] io
 PCI: 00:1f.3 20 *  [0x1020 - 0x103f] io
 PCI: 00:02.0 20 *  [0x1040 - 0x1047] io
 PCI: 00:13.0 10 *  [0x1048 - 0x104f] io
 PCI: 00:13.0 18 *  [0x1050 - 0x1057] io
 PCI: 00:13.0 14 *  [0x1058 - 0x105b] io
 PCI: 00:13.0 1c *  [0x105c - 0x105f] io
 DOMAIN: 0000 io: base: 1060 size: 1060 align: 12 gran: 0 limit: ffff done
 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
 PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
 PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
 PCI: 02:00.0 10 *  [0x0 - 0x7fffff] mem
 PCI: 02:00.0 1c *  [0x800000 - 0x803fff] mem
 PCI: 00:1c.2 mem: base: 804000 size: 900000 align: 23 gran: 20 limit: ffffffff done
 PCI: 00:02.0 18 *  [0x0 - 0xfffffff] prefmem
 PCI: 00:1c.2 20 *  [0x10000000 - 0x108fffff] mem
 PCI: 00:02.0 10 *  [0x10c00000 - 0x10ffffff] mem
 PCI: 00:15.0 10 *  [0x11000000 - 0x111fffff] mem
 PCI: 00:1a.0 10 *  [0x11200000 - 0x112fffff] mem
 PCI: 00:1a.0 14 *  [0x11300000 - 0x113fffff] mem
 PCI: 00:18.0 10 *  [0x11400000 - 0x11403fff] mem
 PCI: 00:1e.0 10 *  [0x11404000 - 0x11407fff] mem
 PCI: 00:11.0 10 *  [0x11408000 - 0x11408fff] mem
 PCI: 00:11.0 14 *  [0x11409000 - 0x11409fff] mem
 PCI: 00:12.0 10 *  [0x1140a000 - 0x1140afff] mem
 PCI: 00:12.0 14 *  [0x1140b000 - 0x1140bfff] mem
 PCI: 00:15.0 14 *  [0x1140c000 - 0x1140cfff] mem
 PCI: 00:17.0 10 *  [0x1140d000 - 0x1140dfff] mem
 PCI: 00:17.0 14 *  [0x1140e000 - 0x1140efff] mem
 PCI: 00:18.0 14 *  [0x1140f000 - 0x1140ffff] mem
 PCI: 00:18.1 10 *  [0x11410000 - 0x11410fff] mem
 PCI: 00:18.1 14 *  [0x11411000 - 0x11411fff] mem
 PCI: 00:18.2 10 *  [0x11412000 - 0x11412fff] mem
 PCI: 00:18.2 14 *  [0x11413000 - 0x11413fff] mem
 PCI: 00:18.3 10 *  [0x11414000 - 0x11414fff] mem
 PCI: 00:18.3 14 *  [0x11415000 - 0x11415fff] mem
 PCI: 00:18.4 10 *  [0x11416000 - 0x11416fff] mem
 PCI: 00:18.4 14 *  [0x11417000 - 0x11417fff] mem
 PCI: 00:18.5 10 *  [0x11418000 - 0x11418fff] mem
 PCI: 00:18.5 14 *  [0x11419000 - 0x11419fff] mem
 PCI: 00:18.6 10 *  [0x1141a000 - 0x1141afff] mem
 PCI: 00:18.6 14 *  [0x1141b000 - 0x1141bfff] mem
 PCI: 00:18.7 10 *  [0x1141c000 - 0x1141cfff] mem
 PCI: 00:18.7 14 *  [0x1141d000 - 0x1141dfff] mem
 PCI: 00:1e.0 14 *  [0x1141e000 - 0x1141efff] mem
 PCI: 00:1e.1 10 *  [0x1141f000 - 0x1141ffff] mem
 PCI: 00:1e.1 14 *  [0x11420000 - 0x11420fff] mem
 PCI: 00:1e.2 10 *  [0x11421000 - 0x11421fff] mem
 PCI: 00:1e.2 14 *  [0x11422000 - 0x11422fff] mem
 PCI: 00:1e.3 10 *  [0x11423000 - 0x11423fff] mem
 PCI: 00:1e.3 14 *  [0x11424000 - 0x11424fff] mem
 PCI: 00:1e.4 10 *  [0x11425000 - 0x11425fff] mem
 PCI: 00:1e.4 14 *  [0x11426000 - 0x11426fff] mem
 PCI: 00:1e.5 10 *  [0x11427000 - 0x11427fff] mem
 PCI: 00:1e.5 14 *  [0x11428000 - 0x11428fff] mem
 PCI: 00:13.0 24 *  [0x11429000 - 0x114297ff] mem
 PCI: 00:1d.0 10 *  [0x11429800 - 0x11429bff] mem
 PCI: 00:1f.3 10 *  [0x11429c00 - 0x11429c1f] mem
 DOMAIN: 0000 mem: base: 11429c20 size: 11429c20 align: 28 gran: 0 limit: ffffffff done
 avoid_fixed_resources: DOMAIN: 0000
 avoid_fixed_resourcesDOMAIN: 0000 10000000 limit 0000ffff
 avoid_fixed_resourcesDOMAIN: 0000 10000100 limit ffffffff
 constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
 constrain_resources: PCI: 00:00.0 01 base 00100000 limit 7adfffff mem (fixed)
 constrain_resources: PCI: 00:00.0 02 base 7ae00000 limit 7fffffff mem (fixed)
 constrain_resources: PCI: 00:00.0 03 base e0000000 limit efffffff mem (fixed)
 constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
 avoid_fixed_resourcesDOMAIN: 0000 10000000 base 00001000 limit 0000ffff
 avoid_fixed_resourcesDOMAIN: 0000 10000100 base c0000000 limit dfffffff
 Setting resources...
 DOMAIN: 0000 io: base:1000 size:1060 align:12 gran:0 limit:ffff
 PCI: 00:1c.2 1c *  [0x1000 - 0x1fff] io
 PCI: 00:13.0 20 *  [0x2000 - 0x201f] io
 PCI: 00:1f.3 20 *  [0x2020 - 0x203f] io
 PCI: 00:02.0 20 *  [0x2040 - 0x2047] io
 PCI: 00:13.0 10 *  [0x2048 - 0x204f] io
 PCI: 00:13.0 18 *  [0x2050 - 0x2057] io
 PCI: 00:13.0 14 *  [0x2058 - 0x205b] io
 PCI: 00:13.0 1c *  [0x205c - 0x205f] io
 DOMAIN: 0000 io: next_base: 2060 size: 1060 align: 12 gran: 0 done
 PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
 PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
 PCI: 00:1c.2 io: base:1000 size:1000 align:12 gran:12 limit:1fff
 PCI: 02:00.0 18 *  [0x1000 - 0x101f] io
 PCI: 00:1c.2 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
 DOMAIN: 0000 mem: base:c0000000 size:11429c20 align:28 gran:0 limit:dfffffff
 PCI: 00:02.0 18 *  [0xc0000000 - 0xcfffffff] prefmem
 PCI: 00:1c.2 20 *  [0xd0000000 - 0xd08fffff] mem
 PCI: 00:02.0 10 *  [0xd0c00000 - 0xd0ffffff] mem
 PCI: 00:15.0 10 *  [0xd1000000 - 0xd11fffff] mem
 PCI: 00:1a.0 10 *  [0xd1200000 - 0xd12fffff] mem
 PCI: 00:1a.0 14 *  [0xd1300000 - 0xd13fffff] mem
 PCI: 00:18.0 10 *  [0xd1400000 - 0xd1403fff] mem
 PCI: 00:1e.0 10 *  [0xd1404000 - 0xd1407fff] mem
 PCI: 00:11.0 10 *  [0xd1408000 - 0xd1408fff] mem
 PCI: 00:11.0 14 *  [0xd1409000 - 0xd1409fff] mem
 PCI: 00:12.0 10 *  [0xd140a000 - 0xd140afff] mem
 PCI: 00:12.0 14 *  [0xd140b000 - 0xd140bfff] mem
 PCI: 00:15.0 14 *  [0xd140c000 - 0xd140cfff] mem
 PCI: 00:17.0 10 *  [0xd140d000 - 0xd140dfff] mem
 PCI: 00:17.0 14 *  [0xd140e000 - 0xd140efff] mem
 PCI: 00:18.0 14 *  [0xd140f000 - 0xd140ffff] mem
 PCI: 00:18.1 10 *  [0xd1410000 - 0xd1410fff] mem
 PCI: 00:18.1 14 *  [0xd1411000 - 0xd1411fff] mem
 PCI: 00:18.2 10 *  [0xd1412000 - 0xd1412fff] mem
 PCI: 00:18.2 14 *  [0xd1413000 - 0xd1413fff] mem
 PCI: 00:18.3 10 *  [0xd1414000 - 0xd1414fff] mem
 PCI: 00:18.3 14 *  [0xd1415000 - 0xd1415fff] mem
 PCI: 00:18.4 10 *  [0xd1416000 - 0xd1416fff] mem
 PCI: 00:18.4 14 *  [0xd1417000 - 0xd1417fff] mem
 PCI: 00:18.5 10 *  [0xd1418000 - 0xd1418fff] mem
 PCI: 00:18.5 14 *  [0xd1419000 - 0xd1419fff] mem
 PCI: 00:18.6 10 *  [0xd141a000 - 0xd141afff] mem
 PCI: 00:18.6 14 *  [0xd141b000 - 0xd141bfff] mem
 PCI: 00:18.7 10 *  [0xd141c000 - 0xd141cfff] mem
 PCI: 00:18.7 14 *  [0xd141d000 - 0xd141dfff] mem
 PCI: 00:1e.0 14 *  [0xd141e000 - 0xd141efff] mem
 PCI: 00:1e.1 10 *  [0xd141f000 - 0xd141ffff] mem
 PCI: 00:1e.1 14 *  [0xd1420000 - 0xd1420fff] mem
 PCI: 00:1e.2 10 *  [0xd1421000 - 0xd1421fff] mem
 PCI: 00:1e.2 14 *  [0xd1422000 - 0xd1422fff] mem
 PCI: 00:1e.3 10 *  [0xd1423000 - 0xd1423fff] mem
 PCI: 00:1e.3 14 *  [0xd1424000 - 0xd1424fff] mem
 PCI: 00:1e.4 10 *  [0xd1425000 - 0xd1425fff] mem
 PCI: 00:1e.4 14 *  [0xd1426000 - 0xd1426fff] mem
 PCI: 00:1e.5 10 *  [0xd1427000 - 0xd1427fff] mem
 PCI: 00:1e.5 14 *  [0xd1428000 - 0xd1428fff] mem
 PCI: 00:13.0 24 *  [0xd1429000 - 0xd14297ff] mem
 PCI: 00:1d.0 10 *  [0xd1429800 - 0xd1429bff] mem
 PCI: 00:1f.3 10 *  [0xd1429c00 - 0xd1429c1f] mem
 DOMAIN: 0000 mem: next_base: d1429c20 size: 11429c20 align: 28 gran: 0 done
 PCI: 00:1c.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
 PCI: 00:1c.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
 PCI: 00:1c.0 mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
 PCI: 00:1c.0 mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
 PCI: 00:1c.2 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
 PCI: 00:1c.2 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
 PCI: 00:1c.2 mem: base:d0000000 size:900000 align:23 gran:20 limit:d08fffff
 PCI: 02:00.0 10 *  [0xd0000000 - 0xd07fffff] mem
 PCI: 02:00.0 1c *  [0xd0800000 - 0xd0803fff] mem
 PCI: 00:1c.2 mem: next_base: d0804000 size: 900000 align: 23 gran: 20 done
 Root Device assign_resources, bus 0 link: 0
 DOMAIN: 0000 assign_resources, bus 0 link: 0
 PCI: 00:00.0 missing set_resources
 PCI: 00:02.0 10 <- [0x00d0c00000 - 0x00d0ffffff] size 0x00400000 gran 0x16 mem
 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem
 PCI: 00:02.0 20 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io
 PCI: 00:11.0 10 <- [0x00d1408000 - 0x00d1408fff] size 0x00001000 gran 0x0c mem
 PCI: 00:11.0 14 <- [0x00d1409000 - 0x00d1409fff] size 0x00001000 gran 0x0c mem
 PCI: 00:12.0 10 <- [0x00d140a000 - 0x00d140afff] size 0x00001000 gran 0x0c mem
 PCI: 00:12.0 14 <- [0x00d140b000 - 0x00d140bfff] size 0x00001000 gran 0x0c mem
 PCI: 00:13.0 10 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io
 PCI: 00:13.0 14 <- [0x0000002058 - 0x000000205b] size 0x00000004 gran 0x02 io
 PCI: 00:13.0 18 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io
 PCI: 00:13.0 1c <- [0x000000205c - 0x000000205f] size 0x00000004 gran 0x02 io
 PCI: 00:13.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
 PCI: 00:13.0 24 <- [0x00d1429000 - 0x00d14297ff] size 0x00000800 gran 0x0b mem
 PCI: 00:15.0 10 <- [0x00d1000000 - 0x00d11fffff] size 0x00200000 gran 0x15 mem
 PCI: 00:15.0 14 <- [0x00d140c000 - 0x00d140cfff] size 0x00001000 gran 0x0c mem
 PCI: 00:17.0 10 <- [0x00d140d000 - 0x00d140dfff] size 0x00001000 gran 0x0c mem
 PCI: 00:17.0 14 <- [0x00d140e000 - 0x00d140efff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.0 10 <- [0x00d1400000 - 0x00d1403fff] size 0x00004000 gran 0x0e mem
 PCI: 00:18.0 14 <- [0x00d140f000 - 0x00d140ffff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.1 10 <- [0x00d1410000 - 0x00d1410fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.1 14 <- [0x00d1411000 - 0x00d1411fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.2 10 <- [0x00d1412000 - 0x00d1412fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.2 14 <- [0x00d1413000 - 0x00d1413fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.3 10 <- [0x00d1414000 - 0x00d1414fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.3 14 <- [0x00d1415000 - 0x00d1415fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.4 10 <- [0x00d1416000 - 0x00d1416fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.4 14 <- [0x00d1417000 - 0x00d1417fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.5 10 <- [0x00d1418000 - 0x00d1418fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.5 14 <- [0x00d1419000 - 0x00d1419fff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.6 10 <- [0x00d141a000 - 0x00d141afff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.6 14 <- [0x00d141b000 - 0x00d141bfff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.7 10 <- [0x00d141c000 - 0x00d141cfff] size 0x00001000 gran 0x0c mem
 PCI: 00:18.7 14 <- [0x00d141d000 - 0x00d141dfff] size 0x00001000 gran 0x0c mem
 PCI: 00:1a.0 10 <- [0x00d1200000 - 0x00d12fffff] size 0x00100000 gran 0x14 mem
 PCI: 00:1a.0 14 <- [0x00d1300000 - 0x00d13fffff] size 0x00100000 gran 0x14 mem
 PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
 PCI: 00:1c.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
 PCI: 00:1c.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem
 PCI: 00:1c.2 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
 PCI: 00:1c.2 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
 PCI: 00:1c.2 20 <- [0x00d0000000 - 0x00d08fffff] size 0x00900000 gran 0x14 bus 02 mem
 PCI: 00:1c.2 assign_resources, bus 2 link: 0
 PCI: 02:00.0 10 <- [0x00d0000000 - 0x00d07fffff] size 0x00800000 gran 0x17 mem
 PCI: 02:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
 PCI: 02:00.0 1c <- [0x00d0800000 - 0x00d0803fff] size 0x00004000 gran 0x0e mem
 PCI: 00:1c.2 assign_resources, bus 2 link: 0
 PCI: 00:1d.0 10 <- [0x00d1429800 - 0x00d1429bff] size 0x00000400 gran 0x0a mem
 PCI: 00:1e.0 10 <- [0x00d1404000 - 0x00d1407fff] size 0x00004000 gran 0x0e mem
 PCI: 00:1e.0 14 <- [0x00d141e000 - 0x00d141efff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.1 10 <- [0x00d141f000 - 0x00d141ffff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.1 14 <- [0x00d1420000 - 0x00d1420fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.2 10 <- [0x00d1421000 - 0x00d1421fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.2 14 <- [0x00d1422000 - 0x00d1422fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.3 10 <- [0x00d1423000 - 0x00d1423fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.3 14 <- [0x00d1424000 - 0x00d1424fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.4 10 <- [0x00d1425000 - 0x00d1425fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.4 14 <- [0x00d1426000 - 0x00d1426fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.5 10 <- [0x00d1427000 - 0x00d1427fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1e.5 14 <- [0x00d1428000 - 0x00d1428fff] size 0x00001000 gran 0x0c mem
 PCI: 00:1f.3 10 <- [0x00d1429c00 - 0x00d1429c1f] size 0x00000020 gran 0x05 mem
 PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
 DOMAIN: 0000 assign_resources, bus 0 link: 0
 Root Device assign_resources, bus 0 link: 0
 Done setting resources.
 Show resources in subtree (Root Device)...After assigning values.
  Root Device child on link 0 CPU_CLUSTER: 0
   CPU_CLUSTER: 0 child on link 0 APIC: 00
    APIC: 00
   DOMAIN: 0000 child on link 0 PCI: 00:00.0
   DOMAIN: 0000 resource base 1000 size 1060 align 12 gran 0 limit ffff flags 40040100 index 10000000
   DOMAIN: 0000 resource base c0000000 size 11429c20 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
    PCI: 00:00.0
    PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
    PCI: 00:00.0 resource base 100000 size 7ad00000 align 0 gran 0 limit 0 flags e0004200 index 1
    PCI: 00:00.0 resource base 7ae00000 size 5200000 align 0 gran 0 limit 0 flags f0000200 index 2
    PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 3
    PCI: 00:00.0 resource base fee00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
    PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 5
    PCI: 00:02.0
    PCI: 00:02.0 resource base d0c00000 size 400000 align 22 gran 22 limit d0ffffff flags 60000200 index 10
    PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001200 index 18
    PCI: 00:02.0 resource base 2040 size 8 align 3 gran 3 limit 2047 flags 60000100 index 20
    PCI: 00:03.0
    PCI: 00:10.0
    PCI: 00:11.0
    PCI: 00:11.0 resource base d1408000 size 1000 align 12 gran 12 limit d1408fff flags 60000200 index 10
    PCI: 00:11.0 resource base d1409000 size 1000 align 12 gran 12 limit d1409fff flags 60000200 index 14
    PCI: 00:12.0
    PCI: 00:12.0 resource base d140a000 size 1000 align 12 gran 12 limit d140afff flags 60000200 index 10
    PCI: 00:12.0 resource base d140b000 size 1000 align 12 gran 12 limit d140bfff flags 60000200 index 14
    PCI: 00:13.0
    PCI: 00:13.0 resource base 2048 size 8 align 3 gran 3 limit 204f flags 60000100 index 10
    PCI: 00:13.0 resource base 2058 size 4 align 2 gran 2 limit 205b flags 60000100 index 14
    PCI: 00:13.0 resource base 2050 size 8 align 3 gran 3 limit 2057 flags 60000100 index 18
    PCI: 00:13.0 resource base 205c size 4 align 2 gran 2 limit 205f flags 60000100 index 1c
    PCI: 00:13.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 20
    PCI: 00:13.0 resource base d1429000 size 800 align 11 gran 11 limit d14297ff flags 60000200 index 24
    PCI: 00:14.0
    PCI: 00:15.0
    PCI: 00:15.0 resource base d1000000 size 200000 align 21 gran 21 limit d11fffff flags 60000200 index 10
    PCI: 00:15.0 resource base d140c000 size 1000 align 12 gran 12 limit d140cfff flags 60000200 index 14
    PCI: 00:17.0
    PCI: 00:17.0 resource base d140d000 size 1000 align 12 gran 12 limit d140dfff flags 60000200 index 10
    PCI: 00:17.0 resource base d140e000 size 1000 align 12 gran 12 limit d140efff flags 60000200 index 14
    PCI: 00:18.0
    PCI: 00:18.0 resource base d1400000 size 4000 align 14 gran 14 limit d1403fff flags 60000200 index 10
    PCI: 00:18.0 resource base d140f000 size 1000 align 12 gran 12 limit d140ffff flags 60000200 index 14
    PCI: 00:18.1
    PCI: 00:18.1 resource base d1410000 size 1000 align 12 gran 12 limit d1410fff flags 60000200 index 10
    PCI: 00:18.1 resource base d1411000 size 1000 align 12 gran 12 limit d1411fff flags 60000200 index 14
    PCI: 00:18.2
    PCI: 00:18.2 resource base d1412000 size 1000 align 12 gran 12 limit d1412fff flags 60000200 index 10
    PCI: 00:18.2 resource base d1413000 size 1000 align 12 gran 12 limit d1413fff flags 60000200 index 14
    PCI: 00:18.3
    PCI: 00:18.3 resource base d1414000 size 1000 align 12 gran 12 limit d1414fff flags 60000200 index 10
    PCI: 00:18.3 resource base d1415000 size 1000 align 12 gran 12 limit d1415fff flags 60000200 index 14
    PCI: 00:18.4
    PCI: 00:18.4 resource base d1416000 size 1000 align 12 gran 12 limit d1416fff flags 60000200 index 10
    PCI: 00:18.4 resource base d1417000 size 1000 align 12 gran 12 limit d1417fff flags 60000200 index 14
    PCI: 00:18.5
    PCI: 00:18.5 resource base d1418000 size 1000 align 12 gran 12 limit d1418fff flags 60000200 index 10
    PCI: 00:18.5 resource base d1419000 size 1000 align 12 gran 12 limit d1419fff flags 60000200 index 14
    PCI: 00:18.6
    PCI: 00:18.6 resource base d141a000 size 1000 align 12 gran 12 limit d141afff flags 60000200 index 10
    PCI: 00:18.6 resource base d141b000 size 1000 align 12 gran 12 limit d141bfff flags 60000200 index 14
    PCI: 00:18.7
    PCI: 00:18.7 resource base d141c000 size 1000 align 12 gran 12 limit d141cfff flags 60000200 index 10
    PCI: 00:18.7 resource base d141d000 size 1000 align 12 gran 12 limit d141dfff flags 60000200 index 14
    PCI: 00:1a.0
    PCI: 00:1a.0 resource base d1200000 size 100000 align 20 gran 20 limit d12fffff flags 60000200 index 10
    PCI: 00:1a.0 resource base d1300000 size 100000 align 20 gran 20 limit d13fffff flags 60000200 index 14
    PCI: 00:1b.0
    PCI: 00:1c.0
    PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
    PCI: 00:1c.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
    PCI: 00:1c.1
    PCI: 00:1c.2 child on link 0 PCI: 02:00.0
    PCI: 00:1c.2 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
    PCI: 00:1c.2 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
    PCI: 00:1c.2 resource base d0000000 size 900000 align 23 gran 20 limit d08fffff flags 60080202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base d0000000 size 800000 align 23 gran 23 limit d07fffff flags 60000200 index 10
     PCI: 02:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
     PCI: 02:00.0 resource base d0800000 size 4000 align 14 gran 14 limit d0803fff flags 60000200 index 1c
    PCI: 00:1c.3
    PCI: 00:1d.0
    PCI: 00:1d.0 resource base d1429800 size 400 align 10 gran 10 limit d1429bff flags 60000200 index 10
    PCI: 00:1e.0
    PCI: 00:1e.0 resource base d1404000 size 4000 align 14 gran 14 limit d1407fff flags 60000200 index 10
    PCI: 00:1e.0 resource base d141e000 size 1000 align 12 gran 12 limit d141efff flags 60000200 index 14
    PCI: 00:1e.1
    PCI: 00:1e.1 resource base d141f000 size 1000 align 12 gran 12 limit d141ffff flags 60000200 index 10
    PCI: 00:1e.1 resource base d1420000 size 1000 align 12 gran 12 limit d1420fff flags 60000200 index 14
    PCI: 00:1e.2
    PCI: 00:1e.2 resource base d1421000 size 1000 align 12 gran 12 limit d1421fff flags 60000200 index 10
    PCI: 00:1e.2 resource base d1422000 size 1000 align 12 gran 12 limit d1422fff flags 60000200 index 14
    PCI: 00:1e.3
    PCI: 00:1e.3 resource base d1423000 size 1000 align 12 gran 12 limit d1423fff flags 60000200 index 10
    PCI: 00:1e.3 resource base d1424000 size 1000 align 12 gran 12 limit d1424fff flags 60000200 index 14
    PCI: 00:1e.4
    PCI: 00:1e.4 resource base d1425000 size 1000 align 12 gran 12 limit d1425fff flags 60000200 index 10
    PCI: 00:1e.4 resource base d1426000 size 1000 align 12 gran 12 limit d1426fff flags 60000200 index 14
    PCI: 00:1e.5
    PCI: 00:1e.5 resource base d1427000 size 1000 align 12 gran 12 limit d1427fff flags 60000200 index 10
    PCI: 00:1e.5 resource base d1428000 size 1000 align 12 gran 12 limit d1428fff flags 60000200 index 14
    PCI: 00:1f.0
    PCI: 00:1f.0 resource base feb00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index feb
    PCI: 00:1f.0 resource base fed03000 size 400 align 0 gran 0 limit 0 flags f0000200 index 44
    PCI: 00:1f.0 resource base fed0c000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4c
    PCI: 00:1f.0 resource base fed08000 size 400 align 0 gran 0 limit 0 flags f0000200 index 50
    PCI: 00:1f.0 resource base fed01000 size 400 align 0 gran 0 limit 0 flags f0000200 index 54
    PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 58
    PCI: 00:1f.0 resource base fed05000 size 800 align 0 gran 0 limit 0 flags f0000200 index 5c
    PCI: 00:1f.0 resource base fed1c000 size 400 align 0 gran 0 limit 0 flags f0000200 index f0
    PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index fff
    PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags f0000200 index fec
    PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:1f.3
    PCI: 00:1f.3 resource base d1429c00 size 20 align 5 gran 5 limit d1429c1f flags 60000200 index 10
    PCI: 00:1f.3 resource base 2020 size 20 align 5 gran 5 limit 203f flags 60000100 index 20
 Done allocating resources.
 BS: BS_DEV_RESOURCES times (us): entry 0 run 3062621 exit 0
 POST: 0x74
 Enabling resources...
 PCI: 00:02.0 subsystem <- 0000/0000
 PCI: 00:02.0 cmd <- 07
 PCI: 00:11.0 subsystem <- 0000/0000
 PCI: 00:11.0 cmd <- 106
 PCI: 00:12.0 subsystem <- 0000/0000
 PCI: 00:12.0 cmd <- 106
 PCI: 00:13.0 subsystem <- 0000/0000
 PCI: 00:13.0 cmd <- 107
 PCI: 00:15.0 subsystem <- 0000/0000
 PCI: 00:15.0 cmd <- 102
 PCI: 00:17.0 subsystem <- 0000/0000
 PCI: 00:17.0 cmd <- 106
 PCI: 00:18.0 subsystem <- 0000/0000
 PCI: 00:18.0 cmd <- 106
 PCI: 00:18.1 subsystem <- 0000/0000
 PCI: 00:18.1 cmd <- 102
 PCI: 00:18.2 subsystem <- 0000/0000
 PCI: 00:18.2 cmd <- 102
 PCI: 00:18.3 subsystem <- 0000/0000
 PCI: 00:18.3 cmd <- 102
 PCI: 00:18.4 subsystem <- 0000/0000
 PCI: 00:18.4 cmd <- 102
 PCI: 00:18.5 subsystem <- 0000/0000
 PCI: 00:18.5 cmd <- 102
 PCI: 00:18.6 subsystem <- 0000/0000
 PCI: 00:18.6 cmd <- 102
 PCI: 00:18.7 subsystem <- 0000/0000
 PCI: 00:18.7 cmd <- 102
 PCI: 00:1a.0 subsystem <- 0000/0000
 PCI: 00:1a.0 cmd <- 102
 PCI: 00:1c.0 bridge ctrl <- 0003
 PCI: 00:1c.0 cmd <- 100
 PCI: 00:1c.2 bridge ctrl <- 0003
 PCI: 00:1c.2 cmd <- 107
 PCI: 00:1d.0 subsystem <- 0000/0000
 PCI: 00:1d.0 cmd <- 102
 PCI: 00:1e.0 subsystem <- 0000/0000
 PCI: 00:1e.0 cmd <- 106
 PCI: 00:1e.1 subsystem <- 0000/0000
 PCI: 00:1e.1 cmd <- 102
 PCI: 00:1e.2 subsystem <- 0000/0000
 PCI: 00:1e.2 cmd <- 102
 PCI: 00:1e.3 subsystem <- 0000/0000
 PCI: 00:1e.3 cmd <- 102
 PCI: 00:1e.4 subsystem <- 0000/0000
 PCI: 00:1e.4 cmd <- 102
 PCI: 00:1e.5 subsystem <- 0000/0000
 PCI: 00:1e.5 cmd <- 102
 PCI: 00:1f.3 subsystem <- 0000/0000
 PCI: 00:1f.3 cmd <- 103
 PCI: 02:00.0 cmd <- 03
 done.
 BS: BS_DEV_ENABLE times (us): entry 0 run 156495 exit 0
 POST: 0x75
 Initializing devices...
 Root Device init ...
 Root Device init finished in 2138 usecs
 POST: 0x75
 CPU_CLUSTER: 0 init ...
 
 MTRR check
 Fixed MTRRs   : Enabled
 Variable MTRRs: Enabled
 
 POST: 0x93
 Setting up local apic... apic_id: 0x00 done.
 POST: 0x9b
 CPU: Intel(R) Atom(TM) CPU  E3825  @ 1.33GHz.
 Loading module at 00030000 with entry 00030000. filesize: 0x140 memsize: 0x140
 Processing 16 relocs. Offset value of 0x00030000
 Attempting to start 1 APs
 Waiting for 10ms after sending INIT.
 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 4.
 done.
 Waiting for 2nd SIPI to complete...done.
 Loading module at 00038000 with entry 00038000. filesize: 0x180 memsize: 0x180
 Processing 10 relocs. Offset value of 0x00038000
 SMM Module: stub loaded at 00038000. Will call 001031a6(00000000)
 Installing SMM handler to 0x7b000000
 Loading module at 7b010000 with entry 7b010056. filesize: 0x4c8 memsize: 0x44d8
 Processing 20 relocs. Offset value of 0x7b010000
 Loading module at 7b008000 with entry 7b008000. filesize: 0x180 memsize: 0x180
 Processing 10 relocs. Offset value of 0x7b008000
 SMM Module: placing jmp sequence at 7b007c00 rel16 0x03fd
 SMM Module: stub loaded at 7b008000. Will call 7b010056(00000000)
 Initializing Southbridge SMI... pmbase = 0x0400
 SMI_STS: PM1 
 PM1_STS: TMROF 
 New SMBASE 0x7b000000
 Relocation complete.
 New SMBASE 0x7afffc00
 Relocation complete.
 Initializing CPU #0
 CPU: vendor Intel device 30679
 CPU: family 06, model 37, stepping 09
 Init BayTrail core.
 CPU #0 initialized
 Initializing CPU #1
 CPU: vendor Intel device 30679
 CPU: family 06, model 37, stepping 09
 Init BayTrail core.
 Turbo is unavailable
 CPU #1 initialized
 Enabling SMIs.
 GPIO_ROUT = 00000000
 ALT_GPIO_SMI = 00000000
 CPU_CLUSTER: 0 init finished in 171068 usecs
 POST: 0x75
 POST: 0x75
 POST: 0x75
 POST: 0x75
 POST: 0x75
 PCI: 00:02.0 init ...
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'pci8086,0f31.rom'
 CBFS: 'pci8086,0f31.rom' not found.
 PCI: 00:02.0 init finished in 12365 usecs
 POST: 0x75
 POST: 0x75
 POST: 0x75
 PCI: 00:11.0 init ...
 PCI: 00:11.0 init finished in 2236 usecs
 POST: 0x75
 PCI: 00:12.0 init ...
 src/soc/intel/fsp_baytrail/emmc.c/scc_enable_acpi_mode ( Intel BayTrail SoC, 0x00000504, 0x00000002 )
 PCI: 00:12.0 init finished in 12244 usecs
 POST: 0x75
 PCI: 00:13.0 init ...
 PCI: 00:13.0 init finished in 2236 usecs
 POST: 0x75
 POST: 0x75
 PCI: 00:15.0 init ...
 PCI: 00:15.0 init finished in 2236 usecs
 POST: 0x75
 PCI: 00:17.0 init ...
 eMMC init
 src/soc/intel/fsp_baytrail/emmc.c/scc_enable_acpi_mode ( Intel BayTrail SoC, 0x0000050c, 0x00000000 )
 PCI: 00:17.0 init finished in 13335 usecs
 POST: 0x75
 PCI: 00:18.0 init ...
 PCI: 00:18.0 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:18.1 init ...
 Releasing I2C device from reset.
 PCI: 00:18.1 init finished in 5552 usecs
 POST: 0x75
 PCI: 00:18.2 init ...
 Releasing I2C device from reset.
 PCI: 00:18.2 init finished in 5551 usecs
 POST: 0x75
 PCI: 00:18.3 init ...
 Releasing I2C device from reset.
 PCI: 00:18.3 init finished in 5551 usecs
 POST: 0x75
 PCI: 00:18.4 init ...
 Releasing I2C device from reset.
 PCI: 00:18.4 init finished in 5550 usecs
 POST: 0x75
 PCI: 00:18.5 init ...
 Releasing I2C device from reset.
 PCI: 00:18.5 init finished in 5550 usecs
 POST: 0x75
 PCI: 00:18.6 init ...
 Releasing I2C device from reset.
 PCI: 00:18.6 init finished in 5551 usecs
 POST: 0x75
 PCI: 00:18.7 init ...
 Releasing I2C device from reset.
 PCI: 00:18.7 init finished in 5551 usecs
 POST: 0x75
 PCI: 00:1a.0 init ...
 PCI: 00:1a.0 init finished in 2236 usecs
 POST: 0x75
 POST: 0x75
 POST: 0x75
 POST: 0x75
 POST: 0x75
 POST: 0x75
 PCI: 00:1d.0 init ...
 PCI: 00:1d.0 init finished in 2236 usecs
 POST: 0x75
 PCI: 00:1e.0 init ...
 PCI: 00:1e.0 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1e.1 init ...
 PCI: 00:1e.1 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1e.2 init ...
 PCI: 00:1e.2 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1e.3 init ...
 PCI: 00:1e.3 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1e.4 init ...
 PCI: 00:1e.4 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1e.5 init ...
 PCI: 00:1e.5 init finished in 2247 usecs
 POST: 0x75
 PCI: 00:1f.0 init ...
 soc: southcluster_init
 Southbridge APIC ID = 2
 Dumping IOAPIC registers
   reg 0x0000: 0x02000000
   reg 0x0001: 0x00560020
   reg 0x0002: 0x00560020
 Start writing IRQ assignments
 PIRQ        A         B         C         D         E         F         G         H
 IRQ         4        5        7        10        11        12        14        15
 
                         PIRQ[A-H] routed to each INT_PIN[A-D]
 Dev        INTA (IRQ)        INTB (IRQ)        INTC (IRQ)        INTD (IRQ)
  16:         D    (10)        E    (11)        F    (12)        G    (14)
  17:         B    (5)        A    (4)        A    (4)        A    (4)
  18:         C    (7)        A    (4)        A    (4)        A    (4)
  19:         D    (10)        A    (4)        A    (4)        A    (4)
  20:         E    (11)        A    (4)        A    (4)        A    (4)
  21:         F    (12)        A    (4)        A    (4)        A    (4)
  23:         F    (12)        A    (4)        A    (4)        A    (4)
  24:         B    (5)        A    (4)        D    (10)        C    (7)
  26:         F    (12)        A    (4)        A    (4)        A    (4)
  27:         G    (14)        A    (4)        A    (4)        A    (4)
  28:         E    (11)        F    (12)        G    (14)        H    (15)
  29:         D    (10)        A    (4)        A    (4)        A    (4)
  30:         B    (5)        D    (10)        E    (11)        F    (12)
  31:         H    (15)        G    (14)        B    (5)        C    (7)
 Finished writing IRQ assignments
 PCI_CFG IRQ: Write PCI config space IRQ assignments
 PCI IRQ: Found device 0:02.00 using PIN A
 Warning: PCI Device 2 does not have an IRQ entry, skipping it
 PCI IRQ: Found device 0:11.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : B
         INT_LINE        : 0x5 (IRQ 5)
 PCI IRQ: Found device 0:12.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : C
         INT_LINE        : 0x7 (IRQ 7)
 PCI IRQ: Found device 0:13.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : D
         INT_LINE        : 0xA (IRQ 10)
 PCI IRQ: Found device 0:15.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : F
         INT_LINE        : 0xC (IRQ 12)
 PCI IRQ: Found device 0:17.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : F
         INT_LINE        : 0xC (IRQ 12)
 PCI IRQ: Found device 0:1A.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : F
         INT_LINE        : 0xC (IRQ 12)
 PCI IRQ: Found device 0:1C.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : E
         INT_LINE        : 0xB (IRQ 11)
 PCI IRQ: Found device 0:1C.02 using PIN C
         INT_PIN                : 3 (PIN C)
         PIRQ                : G
         INT_LINE        : 0xE (IRQ 14)
 PCI IRQ: Found device 0:1D.00 using PIN A
         INT_PIN                : 1 (PIN A)
         PIRQ                : D
         INT_LINE        : 0xA (IRQ 10)
 PCI IRQ: Found device 0:1F.03 using PIN B
         INT_PIN                : 2 (PIN B)
         PIRQ                : G
         INT_LINE        : 0xE (IRQ 14)
 PCI IRQ: Found device 2:00.00 using PIN A
         With INT_PIN swizzled to PIN A
         Attached to bridge device 0:1Ch.02h
         INT_PIN                : 1 (PIN A)
         Swizzled to        : 1 (PIN A)
         PIRQ                : E
         INT_LINE        : 0xB (IRQ 11)
 PCI_CFG IRQ: Finished writing PCI config space IRQ assignments
 PCI: 00:1f.0 init finished in 240717 usecs
 POST: 0x75
 PCI: 00:1f.3 init ...
 PCI: 00:1f.3 init finished in 2236 usecs
 POST: 0x75
 PCI: 02:00.0 init ...
 PCI: 02:00.0 init finished in 2236 usecs
 Devices initialized
 Show all devs... After init.
 Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
 APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
 PCI: 00:00.0: enabled 1
 PCI: 00:02.0: enabled 1
 PCI: 00:03.0: enabled 0
 PCI: 00:10.0: enabled 0
 PCI: 00:11.0: enabled 1
 PCI: 00:12.0: enabled 1
 PCI: 00:13.0: enabled 1
 PCI: 00:14.0: enabled 0
 PCI: 00:15.0: enabled 1
 PCI: 00:17.0: enabled 1
 PCI: 00:18.0: enabled 1
 PCI: 00:18.1: enabled 1
 PCI: 00:18.2: enabled 1
 PCI: 00:18.3: enabled 1
 PCI: 00:18.4: enabled 1
 PCI: 00:18.5: enabled 1
 PCI: 00:18.6: enabled 1
 PCI: 00:18.7: enabled 1
 PCI: 00:1a.0: enabled 1
 PCI: 00:1b.0: enabled 0
 PCI: 00:1c.0: enabled 1
 PCI: 00:1c.1: enabled 0
 PCI: 00:1c.2: enabled 1
 PCI: 00:1c.3: enabled 0
 PCI: 00:1d.0: enabled 1
 PCI: 00:1e.0: enabled 1
 PCI: 00:1e.1: enabled 1
 PCI: 00:1e.2: enabled 1
 PCI: 00:1e.3: enabled 1
 PCI: 00:1e.4: enabled 1
 PCI: 00:1e.5: enabled 1
 PCI: 00:1f.0: enabled 1
 PCI: 00:1f.3: enabled 1
 PCI: 02:00.0: enabled 1
 APIC: 04: enabled 1
 BS: BS_DEV_INIT times (us): entry 0 run 780116 exit 0
 POST: 0x76
 Finalize devices...
 Devices finalized
 FspNotify(EnumInitPhaseAfterPciEnumeration)
 Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)
 BS: BS_POST_DEVICE times (us): entry 0 run 5057 exit 11249
 POST: 0x77
 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1168 exit 0
 
 === FSP HOB Data Structure ===
 FSP Hoblistptr: 0x7ae20000
 HOB 0x7ae20000 is an EFI_HOB_TYPE_HANDOFF (type 0x1)
 HOB 0x7ae20038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae20038 with length0x81f3
   Address: 7ae20040 Guid: ea296d92-0b69-423c-8c2833b4e0a91268
 HOB 0x7ae200f0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae200f0 with length0x81f3
   Address: 7ae200f8 Guid: 9b3ada4f-ae56-4c24-8deaf03b7558ae50
 HOB 0x7ae201e8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae201e8 with length0xc381
   Address: 7ae201f0 Guid: 80dbd530-b74c-4f11-8c03418665532831
 HOB 0x7ae21860 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07
   at location 0x0 with length 0xa0000
 HOB 0x7ae21890 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07
   at location 0xa0000 with length 0x60000
 HOB 0x7ae218c0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07
   at location 0x100000 with length 0x7ad00000
 HOB 0x7ae218f0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07
   at location 0x7ae00000 with length 0x200000
 HOB 0x7ae21920 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x407
   at location 0x7b000000 with length 0xe00000
 HOB 0x7ae21950 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
   Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x407
   at location 0x7be00000 with length 0x4200000
 HOB 0x7ae21980 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae21980 with length0xc381
   Address: 7ae21988 Guid: 721acf02-4d77-4c2a-b3dc270b7ba9e4b0
 HOB 0x7ae22ff8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7ae00000 with length 0x20000
 HOB 0x7ae23028 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afff000 with length 0x1000
 HOB 0x7ae23058 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7affa000 with length 0x5000
 HOB 0x7ae23088 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae23088 with length0xcba1
   Address: 7ae23090 Guid: bbcff46c-c8d3-4113-8985b9d4f3b3f64e
 HOB 0x7ae270a0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae270d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7aff8000 with length 0x2000
 HOB 0x7ae27108 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
   at location 7ae27108 with length0xeba1
   Address: 7ae27110 Guid: 86d70125-baa3-4296-a62f602bebbb9081
 HOB 0x7ae272b8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7aff4000 with length 0x4000
 HOB 0x7ae272e8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7aff2000 with length 0x2000
 HOB 0x7ae27318 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7aff1000 with length 0x1000
 HOB 0x7ae27348 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afed000 with length 0x4000
 HOB 0x7ae27378 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afeb000 with length 0x2000
 HOB 0x7ae273a8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afea000 with length 0x1000
 HOB 0x7ae273d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afe6000 with length 0x4000
 HOB 0x7ae27408 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afe0000 with length 0x6000
 HOB 0x7ae27438 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afdb000 with length 0x5000
 HOB 0x7ae27468 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afd7000 with length 0x4000
 HOB 0x7ae27498 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afd4000 with length 0x3000
 HOB 0x7ae274c8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afd2000 with length 0x2000
 HOB 0x7ae274f8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afce000 with length 0x4000
 HOB 0x7ae27528 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afc3000 with length 0xb000
 HOB 0x7ae27558 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afb9000 with length 0xa000
 HOB 0x7ae27588 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afb5000 with length 0x4000
 HOB 0x7ae275b8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afb3000 with length 0x2000
 HOB 0x7ae275e8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afb2000 with length 0x1000
 HOB 0x7ae27618 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afae000 with length 0x4000
 HOB 0x7ae27648 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afab000 with length 0x3000
 HOB 0x7ae27678 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afa9000 with length 0x2000
 HOB 0x7ae276a8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afa5000 with length 0x4000
 HOB 0x7ae276d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afa2000 with length 0x3000
 HOB 0x7ae27708 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7afa0000 with length 0x2000
 HOB 0x7ae27738 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27750 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27790 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae277a8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae277f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27800 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27818 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27828 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27838 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27848 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27a50 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
   Memory type EfiBootServicesData (0x4)
   at location 0x7af90000 with length 0x10000
 HOB 0x7ae27a80 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
 HOB 0x7ae27ba0 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff)
 === End of FSP HOB Data Structure ===
 
 Memory Configure Data Hob at 7ae21998 (size = 0x1678).
 Copy FSP MRC DATA to HOB (source addr 7ae21998, dest addr 7acfa000, 5760 bytes)
 Fast boot data (includes align and checksum):
 Updating fast boot cache data.
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'mrc.cache'
 CBFS: Found @ offset 24ffc0 size 10000
 find_current_mrc_cache_local: No valid fast boot cache found.
 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
 Need to erase the MRC cache region of 65536 bytes at fff50000
 SF: Successfully erased 65536 bytes @ 0x750000
 Write MRC cache update to flash at fff50000
 POST: 0x79
 POST: 0x9c
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'fallback/dsdt.aml'
 CBFS: Found @ offset 10640 size 31dc
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'fallback/slic'
 CBFS: 'fallback/slic' not found.
 ACPI: Writing ACPI tables at 7acd6000.
 ACPI:    * FACS
 ACPI:    * DSDT
 ACPI:    * FADT
 SCI is IRQ9
 ACPI: added table 1/32, length now 40
 ACPI:     * SSDT
 PSS: 1333MHz power 161000 control 0xa35 status 0xa35
 PSS: 1199MHz power 143161 control 0x934 status 0x934
 PSS: 1066MHz power 125837 control 0x832 status 0x832
 PSS: 933MHz power 108868 control 0x730 status 0x730
 PSS: 799MHz power 92156 control 0x62e status 0x62e
 PSS: 666MHz power 75911 control 0x52c status 0x52c
 PSS: 533MHz power 60020 control 0x42a status 0x42a
 PSS: 1333MHz power 161000 control 0xa35 status 0xa35
 PSS: 1199MHz power 143161 control 0x934 status 0x934
 PSS: 1066MHz power 125837 control 0x832 status 0x832
 PSS: 933MHz power 108868 control 0x730 status 0x730
 PSS: 799MHz power 92156 control 0x62e status 0x62e
 PSS: 666MHz power 75911 control 0x52c status 0x52c
 PSS: 533MHz power 60020 control 0x42a status 0x42a
 ACPI: added table 2/32, length now 44
 ACPI:    * MCFG
 ACPI: added table 3/32, length now 48
 ACPI:    * TCPA
 TCPA log created at 7acc6000
 ACPI: added table 4/32, length now 52
 ACPI:    * MADT
 ACPI: added table 5/32, length now 56
 current = 7acd9ce0
 ACPI:    * HPET
 ACPI: added table 6/32, length now 60
 ACPI:     * SSDT2 not generated.
 current = 7acd9d20
 ACPI: done.
 ACPI tables: 15648 bytes.
 smbios_write_tables: 7acc5000
 Root Device (Intel Minnow Max)
 CPU_CLUSTER: 0 (Intel BayTrail SoC)
 APIC: 00 (Intel BayTrail SoC)
 DOMAIN: 0000 (Intel BayTrail SoC)
 PCI: 00:00.0 (Intel BayTrail SoC)
 PCI: 00:02.0 (Intel BayTrail SoC)
 PCI: 00:03.0 (Intel BayTrail SoC)
 PCI: 00:10.0 (Intel BayTrail SoC)
 PCI: 00:11.0 (Intel BayTrail SoC)
 PCI: 00:12.0 (Intel BayTrail SoC)
 PCI: 00:13.0 (Intel BayTrail SoC)
 PCI: 00:14.0 (Intel BayTrail SoC)
 PCI: 00:15.0 (Intel BayTrail SoC)
 PCI: 00:17.0 (Intel BayTrail SoC)
 PCI: 00:18.0 (Intel BayTrail SoC)
 PCI: 00:18.1 (Intel BayTrail SoC)
 PCI: 00:18.2 (Intel BayTrail SoC)
 PCI: 00:18.3 (Intel BayTrail SoC)
 PCI: 00:18.4 (Intel BayTrail SoC)
 PCI: 00:18.5 (Intel BayTrail SoC)
 PCI: 00:18.6 (Intel BayTrail SoC)
 PCI: 00:18.7 (Intel BayTrail SoC)
 PCI: 00:1a.0 (Intel BayTrail SoC)
 PCI: 00:1b.0 (Intel BayTrail SoC)
 PCI: 00:1c.0 (Intel BayTrail SoC)
 PCI: 00:1c.1 (Intel BayTrail SoC)
 PCI: 00:1c.2 (Intel BayTrail SoC)
 PCI: 00:1c.3 (Intel BayTrail SoC)
 PCI: 00:1d.0 (Intel BayTrail SoC)
 PCI: 00:1e.0 (Intel BayTrail SoC)
 PCI: 00:1e.1 (Intel BayTrail SoC)
 PCI: 00:1e.2 (Intel BayTrail SoC)
 PCI: 00:1e.3 (Intel BayTrail SoC)
 PCI: 00:1e.4 (Intel BayTrail SoC)
 PCI: 00:1e.5 (Intel BayTrail SoC)
 PCI: 00:1f.0 (Intel BayTrail SoC)
 PCI: 00:1f.3 (Intel BayTrail SoC)
 PCI: 02:00.0 (unknown)
 APIC: 04 (unknown)
 SMBIOS tables: 352 bytes.
 POST: 0x9e
 POST: 0x9d
 Writing table forward entry at 0x00000500
 Wrote coreboot table at: 00000500, 0x10 bytes, checksum b512
 Table forward entry ends at 0x00000528.
 ... aligned to 0x00001000
 Writing coreboot table at 0x7acbd000
 rom_table_end = 0x7acbd000
 ... aligned to 0x7acc0000
  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1. 0000000000001000-000000000009ffff: RAM
  2. 00000000000a0000-00000000000fffff: RESERVED
  3. 0000000000100000-000000007acbcfff: RAM
  4. 000000007acbd000-000000007adfffff: CONFIGURATION TABLES
  5. 000000007ae00000-000000007fffffff: RESERVED
  6. 00000000e0000000-00000000efffffff: RESERVED
  7. 00000000feb00000-00000000fec00fff: RESERVED
  8. 00000000fed01000-00000000fed01fff: RESERVED
  9. 00000000fed03000-00000000fed03fff: RESERVED
 10. 00000000fed05000-00000000fed05fff: RESERVED
 11. 00000000fed08000-00000000fed08fff: RESERVED
 12. 00000000fed0c000-00000000fed0ffff: RESERVED
 13. 00000000fed1c000-00000000fed1cfff: RESERVED
 14. 00000000fee00000-00000000fee00fff: RESERVED
 15. 00000000fef00000-00000000feffffff: RESERVED
 16. 00000000ff800000-00000000ffffffff: RESERVED
 Wrote coreboot table at: 7acbd000, 0x23c bytes, checksum 438f
 coreboot table: 596 bytes.
 IMD ROOT    0. 7adff000 00001000
 IMD SMALL   1. 7adfe000 00001000
 ACPI GNVS   2. 7adfc000 00002000
 ACPI RESUME 3. 7acfc000 00100000
 MRC DATA    4. 7acfa000 00001690
 ACPI        5. 7acd6000 00024000
 54435041    6. 7acc6000 00010000
 SMBIOS      7. 7acc5000 00000800
 COREBOOT    8. 7acbd000 00008000
 IMD small region:
   IMD ROOT    0. 7adfec00 00000400
   484f4221    1. 7adfebe0 00000001
   ROMSTAGE    2. 7adfebc0 00000004
   GDT         3. 7adfe9c0 00000200
   GNVS PTR    4. 7adfe9a0 00000004
 BS: BS_WRITE_TABLES times (us): entry 3083867 run 458387 exit 0
 POST: 0x7a
 CBFS provider active.
 CBFS @ 500000 size 2ffb80
 CBFS: Locating 'fallback/payload'
 CBFS: Found @ offset 27c40 size a3a58
 'fallback/payload' located at offset: 527c78 size: a3a58
 Loading segment from rom address 0xffd27c78
   code (compression=1)
   New segment dstaddr 0x800000 memsize 0x400000 srcaddr 0xffd27cb0 filesize 0xa3a20
 Loading segment from rom address 0xffd27c94
   Entry Point 0x008007c0
 Bounce Buffer at 7ac4e000, 454616 bytes
 Loading Segment: addr: 0x0000000000800000 memsz: 0x0000000000400000 filesz: 0x00000000000a3a20
 lb: [0x0000000000100000, 0x00000000001377ec)
 Post relocation: addr: 0x0000000000800000 memsz: 0x0000000000400000 filesz: 0x00000000000a3a20
 using LZMA
 [ 0x00800000, 00c00000, 0x00c00000) <- ffd27cb0
 dest 00800000, end 00c00000, bouncebuffer 7ac4e000
 Loaded segments
 BS: BS_PAYLOAD_LOAD times (us): entry 0 run 573362 exit 0
 FspNotify(EnumInitPhaseReadyToBoot)
 fsp_header_ptr: fffc0094
 FSP Header Version: 1
 FSP Revision: 3.3
 Returned from FspNotify(EnumInitPhaseReadyToBoot)
 POST: 0x7b
 Jumping to boot code at 008007c0(7acbd000)
 POST: 0xf8
 CPU0: stack: 0012e000 - 0012f000, lowest used address 0012eb7c, stack used: 1156 bytes
 entry    = 0x008007c0
 lb_start = 0x00100000
 lb_size  = 0x000377ec
 buffer   = 0x7ac4e000
 PROGRESS CODE: V03020003 I0
 Loading PEIM at 0x0000080ED20 EntryPoint=0x0000080EF80 CbSupportPeim.efi
 PROGRESS CODE: V03020002 I0
 0. 0000000000000000 - 0000000000000FFF [10]
 1. 0000000000001000 - 000000000009FFFF [01]
 2. 00000000000A0000 - 00000000000FFFFF [02]
 3. 0000000000100000 - 000000007ACBCFFF [01]
 4. 000000007ACBD000 - 000000007ADFFFFF [10]
 5. 000000007AE00000 - 000000007FFFFFFF [02]
 6. 00000000E0000000 - 00000000EFFFFFFF [02]
 7. 00000000FEB00000 - 00000000FEC00FFF [02]
 8. 00000000FED01000 - 00000000FED01FFF [02]
 9. 00000000FED03000 - 00000000FED03FFF [02]
 10. 00000000FED05000 - 00000000FED05FFF [02]
 11. 00000000FED08000 - 00000000FED08FFF [02]
 12. 00000000FED0C000 - 00000000FED0FFFF [02]
 13. 00000000FED1C000 - 00000000FED1CFFF [02]
 14. 00000000FEE00000 - 00000000FEE00FFF [02]
 15. 00000000FEF00000 - 00000000FEFFFFFF [02]
 16. 00000000FF800000 - 00000000FFFFFFFF [02]
 Low memory 0x7ACBD000, High Memory 0x0
 LowMemorySize: 0x7ACBD000.
 HighMemorySize: 0x0.
 PeiMemBase: 0x76CB0000.
 PeiMemSize: 0x4000000.
 PeiInstallPeiMemory MemoryBegin 0x76CB0000, MemoryLength 0x4000000
 Found one valid fv : 0x820000.
 Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 801BC0
 The 1th FV start address is 0x00000820000, size is 0x003E0000, handle is 0x820000
 Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410
 Actual Coreboot header: 0x7ACBD000.
 Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x24000
 Find CbMemTable Id 0x534D4254, base 7ACC5000, size 0x800
 Detected Acpi Table at 0x7ACD6000, length 0x24000
 Detected Smbios Table at 0x7ACC5000, length 0x800
 Create system table info guid hob
 Find CbMemTable Id 0x41435049, base 7ACD6000, size 0x6BE0505D
 Find Rsdp at 7ACD6000
 Find Rsdt 0x7ACD6030, Xsdt 0x7ACD60E0
 PmCtrl Reg 0x404
 PmTimer Reg 0x408
 Reset Reg 0xCF9
 Reset Value 0x6
 PmEvt Reg 0x400
 PmGpeEn Reg 0x424
 Create acpi board info guid hob
 PROGRESS CODE: V03020003 I0
 Temp Stack : BaseAddress=0x88000 Length=0x8000
 Temp Heap  : BaseAddress=0x80000 Length=0xCF0
 Total temporary memory:    65536 bytes.
   temporary memory stack ever used: 32768 bytes.
   temporary memory heap used:       3312 bytes.
 Old Stack size 32768, New stack size 131072
 Stack Hob: BaseAddress=0x76CB0000 Length=0x20000
 Heap Offset = 0x76C50000 Stack Offset = 0x76C40000
 Loading PEIM at 0x0007ACA6000 EntryPoint=0x0007ACA6260 PeiCore.efi
 Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
 Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE
 Loading PEIM at 0x0007ACA2000 EntryPoint=0x0007ACA2260 DxeIpl.efi
 PROGRESS CODE: V03020002 I0
 PROGRESS CODE: V03020003 I0
 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731
 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7
 DXE IPL Entry
 Loading PEIM at 0x0007AC80000 EntryPoint=0x0007AC802C0 DxeCore.efi
 PROGRESS CODE: V03021001 I0
 Loading DXE CORE at 0x0007AC80000 EntryPoint=0x0007AC802C0
 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6
 PROGRESS CODE: V03040003 I0
 Loading driver F80697E9-7FD6-4665-8646-88E33EF71DFC
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99FA40
 Loading driver at 0x0007A996000 EntryPoint=0x0007A9962C0 SecurityStubDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9A5798
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 94AB2F58-1438-4EF1-9152-18941A3A0E68 7A998178
 InstallProtocolInterface: A46423E3-4617-49F1-B9FF-D1BFA9115839 7A998170
 PROGRESS CODE: V03040003 I0
 Loading driver 1A1E4886-9517-440E-9FDE-3BE44CEE2136
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99F840
 Loading driver at 0x0007A986000 EntryPoint=0x0007A9862C0 CpuDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9A5418
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 26BACCB1-6F42-11D4-BCE7-0080C73C8881 7A98D0A0
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
   Flushing GCD
 PROGRESS CODE: V03040003 I0
 Loading driver C8339973-A563-4561-B858-D8476F9DEFC4
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99F640
 Loading driver at 0x0007A984000 EntryPoint=0x0007A9842C0 Metronome.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A9A5098
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 26BACCB2-6F42-11D4-BCE7-0080C73C8881 7A9858F0
 PROGRESS CODE: V03040003 I0
 Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99F440
 Loading driver at 0x0007AB84000 EntryPoint=0x0007AB842C0 RuntimeDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98FD18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: B7DFB4E1-052F-449F-87BE-9818FC91B733 7AB85FA0
 PROGRESS CODE: V03040003 I0
 Loading driver 4B28E4C7-FF36-4E10-93CF-A82159E777C5
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99F240
 Loading driver at 0x0007AB81000 EntryPoint=0x0007AB812C0 ResetSystemRuntimeDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98F998
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 27CFAC88-46CC-11D4-9A38-0090273FC14D 0
 PROGRESS CODE: V03040003 I0
 Loading driver 02B01AD5-7E59-43E8-A6D8-238180613A5A
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A99F040
 Loading driver at 0x0007AB7C000 EntryPoint=0x0007AB7C2C0 EmuVariableRuntimeDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98F618
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 1E5668E2-8481-11D4-BCF1-0080C73C8881 0
 InstallProtocolInterface: 6441F818-6362-4E44-B570-7DBA31DD2453 0
 PROGRESS CODE: V03040003 I0
 Loading driver A19B1FE7-C1BC-49F8-875F-54A5D542443F
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980E40
 Loading driver at 0x0007A97E000 EntryPoint=0x0007A97E2C0 CpuIo2Dxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A98F298
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: AD61F191-AE5F-4C0E-B9FA-E869D288C64F 7A97FB10
 PROGRESS CODE: V03040003 I0
 Loading driver 9B680FCE-AD6B-4F3A-B60B-F59899003443
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980C40
 Loading driver at 0x0007A968000 EntryPoint=0x0007A9682C0 DevicePathDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A982E98
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 0379BE4E-D706-437D-B037-EDB82FB772A4 7A96F140
 InstallProtocolInterface: 8B843E20-8132-4852-90CC-551A4E4A7F1C 7A96F180
 InstallProtocolInterface: 05C99A21-C70F-4AD2-8A5F-35DF3343F51E 7A96F190
 PROGRESS CODE: V03040003 I0
 Loading driver 96B5C032-DF4C-4B6E-8232-438DCF448D0E
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980A40
 Loading driver at 0x0007A97A000 EntryPoint=0x0007A97A2C0 NullMemoryTestDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A982998
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 309DE7F1-7F5E-4ACE-B49C-531BE5AA95EF 7A97B7E0
 PROGRESS CODE: V03040003 I0
 Loading driver 79CA4208-BBA1-4A9A-8456-E1E66A81484E
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980840
 Loading driver at 0x0007A978000 EntryPoint=0x0007A9782C0 Legacy8259.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A982598
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 38321DBA-4FE0-4E17-8AEC-413055EAEDC1 7A9796E0
 PROGRESS CODE: V03040003 I0
 Loading driver 348C4D62-BFBD-4882-9ECE-C80BB1C4783B
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980640
 Loading driver at 0x0007A93A000 EntryPoint=0x0007A93A2C0 HiiDatabase.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A982198
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: E9CA4775-8657-47FC-97E7-7ED65A084324 7A94F718
 InstallProtocolInterface: 0FD96974-23AA-4CDC-B9CB-98D17750322A 7A94F760
 InstallProtocolInterface: EF9FC172-A1B2-4693-B327-6D32FC416042 7A94F788
 InstallProtocolInterface: 587E72D7-CC50-4F79-8209-CA291FC1A10F 7A94F7E0
 InstallProtocolInterface: 31A6406A-6BDF-4E46-B2A2-EBAA89C40920 7A94F738
 PROGRESS CODE: V03040003 I0
 Loading driver C68DAA4E-7AB5-41E8-A91D-5954421053F3
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980440
 Loading driver at 0x0007A965000 EntryPoint=0x0007A9652C0 CbSupportDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97DB98
 PROGRESS CODE: V03040002 I0
 Install Acpi Table at 0x7ACD6000, length 0x24000
 Install Smbios Table at 0x7ACC5000, length 0x800
 PmCtrlReg at 0x404
 PROGRESS CODE: V03040003 I0
 Loading driver F9D88642-0737-49BC-81B5-6889CD57D9EA
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980240
 Loading driver at 0x0007A962000 EntryPoint=0x0007A9622C0 SmbiosDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97D618
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 03583FF6-CB36-4940-947E-B9B39F4AFAF7 7A964B90
 PROGRESS CODE: V03040003 I0
 Loading driver D3987D4B-971A-435F-8CAF-4967EB627241
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A980040
 Loading driver at 0x0007A974000 EntryPoint=0x0007A9742C0 SerialDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A97D218
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD 7A975B70
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A975B20
 PROGRESS CODE: V03040003 I0
 Loading driver FC5C7020-1A48-4198-9BE2-EAD5ABC8CF2F
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976E40
 Loading driver at 0x0007A8E0000 EntryPoint=0x0007A8E02C0 BdsDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A977D18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 665E3FF6-46CC-11D4-9A38-0090273FC14D 7A906A38
 PROGRESS CODE: V03040003 I0
 Loading driver F2765DEC-6B41-11D5-8E71-00902707B35E
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976C40
 Loading driver at 0x0007A95E000 EntryPoint=0x0007A95E2C0 Timer.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A977698
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 26BACCB3-6F42-11D4-BCE7-0080C73C8881 7A95F630
 PROGRESS CODE: V03040003 I0
 Loading driver 42857F0A-13F2-4B21-8A23-53D3F714B840
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976A40
 Loading driver at 0x0007AB7A000 EntryPoint=0x0007AB7A2C0 CapsuleRuntimeDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A977318
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 5053697E-2CBC-4819-90D9-0580DEEE5754 0
 PROGRESS CODE: V03040003 I0
 Loading driver AD608272-D07F-4964-801E-7BD3B7888652
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976840
 Loading driver at 0x0007AB78000 EntryPoint=0x0007AB782C0 MonotonicCounterRuntimeDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95DF98
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 1DA97072-BDDC-4B30-99F1-72A0B56FFF2A 0
 PROGRESS CODE: V03040003 I0
 Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976640
 Loading driver at 0x0007AB74000 EntryPoint=0x0007AB742C0 PcRtc.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95DC18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 27CFAC87-46CC-11D4-9A38-0090273FC14D 0
 PROGRESS CODE: V03040003 I0
 Loading driver EBF342FE-B1D3-4EF8-957C-8048606FF671
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976440
 Loading driver at 0x0007A8C8000 EntryPoint=0x0007A8C82C0 SetupBrowser.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95D898
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: B9D4C360-BCFB-4F9B-9298-53C136982258 7A8DDFB0
 InstallProtocolInterface: A770C357-B693-4E6D-A6CF-D21C728E550B 7A8DDFE0
 InstallProtocolInterface: 1F73B18D-4630-43C1-A1DE-6F80855D7DA4 7A8DDFC0
 PROGRESS CODE: V03040003 I0
 Loading driver 2383608E-C6D0-4E3E-858D-45DFAC3543D5
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976240
 Loading driver at 0x0007A953000 EntryPoint=0x0007A9532C0 PciHostBridge.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95D218
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: CF8034BE-6768-4D8B-B739-7CCE683A9FBE 7A960D48
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A9575B8
 InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7A95CE08
 PROGRESS CODE: V03040003 I0
 Loading driver F099D67F-71AE-4C36-B2A3-DCEB0EB2B7D8
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A976040
 Loading driver at 0x0007A951000 EntryPoint=0x0007A9512C0 WatchdogTimer.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95BC98
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 665E3FF5-46CC-11D4-9A38-0090273FC14D 7A9524F0
 PROGRESS CODE: V03040003 I0
 Loading driver E660EA85-058E-4B55-A54B-F02F83A24707
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95AE40
 Loading driver at 0x0007A914000 EntryPoint=0x0007A914314 DisplayEngine.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A95B898
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 9BBE29E9-FDA1-41EC-AD52-452213742D2E 7A9249B0
 PROGRESS CODE: V03040003 I0
 Loading driver 35C0C168-2607-4E51-BB53-448E3ED1A87F
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95AC40
 Loading driver at 0x0007A8C0000 EntryPoint=0x0007A8C02C0 PciBusNoEnumerationDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A937398
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8C6E70
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8C6EA8
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8C6EC0
 PROGRESS CODE: V03040003 I0
 Loading driver 51CCF399-4FDF-4E55-A45B-E123F84D456A
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95AA40
 Loading driver at 0x0007A92D000 EntryPoint=0x0007A92D2C0 ConPlatformDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A92CF18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A92FD20
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A92FD80
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A92FD98
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A92FD50
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A92FD80
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A92FD98
 PROGRESS CODE: V03040003 I0
 Loading driver 408EDCEC-CF6D-477C-A5A8-B4844E3DE281
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95A840
 Loading driver at 0x0007A8B0000 EntryPoint=0x0007A8B02C0 ConSplitterDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A92CA98
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8B6228
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8B66C8
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8B66E0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8B62B8
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8B66F8
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8B6710
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8B62E8
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8B6728
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8B6740
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8B6258
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8B6758
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8B6770
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8B6288
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8B6788
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8B67A0
 InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7A8B6330
 InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7A8B6360
 InstallProtocolInterface: 31878C87-0B75-11D5-9A4F-0090273FC14D 7A8B63B8
 InstallProtocolInterface: 8D59D32B-C655-4AE9-9B15-F25904992A43 7A8B6410
 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A8B64C0
 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7A8B65D0
 PROGRESS CODE: V03040003 I0
 Loading driver CCCB0C28-4B24-11D5-9A5A-0090273FC14D
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95A640
 Loading driver at 0x0007A8BA000 EntryPoint=0x0007A8BA2C0 GraphicsConsoleDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A932C98
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8BF200
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8BF238
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8BF250
 PROGRESS CODE: V03040003 I0
 Loading driver 9E863906-A40F-4875-977F-5B93FF237FC6
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95A440
 Loading driver at 0x0007A8A0000 EntryPoint=0x0007A8A02C0 TerminalDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A932818
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8A6A88
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8A6C28
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8A6C40
 PROGRESS CODE: V03040003 I0
 Loading driver 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95A240
 Loading driver at 0x0007A90D000 EntryPoint=0x0007A90D2C0 DiskIoDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A932518
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A911770
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A911828
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A911840
 PROGRESS CODE: V03040003 I0
 Loading driver 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A95A040
 Loading driver at 0x0007A89A000 EntryPoint=0x0007A89A2C0 PartitionDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A932218
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A89EE90
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A89EEE0
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A89EEF8
 PROGRESS CODE: V03040003 I0
 Loading driver CD3BAFB6-50FB-4FE8-8E4E-AB74D2C1A600
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928E40
 Loading driver at 0x0007A8B8000 EntryPoint=0x0007A8B82C0 EnglishDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A927F18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 1D85CD7F-F43D-11D2-9A0C-0090273FC14D 7A8B9700
 InstallProtocolInterface: A4C751FC-23AE-4C3E-92E9-4964CF63F349 7A8B9738
 PROGRESS CODE: V03040003 I0
 Loading driver 8F4CD826-A5A0-4E93-9522-CFB0AB72926C
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928C40
 Loading driver at 0x0007A8AA000 EntryPoint=0x0007A8AA2C0 SataController.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A927B18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8AC670
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8AC6A0
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8AC6B8
 PROGRESS CODE: V03040003 I0
 Loading driver 19DF145A-B1D4-453F-8507-38816676D7F6
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928A40
 Loading driver at 0x0007A88C000 EntryPoint=0x0007A88C2C0 AtaBusDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A927818
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A891E70
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8920C0
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A8920D8
 AtaBus:gEfiMemoryOverwriteControlDataGuid doesn't exist!!***
 PROGRESS CODE: V03040003 I0
 Loading driver 5E523CB4-D397-4986-87BD-A6DD8B22F455
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928840
 Loading driver at 0x0007A876000 EntryPoint=0x0007A8762C0 AtaAtapiPassThruDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A927518
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A87F660
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A87F8A0
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A87F8B8
 PROGRESS CODE: V03040003 I0
 Loading driver 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928640
 Loading driver at 0x0007A888000 EntryPoint=0x0007A8882C0 ScsiBus.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A927218
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A88B470
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A88B4A0
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A88B4B8
 PROGRESS CODE: V03040003 I0
 Loading driver 0A66E322-3740-4CCE-AD62-BD172CECCA35
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928440
 Loading driver at 0x0007A881000 EntryPoint=0x0007A8812C0 ScsiDisk.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929F18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A886DB0
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A886E10
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A886E28
 PROGRESS CODE: V03040003 I0
 Loading driver 961578FE-B6B7-44C3-AF35-6BC705CD2B1F
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928240
 Loading driver at 0x0007A86F000 EntryPoint=0x0007A86F56C 
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929C18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A86F360
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A86F438
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A86F450
 PROGRESS CODE: V03040003 I0
 Loading driver 2FB92EFA-2EE0-4BAE-9EB6-7464125E1EF7
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A928040
 Loading driver at 0x0007A868000 EntryPoint=0x0007A8682C0 UhciDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929918
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A86E830
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A86E860
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A86E878
 PROGRESS CODE: V03040003 I0
 Loading driver BDFE430E-8F2A-4DB0-9991-6F856594777E
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AEE40
 Loading driver at 0x0007A856000 EntryPoint=0x0007A8562C0 EhciDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929618
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A85DE00
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A85DE30
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A85DE48
 PROGRESS CODE: V03040003 I0
 Loading driver B7F50E91-A759-412C-ADE4-DCD03E7F7C28
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AEC40
 Loading driver at 0x0007A83C000 EntryPoint=0x0007A83C2C0 XhciDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929318
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A847658
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A847700
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A847718
 PROGRESS CODE: V03040003 I0
 Loading driver 240612B7-A063-11D4-9A3A-0090273FC14D
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AEA40
 Loading driver at 0x0007A832000 EntryPoint=0x0007A8322C0 UsbBusDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A929018
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A83A948
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A83A978
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A83A990
 PROGRESS CODE: V03040003 I0
 Loading driver 2D2E62CF-9ECF-43B7-8219-94E7FC713DFE
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AE840
 Loading driver at 0x0007A861000 EntryPoint=0x0007A8612C0 UsbKbDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8A9D18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A866A20
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A866A50
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A866A68
 PROGRESS CODE: V03040003 I0
 Loading driver 9FB4B4A7-42C0-4BCD-8540-9BCC6711F83E
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AE640
 Loading driver at 0x0007A850000 EntryPoint=0x0007A8502C0 UsbMassStorageDxe.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8A9A18
 PROGRESS CODE: V03040002 I0
 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7A8556C8
 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7A8556F8
 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7A855710
 PROGRESS CODE: V03040003 I0
 Loading driver 0B04B2ED-861C-42CD-A22F-C3AAFACCB896
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AE440
 Loading driver at 0x0007A84C000 EntryPoint=0x0007A84C2C0 FbGop.efi
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A8A9718
 PROGRESS CODE: V03040002 I0
 No FrameBuffer information from coreboot.  NO GOP driver !!!
 Error: Image at 0007A84C000 start failed: Aborted
 PROGRESS CODE: V03040003 I0
 PROGRESS CODE: V03041001 I0
 [BdsDxe] Locate Variable Lock protocol - Not Found
 PROGRESS CODE: V03051005 I0
 Variable Driver Auto Update Lang, Lang:eng, PlatformLang:en
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A905A10
 InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A9059B8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A905A28
 InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A9059D0
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A905A80
 InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A905AB0
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A906A20
 InstallProtocolInterface: 330D4706-F2A0-4E4F-A369-B66FA8D54385 7A905AE8
 PlatformBdsPolicyBehavior
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849A98
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A95C2A8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849A18
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A95C528
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849F98
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A831CA8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A899118
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A831A28
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849918
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8317A8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849898
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A831528
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849818
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8312A8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849798
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A831028
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849718
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A830CA8
 PciExp - 1 (B-0, D-1C, F-0)
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849698
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A830A28
 PciExp - 1 (B-0, D-1C, F-2)
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849618
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8307A8
 PciExp - 1 (B-2, D-0, F-0)
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849598
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A830528
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849518
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A8302A8
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A849498
 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7A830028
 PlatformBdsGetDriverOption
 Boot Mode:0
 Found PCI VGA device
 Found LPC Bridge device
 BdsPlatform.c+140: COM1 DevPath: VenHw(BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD)/Uart(115200,8,N,1)/VenPcAnsi()
 InstallProtocolInterface: 9E863906-A40F-4875-977F-5B93FF237FC6 7A82D198
 Terminal - Mode 0, Column = 80, Row = 25
 Terminal - Mode 1, Column = 80, Row = 50
 Terminal - Mode 2, Column = 100, Row = 31
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A82AD18
 PROGRESS CODE: V01040001 I0
 [=3h[=3hInstallProtocolInterface:  387477C1-69C7-11D2-8E39-00A0C969723B 7AB09C40
 InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7AB09D10
 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7AB09C58
 InstallProtocolInterface: D3B36F2C-D551-11D4-9A46-0090273FC14D 0
 InstallProtocolInterface: D3B36F2D-D551-11D4-9A46-0090273FC14D 0
 [=3h[=3hInstallProtocolInterface:  D3B36F2B-D551-11D4-9A46-0090273FC14D 0
 PlatformBdsDiagnostics
 PlatformBdsConnectSequence
 SataControllerStart START
 InstallProtocolInterface: A1E37052-80D9-4E65-A317-3E9A55C43EC9 7A82C820
 SataControllerStart END status = Success
 ==AtaAtapiPassThru Start== Controller = 7A82FE18
 InstallProtocolInterface: 1D3DE7F0-0807-424F-AA69-11A54E19A46F 7A8AE440
 InstallProtocolInterface: 143B7632-B81B-4CB7-ABD3-B625A5B9BFFE 7A8AE490
 PROGRESS CODE: V02080000 I0
 InstallProtocolInterface: 19DF145A-B1D4-453F-8507-38816676D7F6 7A825118
 PROGRESS CODE: V02080003 I0
 PROGRESS CODE: V02070000 I0
 InstallProtocolInterface: 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B 7A820F20
 PROGRESS CODE: V02070003 I0
 EhcCreateUsb2Hc: capability length 32
 InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC 7AB09020
 EhcDriverBindingStart: EHCI started for controller @ 7A82F398
 PROGRESS CODE: V02020000 I0
 PROGRESS CODE: V02020004 I0
 PROGRESS CODE: V02020001 I0
 EhcReset: exit status Success
 EhcGetState: current state 1
 InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D 7A80A020
 PROGRESS CODE: V02020003 I0
 EhcGetCapability: 8 ports, 64 bit 1
 UsbRootHubInit: root hub 7A809F18 - max speed 2, 8 ports
 UsbEnumeratePort: port 0 state - 101, change - 01 on 7A809F18
 UsbEnumeratePort: Device Connect/Disconnect Normally
 UsbEnumeratePort: new device connected at port 0
 EhcSetRootHubPortFeature: exit status Success
 EhcClearRootHubPortFeature: exit status Success
 UsbEnumerateNewDev: hub port 0 is reset
 UsbEnumerateNewDev: device is of 2 speed
 UsbEnumerateNewDev: device uses translator (0, 0)
 UsbEnumerateNewDev: device is now ADDRESSED at 1
 UsbEnumerateNewDev: max packet size for EP 0 is 64
 UsbBuildDescTable: device has 1 configures
 UsbGetOneConfig: total length is 25
 UsbParseConfigDesc: config 1 has 1 interfaces
 UsbParseInterfaceDesc: interface 0(setting 0) has 1 endpoints
 EhcExecTransfer: transfer failed with 2
 EhcControlTransfer: error - Device Error, transfer - 2
 UsbBuildDescTable: get language ID table Unsupported
 UsbEnumerateNewDev: device 1 is now in CONFIGED state
 UsbSelectConfig: config 1 selected for device 1
 UsbSelectSetting: setting 0 selected for interface 0
 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7A80B698
 InstallProtocolInterface: 2B2F68D6-0CD2-44CF-8E8B-BBA20B1B5B75 7A821640
 UsbConnectDriver: found a hub device
 UsbHubInit: hub 1 has 4 ports
 UsbHubInit: hub 1 initialized
 PROGRESS CODE: V02020006 I0
 EhcClearRootHubPortFeature: exit status Success
 UsbBusStart: usb bus started on 7A82F398, root hub 7A809F18
 PROGRESS CODE: V02080000 I0
 PROGRESS CODE: V02080003 I0
 SataControllerStart START
 SataControllerStart error return status = Already started
 PROGRESS CODE: V02070000 I0
 PROGRESS CODE: V02070003 I0
 PROGRESS CODE: V02020000 I0
 UsbConnectDriver: TPL before connect is 4
 UsbConnectDriver: TPL after connect is 4
 PROGRESS CODE: V03051001 I0
 Enable SCI bit at 0x404 before boot
 Memory  Previous  Current    Next   
  Type    Pages     Pages     Pages  
 ======  ========  ========  ========
   09    00000008  00000000  00000008
   0A    00000004  00000000  00000004
   00    00000004  00000000  00000004
   06    00000080  00000028  00000080
   05    00000080  00000018  00000080
 Booting EFI Internal Shell
 PROGRESS CODE: V03058000 I0
 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7A8AE240
 Loading driver at 0x0007A4C8000 EntryPoint=0x0007A52D8C4 
 InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7A806F18
 PROGRESS CODE: V03058001 I0
 InstallProtocolInterface: 47C7B221-C42A-11D2-8E57-00A0C969723B 7A4D0020
 InstallProtocolInterface: 47C7B223-C42A-11D2-8E57-00A0C969723B 7A63DE18
 EFI Shell version 2.40 [1.0]
 Current running mode: Cannot find required map name.
 Shell> pci
    Seg  Bus  Dev  Func
    ---  ---  ---  ----
 00   00   00    00 ==> Bridge Device - Host/PCI bridge
              Vendor 8086 Device 0F00 Prog Interface 0
 00   00   02    00 ==> Display Controller - VGA/8514 controller
              Vendor 8086 Device 0F31 Prog Interface 0
 00   00   11    00 ==> Base System Peripherals - UNDEFINED
              Vendor 8086 Device 0F15 Prog Interface 1
 00   00   12    00 ==> Base System Peripherals - UNDEFINED
              Vendor 8086 Device 0F16 Prog Interface 1
 00   00   13    00 ==> Mass Storage Controller - UNDEFINED
              Vendor 8086 Device 0F23 Prog Interface 1
 00   00   15    00 ==> Multimedia Device - Audio device
              Vendor 8086 Device 0F28 Prog Interface 0
 00   00   17    00 ==> Base System Peripherals - UNDEFINED
              Vendor 8086 Device 0F50 Prog Interface 1
 00   00   1A    00 ==> Encryption/Decryption Controllers - Other Encrypt/Dec
              Vendor 8086 Device 0F18 Prog Interface 0
 00   00   1C    00 ==> Bridge Device - PCI/PCI bridge
              Vendor 8086 Device 0F48 Prog Interface 0
 00   00   1C    02 ==> Bridge Device - PCI/PCI bridge
              Vendor 8086 Device 0F4C Prog Interface 0
 00   00   1D    00 ==> Serial Bus Controllers - USB
              Vendor 8086 Device 0F34 Prog Interface 20
 00   00   1F    00 ==> Bridge Device - PCI/ISA bridge
              Vendor 8086 Device 0F1C Prog Interface 0
 00   00   1F    03 ==> Serial Bus Controllers - System Management Bus
              Vendor 8086 Device 0F12 Prog Interface 0
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150716/6fd18b61/attachment-0001.html>

From rminnich at gmail.com  Fri Jul 17 21:45:37 2015
From: rminnich at gmail.com (ron minnich)
Date: Fri, 17 Jul 2015 19:45:37 +0000
Subject: [coreboot] cbfs alignment
Message-ID: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>

riscv is taking alignment traps reading cbfs.

The issue is that 64-bit fields are 32-bit aligned, which fails many places.

Thaminda found this comment:

  * Since coreboot is usually compiled 32bit, gcc will align 64bit
 * types to 32bit boundaries. If the coreboot table is dumped on a
 * 64bit system, a uint64_t would be aligned to 64bit boundaries,
 * breaking the table format.

this is a real problem. Would have broken badly on Alpha, and breaks badly
on RISCV.

We can fix it, with an ugly macro, but ... what's the right move here?

ron
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150717/30f47cba/attachment.html>

From adurbin at google.com  Fri Jul 17 22:23:48 2015
From: adurbin at google.com (Aaron Durbin)
Date: Fri, 17 Jul 2015 15:23:48 -0500
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
Message-ID: <CAE2855tWfHTsgmGJ=mL6Jw-qVBPEyZ5cJpS2r=zQibNYtcPC_w@mail.gmail.com>

On Fri, Jul 17, 2015 at 2:45 PM, ron minnich <rminnich at gmail.com> wrote:
> riscv is taking alignment traps reading cbfs.
>
> The issue is that 64-bit fields are 32-bit aligned, which fails many places.
>
> Thaminda found this comment:
>
>   * Since coreboot is usually compiled 32bit, gcc will align 64bit
>  * types to 32bit boundaries. If the coreboot table is dumped on a
>  * 64bit system, a uint64_t would be aligned to 64bit boundaries,
>  * breaking the table format.
>
> this is a real problem. Would have broken badly on Alpha, and breaks badly
> on RISCV.
>
> We can fix it, with an ugly macro, but ... what's the right move here?

You mean how none of the structs in src/include/boot/coreboot_tables.h
have a packed attribute decorated on them? And they should be marked
packed since these are a serialized format. That's not really going to
help you.

One thing you do is break up all uint64_t in that header to be a
struct of 2 uint32_t -- which is what lb_uint64 was for I assume. What
that means is the types all need to be marshalled properly, and you'd
have to do this as it is if RISC V doesn't support unaligned accesses.

In general, coreboot has been largely written to assume unaligned
accesses are no big deal (thanks, x86!). Because of this architectures
like ARM *have* to get their MMUs up to enable normal memory so that
it can honor the "handle unaligned accesses".

>
> ron
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From rminnich at gmail.com  Fri Jul 17 22:27:25 2015
From: rminnich at gmail.com (ron minnich)
Date: Fri, 17 Jul 2015 20:27:25 +0000
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAE2855tWfHTsgmGJ=mL6Jw-qVBPEyZ5cJpS2r=zQibNYtcPC_w@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAE2855tWfHTsgmGJ=mL6Jw-qVBPEyZ5cJpS2r=zQibNYtcPC_w@mail.gmail.com>
Message-ID: <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>

bummer. We're going to have to add marshalling code to cbfs, to copy
pointers from the architecture we're on to the architecture we're on, which
was compiled by gcc for the architecture we're on, compiled on the
architecture we're not on, to conform to rules for an architecture we're
not on.

goodbye, a = b
hello, memcpy(&a, &b, sizeof(a));
barf.

ron

On Fri, Jul 17, 2015 at 1:23 PM Aaron Durbin <adurbin at google.com> wrote:

> On Fri, Jul 17, 2015 at 2:45 PM, ron minnich <rminnich at gmail.com> wrote:
> > riscv is taking alignment traps reading cbfs.
> >
> > The issue is that 64-bit fields are 32-bit aligned, which fails many
> places.
> >
> > Thaminda found this comment:
> >
> >   * Since coreboot is usually compiled 32bit, gcc will align 64bit
> >  * types to 32bit boundaries. If the coreboot table is dumped on a
> >  * 64bit system, a uint64_t would be aligned to 64bit boundaries,
> >  * breaking the table format.
> >
> > this is a real problem. Would have broken badly on Alpha, and breaks
> badly
> > on RISCV.
> >
> > We can fix it, with an ugly macro, but ... what's the right move here?
>
> You mean how none of the structs in src/include/boot/coreboot_tables.h
> have a packed attribute decorated on them? And they should be marked
> packed since these are a serialized format. That's not really going to
> help you.
>
> One thing you do is break up all uint64_t in that header to be a
> struct of 2 uint32_t -- which is what lb_uint64 was for I assume. What
> that means is the types all need to be marshalled properly, and you'd
> have to do this as it is if RISC V doesn't support unaligned accesses.
>
> In general, coreboot has been largely written to assume unaligned
> accesses are no big deal (thanks, x86!). Because of this architectures
> like ARM *have* to get their MMUs up to enable normal memory so that
> it can honor the "handle unaligned accesses".
>
> >
> > ron
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150717/6fe83ee2/attachment.html>

From adurbin at google.com  Fri Jul 17 22:32:43 2015
From: adurbin at google.com (Aaron Durbin)
Date: Fri, 17 Jul 2015 15:32:43 -0500
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAE2855tWfHTsgmGJ=mL6Jw-qVBPEyZ5cJpS2r=zQibNYtcPC_w@mail.gmail.com>
 <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
Message-ID: <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>

On Fri, Jul 17, 2015 at 3:27 PM, ron minnich <rminnich at gmail.com> wrote:
> bummer. We're going to have to add marshalling code to cbfs, to copy


Ya. You'd need to fix cbfs as well is my guess.

> pointers from the architecture we're on to the architecture we're on, which
> was compiled by gcc for the architecture we're on, compiled on the
> architecture we're not on, to conform to rules for an architecture we're not
> on.
>
> goodbye, a = b
> hello, memcpy(&a, &b, sizeof(a));
> barf.

Ya. And since this is C it makes for some really annoying work. Now if
you write a spec that can be processed by a machine for all these
serialized structs we could generate code based on the CPU's
constraints.


>
> ron
>
> On Fri, Jul 17, 2015 at 1:23 PM Aaron Durbin <adurbin at google.com> wrote:
>>
>> On Fri, Jul 17, 2015 at 2:45 PM, ron minnich <rminnich at gmail.com> wrote:
>> > riscv is taking alignment traps reading cbfs.
>> >
>> > The issue is that 64-bit fields are 32-bit aligned, which fails many
>> > places.
>> >
>> > Thaminda found this comment:
>> >
>> >   * Since coreboot is usually compiled 32bit, gcc will align 64bit
>> >  * types to 32bit boundaries. If the coreboot table is dumped on a
>> >  * 64bit system, a uint64_t would be aligned to 64bit boundaries,
>> >  * breaking the table format.
>> >
>> > this is a real problem. Would have broken badly on Alpha, and breaks
>> > badly
>> > on RISCV.
>> >
>> > We can fix it, with an ugly macro, but ... what's the right move here?
>>
>> You mean how none of the structs in src/include/boot/coreboot_tables.h
>> have a packed attribute decorated on them? And they should be marked
>> packed since these are a serialized format. That's not really going to
>> help you.
>>
>> One thing you do is break up all uint64_t in that header to be a
>> struct of 2 uint32_t -- which is what lb_uint64 was for I assume. What
>> that means is the types all need to be marshalled properly, and you'd
>> have to do this as it is if RISC V doesn't support unaligned accesses.
>>
>> In general, coreboot has been largely written to assume unaligned
>> accesses are no big deal (thanks, x86!). Because of this architectures
>> like ARM *have* to get their MMUs up to enable normal memory so that
>> it can honor the "handle unaligned accesses".
>>
>> >
>> > ron
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot


From mr.nuke.me at gmail.com  Fri Jul 17 22:44:37 2015
From: mr.nuke.me at gmail.com (mrnuke)
Date: Fri, 17 Jul 2015 13:44:37 -0700
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
 <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>
Message-ID: <102657251.ltvqduH99B@nukelap.gtech>

On Friday, July 17, 2015 03:32:43 PM Aaron Durbin wrote:
> On Fri, Jul 17, 2015 at 3:27 PM, ron minnich <rminnich at gmail.com> wrote:
> > bummer. We're going to have to add marshalling code to cbfs, to copy
> 
> Ya. You'd need to fix cbfs as well is my guess.
> 
Not really. It's OK to be extra careful when generating the CBFS headers, but 
it's also nice to have a clean simple format that can be easily parsed from 
assembly (haven't we seen that before?).

Long term, we might want to look at the benefits of consolidating the table 
format. At the very least, we shouldn't care enough about how gcc aligns 
things, that there's a multi-line comment about it.

> > pointers from the architecture we're on to the architecture we're on,
> > which
> > was compiled by gcc for the architecture we're on, compiled on the
> > architecture we're not on, to conform to rules for an architecture we're
> > not on.
> > 
> > goodbye, a = b
> > hello, memcpy(&a, &b, sizeof(a));
> > barf.
> 
> Ya. And since this is C it makes for some really annoying work. Now if
> you write a spec that can be processed by a machine for all these
> serialized structs we could generate code based on the CPU's
> constraints.
> 
Well, similar schemes exist already (see nanopb).

Alex


From jwerner at chromium.org  Sat Jul 18 00:05:17 2015
From: jwerner at chromium.org (Julius Werner)
Date: Fri, 17 Jul 2015 15:05:17 -0700
Subject: [coreboot] cbfs alignment
In-Reply-To: <102657251.ltvqduH99B@nukelap.gtech>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
 <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>
 <102657251.ltvqduH99B@nukelap.gtech>
Message-ID: <CAODwPW9FF41xVo=JCh5YTCqn23jT9g-GNzgx_X16DfOk6j78Rg@mail.gmail.com>

Is there no way to make RISCV support unaligned accesses? There's a
bunch of things in coreboot (and especially libpayload) that depend on
it. I think that it generally makes code look much simpler (and run
faster) if you can assume that it's supported across the board.

If we do need to make CBFS unaligned access aware, we should do it
with some inline functions that fold into a simple read on the
platforms that support them in hardware.

(Depending on how many such accesses you have and what your context
switch costs are, it might also be feasible to emulate it in an
exception handler... that way you wouldn't need to hunt down every
single occurrence we've accumulated over the years.)


From rminnich at gmail.com  Sat Jul 18 00:13:53 2015
From: rminnich at gmail.com (ron minnich)
Date: Fri, 17 Jul 2015 22:13:53 +0000
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAODwPW9FF41xVo=JCh5YTCqn23jT9g-GNzgx_X16DfOk6j78Rg@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
 <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>
 <102657251.ltvqduH99B@nukelap.gtech>
 <CAODwPW9FF41xVo=JCh5YTCqn23jT9g-GNzgx_X16DfOk6j78Rg@mail.gmail.com>
Message-ID: <CAP6exYJ7aZRfOCSCt+d-bjVhHy3Xeg0Y4GMjwtnoPcZ=pxWXOw@mail.gmail.com>

we're going to support unaligned accesses, they make it easy. I think it's
silly that have data structs that are not 64-bit aligned, however :-)

ron

On Fri, Jul 17, 2015 at 3:05 PM Julius Werner <jwerner at chromium.org> wrote:

> Is there no way to make RISCV support unaligned accesses? There's a
> bunch of things in coreboot (and especially libpayload) that depend on
> it. I think that it generally makes code look much simpler (and run
> faster) if you can assume that it's supported across the board.
>
> If we do need to make CBFS unaligned access aware, we should do it
> with some inline functions that fold into a simple read on the
> platforms that support them in hardware.
>
> (Depending on how many such accesses you have and what your context
> switch costs are, it might also be feasible to emulate it in an
> exception handler... that way you wouldn't need to hunt down every
> single occurrence we've accumulated over the years.)
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150717/65281cec/attachment-0001.html>

From jwerner at chromium.org  Sat Jul 18 00:17:21 2015
From: jwerner at chromium.org (Julius Werner)
Date: Fri, 17 Jul 2015 15:17:21 -0700
Subject: [coreboot] cbfs alignment
In-Reply-To: <CAP6exYJ7aZRfOCSCt+d-bjVhHy3Xeg0Y4GMjwtnoPcZ=pxWXOw@mail.gmail.com>
References: <CAP6exYLnphkNy3KXEdzfap0snKBQT13PCX26WFoHQiygz5_waw@mail.gmail.com>
 <CAP6exY+y1yFQxaAyidujyrrt8wNMK-Q03ksX17FZR6TPmNTtzg@mail.gmail.com>
 <CAE2855teJ-nS==NaiUz=xTsni0vzwEyVaNehkYbj7WJ=GAjhfw@mail.gmail.com>
 <102657251.ltvqduH99B@nukelap.gtech>
 <CAODwPW9FF41xVo=JCh5YTCqn23jT9g-GNzgx_X16DfOk6j78Rg@mail.gmail.com>
 <CAP6exYJ7aZRfOCSCt+d-bjVhHy3Xeg0Y4GMjwtnoPcZ=pxWXOw@mail.gmail.com>
Message-ID: <CAODwPW_cE3v0WmAjuo7SriTETju0nJD=dCa5cCBKSdnbs0L1nQ@mail.gmail.com>

On Fri, Jul 17, 2015 at 3:13 PM, ron minnich <rminnich at gmail.com> wrote:
> we're going to support unaligned accesses, they make it easy. I think it's
> silly that have data structs that are not 64-bit aligned, however :-)

Of course. Unfortunately they're usually embedded in age-old
specifications that are extremely hard or impossible to change. ;)
(USB is another prime example that comes to mind... they just *had* to
put those LE16s in the weirdest places for no reason.)


From wkevils at gmail.com  Sat Jul 18 09:03:38 2015
From: wkevils at gmail.com (Kevin Wilson)
Date: Sat, 18 Jul 2015 10:03:38 +0300
Subject: [coreboot] Finding whether the BIOS is coreboot or not
Message-ID: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>

Hello,
Is there a way, from a device running Linux,  to which I have access
to the command line, to know
whether the BIOS is coreboot or not ? by some utility, or by some sysfs entry ?

Regards,
Kevin


From pgeorgi at google.com  Sat Jul 18 09:34:19 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Sat, 18 Jul 2015 09:34:19 +0200
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
Message-ID: <CAE-gjdUuRhJP_rv33Hp1bObzL763EtCWULk1Hv3hx58O2fmjKw@mail.gmail.com>

2015-07-18 9:03 GMT+02:00 Kevin Wilson <wkevils at gmail.com>:
> Is there a way, from a device running Linux,  to which I have access
> to the command line, to know
> whether the BIOS is coreboot or not ? by some utility, or by some sysfs entry ?
We usually have coreboot related vendor names for ACPI tables (eg.
dsdt table id 'COREBOOT'). Those are visible early on in dmesg, I
think.
Also our cbmem utility (coreboot source tree, util/cbmem) can print a
coreboot specific table's content.

Neither of these are guaranteed to be around (it would be possible to
cloak things thoroughly), but it's likely that they are on coreboot,
and pretty much non-existent otherwise.


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From peter90609 at gmail.com  Tue Jul 14 08:45:41 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Tue, 14 Jul 2015 14:45:41 +0800
Subject: [coreboot] There is no coreboot_ram.debug in my directory
Message-ID: <CACS=nFNzih_Fb77aU1cBk094KmykAQkyY2eoRhNnEtg1KZk0vw@mail.gmail.com>

hello ,

1.I tried to trace coreboot, I followed the coreboot Debugging steps but
there is no *coreboot_ram.debug *in my directory.
I select *GDB debugging support* and *Wait for a GDB connection *rebuild
coreboot already, what step is missing ?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150714/ea81f716/attachment.html>

From adurbin at chromium.org  Sat Jul 18 16:43:30 2015
From: adurbin at chromium.org (Aaron Durbin)
Date: Sat, 18 Jul 2015 07:43:30 -0700
Subject: [coreboot] There is no coreboot_ram.debug in my directory
In-Reply-To: <CACS=nFNzih_Fb77aU1cBk094KmykAQkyY2eoRhNnEtg1KZk0vw@mail.gmail.com>
References: <CACS=nFNzih_Fb77aU1cBk094KmykAQkyY2eoRhNnEtg1KZk0vw@mail.gmail.com>
Message-ID: <CAE2855t_suuaC6ms4s0d=Mcdq=nLpmp-QQSryU+YmuuBvU73aw@mail.gmail.com>

On Mon, Jul 13, 2015 at 11:45 PM, Yu-Cheng Liu <peter90609 at gmail.com> wrote:
> hello ,
>
> 1.I tried to trace coreboot, I followed the coreboot Debugging steps but
> there is no coreboot_ram.debug in my directory.
> I select GDB debugging support and Wait for a GDB connection rebuild
> coreboot already, what step is missing ?
>

There were some file name changes in the tree. coreboot_ram.debug
should now be ramstage.debug. It should be sitting in the
build/cbfs/fallback/ directory.

Hope that helps.

-Aaron

>
>
>
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From rminnich at gmail.com  Sat Jul 18 18:10:52 2015
From: rminnich at gmail.com (ron minnich)
Date: Sat, 18 Jul 2015 16:10:52 +0000
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAE-gjdUuRhJP_rv33Hp1bObzL763EtCWULk1Hv3hx58O2fmjKw@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
 <CAE-gjdUuRhJP_rv33Hp1bObzL763EtCWULk1Hv3hx58O2fmjKw@mail.gmail.com>
Message-ID: <CAP6exYJ5eSJ-vmHM+C-vFRd7y0Gv6a2eYS-bOFE00hxBxOz8pw@mail.gmail.com>

Could you also look for LBIO in the e and f segments?

On Sat, Jul 18, 2015 at 12:34 AM Patrick Georgi <pgeorgi at google.com> wrote:

> 2015-07-18 9:03 GMT+02:00 Kevin Wilson <wkevils at gmail.com>:
> > Is there a way, from a device running Linux,  to which I have access
> > to the command line, to know
> > whether the BIOS is coreboot or not ? by some utility, or by some sysfs
> entry ?
> We usually have coreboot related vendor names for ACPI tables (eg.
> dsdt table id 'COREBOOT'). Those are visible early on in dmesg, I
> think.
> Also our cbmem utility (coreboot source tree, util/cbmem) can print a
> coreboot specific table's content.
>
> Neither of these are guaranteed to be around (it would be possible to
> cloak things thoroughly), but it's likely that they are on coreboot,
> and pretty much non-existent otherwise.
>
>
> Patrick
> --
> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
> Hamburg
> Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150718/e4fa9560/attachment.html>

From marcj303 at gmail.com  Sat Jul 18 19:20:46 2015
From: marcj303 at gmail.com (Marc Jones)
Date: Sat, 18 Jul 2015 17:20:46 +0000
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAP6exYJ5eSJ-vmHM+C-vFRd7y0Gv6a2eYS-bOFE00hxBxOz8pw@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
 <CAE-gjdUuRhJP_rv33Hp1bObzL763EtCWULk1Hv3hx58O2fmjKw@mail.gmail.com>
 <CAP6exYJ5eSJ-vmHM+C-vFRd7y0Gv6a2eYS-bOFE00hxBxOz8pw@mail.gmail.com>
Message-ID: <CALrs_3hKrZ09rgBn_L=qVZK5kSefSy94aNqfJEOcQMyCcd+7_Q@mail.gmail.com>

My $.02 is to check dmidecode.
Marc


On Sat, Jul 18, 2015 at 10:11 AM ron minnich <rminnich at gmail.com> wrote:

> Could you also look for LBIO in the e and f segments?
>
> On Sat, Jul 18, 2015 at 12:34 AM Patrick Georgi <pgeorgi at google.com>
> wrote:
>
>> 2015-07-18 9:03 GMT+02:00 Kevin Wilson <wkevils at gmail.com>:
>> > Is there a way, from a device running Linux,  to which I have access
>> > to the command line, to know
>> > whether the BIOS is coreboot or not ? by some utility, or by some sysfs
>> entry ?
>> We usually have coreboot related vendor names for ACPI tables (eg.
>> dsdt table id 'COREBOOT'). Those are visible early on in dmesg, I
>> think.
>> Also our cbmem utility (coreboot source tree, util/cbmem) can print a
>> coreboot specific table's content.
>>
>> Neither of these are guaranteed to be around (it would be possible to
>> cloak things thoroughly), but it's likely that they are on coreboot,
>> and pretty much non-existent otherwise.
>>
>>
>> Patrick
>> --
>> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
>> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
>> Hamburg
>> Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150718/721f2f6e/attachment.html>

From a_coreboot at skater.priv.at  Sat Jul 18 22:14:35 2015
From: a_coreboot at skater.priv.at (Andreas Kreuzinger)
Date: Sat, 18 Jul 2015 22:14:35 +0200
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
Message-ID: <20150718201435.GA3449@skater.priv.at>

Hi,

* Kevin Wilson <wkevils at gmail.com> [2015-07-18 10:03]:
> Is there a way, from a device running Linux,  to which I have access
> to the command line, to know
> whether the BIOS is coreboot or not ? by some utility, or by some sysfs entry ?

Yes, if you have dmidecode present:
ctvdr:~# dmidecode -t bios | grep Vendor                                        
        Vendor: coreboot                                                        
                                                                                
Probably it might be possible to set it to something else, but that             
seems to be the default.                                                        
                                                                                
@ndy                                                                            



From wkevils at gmail.com  Sun Jul 19 06:45:50 2015
From: wkevils at gmail.com (Kevin Wilson)
Date: Sun, 19 Jul 2015 07:45:50 +0300
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <20150718201435.GA3449@skater.priv.at>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
 <20150718201435.GA3449@skater.priv.at>
Message-ID: <CAGXs5wU6=JvvYpra4y5ryL2Tfw=wk6YCC=Co9Z9LLZ-T+hMZuQ@mail.gmail.com>

Hi,
Thanks for all the responses.
Short questions:
I saw. on my system::
cat  /sys/class/dmi/id/bios_vendor
coreboot

Is it equivalent to
dmidecode -t bios | grep Vendor
        Vendor: coreboot

What I mean is: does dmidecode in fact read the
/sys/class/dmi/id/bios_vendor  entry?


Regard,
Kevin


On Sat, Jul 18, 2015 at 11:14 PM, Andreas Kreuzinger
<a_coreboot at skater.priv.at> wrote:
> Hi,
>
> * Kevin Wilson <wkevils at gmail.com> [2015-07-18 10:03]:
>> Is there a way, from a device running Linux,  to which I have access
>> to the command line, to know
>> whether the BIOS is coreboot or not ? by some utility, or by some sysfs entry ?
>
> Yes, if you have dmidecode present:
> ctvdr:~# dmidecode -t bios | grep Vendor
>         Vendor: coreboot
>
> Probably it might be possible to set it to something else, but that
> seems to be the default.
>
> @ndy
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From a_coreboot at skater.priv.at  Sun Jul 19 09:25:11 2015
From: a_coreboot at skater.priv.at (Andreas Kreuzinger)
Date: Sun, 19 Jul 2015 09:25:11 +0200
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAGXs5wU6=JvvYpra4y5ryL2Tfw=wk6YCC=Co9Z9LLZ-T+hMZuQ@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
 <20150718201435.GA3449@skater.priv.at>
 <CAGXs5wU6=JvvYpra4y5ryL2Tfw=wk6YCC=Co9Z9LLZ-T+hMZuQ@mail.gmail.com>
Message-ID: <20150719072511.GB3449@skater.priv.at>

Hi,

[ Please don't send an extra mail to me, I'm on the mailing list.
  And try to avoid TOFU. Thank you. ]

* Kevin Wilson <wkevils at gmail.com> [2015-07-19 07:45]:
> Thanks for all the responses.
> Short questions:
> I saw. on my system::
> cat  /sys/class/dmi/id/bios_vendor
> coreboot
> 
> Is it equivalent to
> dmidecode -t bios | grep Vendor
>         Vendor: coreboot
> 
> What I mean is: does dmidecode in fact read the
> /sys/class/dmi/id/bios_vendor  entry?
[...snip...]

Seems so:
ctvdr:~# cat /sys/class/dmi/id/bios_vendor
coreboot

Let's take a different example:
erwin:~# dmidecode -t bios | grep Vendor
        Vendor: Award Software International, Inc.
erwin:~# cat /sys/class/dmi/id/bios_vendor
Award Software International, Inc.

If you want to be sure, verify with the dmidecode source code.

BTW: I found a shorter dmidecode command line:
ctvdr:~# dmidecode -s bios-vendor
coreboot

@ndy


From wangsiyuanbuaa at gmail.com  Mon Jul 20 10:52:56 2015
From: wangsiyuanbuaa at gmail.com (WANG Siyuan)
Date: Mon, 20 Jul 2015 08:52:56 +0000
Subject: [coreboot] ACPI resource problem
In-Reply-To: <CAGH0wH3R1hPK8SsFKFZdp72V=+bd3chCztxtjtAvWudT7ZnVpA@mail.gmail.com>
References: <CAKhuMPmYN=Ub7F=LqQqGrS0VQCJurT+_AuFCBNt+HUc8KZsm4w@mail.gmail.com>
 <CAGH0wH3R1hPK8SsFKFZdp72V=+bd3chCztxtjtAvWudT7ZnVpA@mail.gmail.com>
Message-ID: <CAKhuMPmvS3vufc1i7hJob0dj5L7PyUfh_XFe=-b6L+CEfKDK1A@mail.gmail.com>

Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000) reserves memory in asl. I
tried to add DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
but not work.

On Tue, Jul 7, 2015 at 7:22 PM WANG FEI <wangfei.jimei at gmail.com> wrote:

> Siyuan, did you reserved 0xFEDC2000 - 0xFEDC2FFF in ASL file? what you've
> done in your code is to reserve this MMIO area in E820 table, OS will not
> take this area, but it's not enough for ACPI.
>
> Here is a sample to reserve MMIO area in asl file.
>
> // TPM Area (0xfed40000-0xfed44fff)
> DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
> Cacheable, ReadWrite,
> 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
> 0x00005000,,, TPMR)
>
> On Mon, Jul 6, 2015 at 12:31 PM, WANG Siyuan <wangsiyuanbuaa at gmail.com>
> wrote:
>
>> Hi,
>> I have a question about acpi resource.
>>
>> My device need the resource:
>>     Name(_CRS, ResourceTemplate() {
>>       IRQ(Edge, ActiveHigh, Exclusive) {3}
>>       Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
>>     })
>> In Win8's device manager, I got error "This device cannot find enough
>> free resources that it can use."
>>
>> I reserve resource (0xFEDC2000 - 0xFEDC2FFF) using flag resource->flags =
>> IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED
>> |  IORESOURCE_ASSIGNED; I still got this error.
>>
>> I have 2 questions:
>> 1) Do I need to reserve MMIO for (0xFEDC2000 - 0xFEDC2FFF)?
>> 2) Do I need to do some thing for IRQ(Edge, ActiveHigh, Exclusive) {3}?
>>
>> Any replay is appreciated!
>>
>> Yours sincerely,
>> WANG Siyuan
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150720/6a243df1/attachment.html>

From namangov at gmail.com  Wed Jul 22 01:12:27 2015
From: namangov at gmail.com (Naman Govil)
Date: Tue, 21 Jul 2015 19:12:27 -0400
Subject: [coreboot] coreboot on Qemu aarch64 - error while booting kernel
Message-ID: <CA+4PC+_fNVGQ4gik56Sj_Oj4cF-8bq7i9dnmT99cSrWL1jYB0A@mail.gmail.com>

Hi,

I am trying to boot off a coreboot kernel image on aarch64
(qemu-system-aarch64) [Currently under development]. I am sort of stuck
with some qemu related issue (not as much of a coreboot issue)
I have the compiled image which I am ran by using the command

$qemu-system-aarch64 -machine type=virt -nographic -kernel
~/coreboot/build/coreboot.rom

I was getting no output on serial (on the terminal) on doing this.

For debugging purposes, I tried to get qemu monitor working first.

This gave me then following :

qemu: fatal: Trying to execute code outside RAM or ROM at 0x0000000008000000

R00=00000950 R01=ffffffff R02=44000000 R03=00000000

R04=00000000 R05=00000000 R06=00000000 R07=00000000

R08=00000000 R09=00000000 R10=00000000 R11=00000000

R12=00000000 R13=00000000 R14=40010010 R15=08000000

PSR=400001db -Z-- A und32

s00=00000000 s01=00000000 d00=0000000000000000

s02=00000000 s03=00000000 d01=0000000000000000

s04=00000000 s05=00000000 d02=0000000000000000

s06=00000000 s07=00000000 d03=0000000000000000

s08=00000000 s09=00000000 d04=0000000000000000

s10=00000000 s11=00000000 d05=0000000000000000

s12=00000000 s13=00000000 d06=0000000000000000

s14=00000000 s15=00000000 d07=0000000000000000

s16=00000000 s17=00000000 d08=0000000000000000

s18=00000000 s19=00000000 d09=0000000000000000

s20=00000000 s21=00000000 d10=0000000000000000

s22=00000000 s23=00000000 d11=0000000000000000

s24=00000000 s25=00000000 d12=0000000000000000

s26=00000000 s27=00000000 d13=0000000000000000

s28=00000000 s29=00000000 d14=0000000000000000

s30=00000000 s31=00000000 d15=0000000000000000

s32=00000000 s33=00000000 d16=0000000000000000

s34=00000000 s35=00000000 d17=0000000000000000

s36=00000000 s37=00000000 d18=0000000000000000

s38=00000000 s39=00000000 d19=0000000000000000

s40=000000 Abort trap: 6

I did some searching, this meant that the bootloader cannot be loaded. And
realised maybe the ROM qemu is getting is not sufficient. The 'execute
outside ram or rom' is usually a jump to somewhere that qemu does not
recognize as ROM/RAM.

In coreboot*, *Since we expect

CONFIG_BOOTBLOCK_BASE is 0x10000
CONFIG_ROMSTAGE_BASE  is 0x20000
CONFIG_SYS_SDRAM_BASE is 0x1000000

i.e ROM to start at 64k. So I ran qemu by giving a -m 2048M (for testing)
and got something. A window popped out (qemu), I am unsure as to what this
is. I am attaching the picture with this mail*.*


What is this window? Is this just a serial monitor? If so, why does it pop
out on doing just $qemu-system-aarch64 -machine type=virt -m 2048M
-nographic -kernel ~/coreboot/build/coreboot.rom ?

Why is there no output on the terminal?


I would appreciate any help on this.


Regards,
Naman
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150721/55270152/attachment-0001.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: image.png
Type: image/png
Size: 24126 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150721/55270152/attachment-0001.png>

From pgeorgi at google.com  Wed Jul 22 19:55:19 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Wed, 22 Jul 2015 10:55:19 -0700
Subject: [coreboot] coreboot changelog - Week of 2015-07-13
Message-ID: <CAE-gjdWdxE6Gh7PRAT6YFdOjnZf7NcKEE=DzYmpu16P_quidHA@mail.gmail.com>

(This covers commits 6cb3a59 (which is the 4.1 tag) up to commit 406effd5)

This week brought the addition of one new chipset and four new
mainboards: Welcome the Intel Skylake SoC, and the new mainboards
google/cyan, intel/kunimitsu, intel/sklrvp, and intel/strago, which
are Braswell or Skylake based.

As for tools, the script that generated the 4.1 release was added to
the tree. To aid with debugging build issues, buildgcc shows the URLs
it uses to download the sources to the toolchain. The standard git
hook now uses a customized version of Linux?s checkpatch.pl utility
for better coding style compliance tests. The cbmem utility gained
OpenBSD compatibility when reading timestamps.

The USB host drivers in libpayload saw improvements both for USB3,
supporting SuperSpeed hubs and showing more robustness in the presence
of strangely behaving USB devices, and for DWC2 controllers, which now
support LowSpeed devices behind HighSpeed hubs. coreboot also passes
more information to libpayload on where to find the flash part as well
as the parameters of the CBFS that was used during boot.

The CBFS format is seeing new development: The default alignment for
files is now hardcoded to 64 bytes, which was already the default.
There are no known instances where this value was changed, and it
simplifies development going forward. The change is forward compatible
in that old users can still read new CBFS images. New CBFS consumers
run into problems if they work on a CBFS image with a different
alignment configuration.

Furthermore there were discussions on how to extend the CBFS format
compatibly. So far this led to numerous refactorings in cbfstool to
simplify further development.

Finally, there were a whole lot of bug fixes: ARM64, the code for
Nvidia?s Tegra210 chipset and the google/foster and google/smaug
boards saw lots of development, from making them boot again to various
hardware enablement. AMD?s RS780 chipset was effectively disabled due
to a typo in the build system. There?s an ongoing effort to bring AMD
K8/Fam10h into shape again, which also positively affected HD Audio
configuration. CBMEM timestamps are more complete than ever.

There was also the usual bunch of cleanups that get rid of unused
Kconfig symbols and configuration options, deal with wrong
indentation, and replace magic numbers with meaningful names.


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores


From GNUtoo at no-log.org  Fri Jul 24 22:16:16 2015
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Fri, 24 Jul 2015 22:16:16 +0200
Subject: [coreboot] Thinkpad ECs (H8)
Message-ID: <20150724221616.5fbe3ab5@top-laptop>

Hi,

I just learned about (and watched) a presentation[1] that is about
backdooring the Thinkpad ECs.

This information might help with the task of writing a free software EC
firmware[2].

The information is also very useful to get a better ideas of the
threats due to having a non-free EC firmware.
I for instance missed the EC ThinkLight issue, when thinking about the
security of i945 Lenovo laptops:
-> The EC code is non-free
-> There is a long wire that goes from the EC to the ThinkLight (That's
   a potential antenna, according to the talk the Thinkpad EC
   microcontrollers speed is around 10Mhz so it seems doable)
-> Since The i945 Thinkpads are often bought second hand, a broken EC
   light isn't suspicious if you don't know about this issue.

The talk contains a link to an EC firmware dumper[3]. Unfortunately
after cloning the it, the git repository contained no code at all.
Maybe Ralf-Philipp could comment on that?

In the QA, it is also said that it's possible to talk directly to the
EC hardware to dump the fimrware (and not the EC firmware), from the
computer. The IO addresses he's mentioning look like EC addresses.

I then wonder if it's also possible to flash it in the same way.
In that case the fimrware should better be able to power on the
computer, else some sort of external flashing/recovery would be needed
(as it is for coreboot).

The talk also contained a link to the original firmware "commented
assembly".
I've no idea if it's safe to look at it, but it's better not to do it
until we know for sure that's it's legally safe.
The SFLC (Software Freedom Law Center) might help with that.
The people who looks at it might be prevented from writing legal free
software firmware for such EC if they do, so beware.

The talk also mention that the H8(The Thinkpad EC) have good
documentation.

References:
-----------
[1] 27c3-4174-en-the_hidden_nemesis.webm
[2] http://blogs.coreboot.org/blog/tag/h8s/
[3] http://coderpunks.org/ecdumper

Denis.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: not available
Type: application/pgp-signature
Size: 819 bytes
Desc: OpenPGP digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150724/f97c5d3a/attachment.sig>

From fowlslegs at riseup.net  Sat Jul 25 06:57:36 2015
From: fowlslegs at riseup.net (Noah Vesely)
Date: Fri, 24 Jul 2015 21:57:36 -0700
Subject: [coreboot] VT-d on Pixel 2015 (samus)
Message-ID: <55B31740.8060100@riseup.net>

I've been trying to get VT-d working on John Lewis's build for the 2015 
Pixel (samus). You can see our conversation at 
https://plus.google.com/116173342884039282107/posts/TGA4EXYQMfq and I 
have also pasted it below. So far, I haven't got anywhere, so I thought 
I would try asking you all as well.

Thanks,
Noah

&%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#

Noah Vesely
  -  Jul 16, 2015

Is it possible to get Intel VT-d working on the Chromebook Pixel 2/ 
Samus? The i7-5600U processor does support it.?
ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz)
ark.intel.com
ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz) quick 
reference guide including specifications, features, pricing, 
compatibility, design documentation, ordering codes, spec codes and more.
John Lewis's profile photoNoah Vesely's profile photo
10 comments
John Lewis
Jul 18, 2015




AFAIK, none of the hardware VT extensions are disabled in the firmware 
on Samus. Have you tried it??
Noah Vesely
Jul 18, 2015




Yes. VT-x was enable while VT-d was not.?
John Lewis
Jul 18, 2015




Clone 
https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-samus-6300.B 
and run menuconfig to see if there's an option for VT-d.?
Noah Vesely
Jul 19, 2015




I can't figure out how to checkout this repository. I cloned the main 
third_part/coreboot repo then checked out the broadwell branch, but 
could not find the same directory you linked. Maybe my git fu could use 
some work.?
John Lewis
Jul 20, 2015




Use the last chunk of the URL as the branch argument i.e. "-b 
firmware-samus-6300.B".?
Noah Vesely
Jul 20, 2015




Nothing in menuconfig, however, I found the line `#define CONFIG_IOMMU 
0` in ./build/config.h. I also found `#define CONFIG_ENABLE_VMX 0`.?
John Lewis
Jul 21, 2015




VMX is already enabled in the firmware. IOMMU is unrelated. I would have 
to conclude that VT'd is either not supported by that CPU or something 
more needs to be done in coreboot to get it to work.?
Noah Vesely
Jul 21, 2015




VT-d is supported by this CPU. See original link to Intel Ark.

VT-d is Intel's specification for their IOMMU technology, so I don't see 
how it's unrelated.?
John Lewis
Jul 21, 2015




Take a look at the .config from a shellball ROM (you can extract it 
using cbfstool).

https://johnlewis.ie/extracting-the-shell-ball-rom-using-a-chromeos-image/?
Noah Vesely
9:15 PM




I don't see anything relevant to VT-d; no VT-d keywords (e.g., iommu, 
vt, vmx, hvm, and directio).

http://paste.debian.net/hidden/08ac8494/?


From rminnich at gmail.com  Sat Jul 25 08:25:33 2015
From: rminnich at gmail.com (ron minnich)
Date: Sat, 25 Jul 2015 06:25:33 +0000
Subject: [coreboot] VT-d on Pixel 2015 (samus)
In-Reply-To: <55B31740.8060100@riseup.net>
References: <55B31740.8060100@riseup.net>
Message-ID: <CAP6exYJjAUwA7pMxJzDRGEZMfMBKRuwQWJYsvieqFcA9S1jy6g@mail.gmail.com>

what does rdmsr 0 0x3a show you?

ron

On Fri, Jul 24, 2015 at 10:06 PM Noah Vesely <fowlslegs at riseup.net> wrote:

> I've been trying to get VT-d working on John Lewis's build for the 2015
> Pixel (samus). You can see our conversation at
> https://plus.google.com/116173342884039282107/posts/TGA4EXYQMfq and I
> have also pasted it below. So far, I haven't got anywhere, so I thought
> I would try asking you all as well.
>
> Thanks,
> Noah
>
> &%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#
>
> Noah Vesely
>   -  Jul 16, 2015
>
> Is it possible to get Intel VT-d working on the Chromebook Pixel 2/
> Samus? The i7-5600U processor does support it.?
> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz)
> ark.intel.com
> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz) quick
> reference guide including specifications, features, pricing,
> compatibility, design documentation, ordering codes, spec codes and more.
> John Lewis's profile photoNoah Vesely's profile photo
> 10 comments
> John Lewis
> Jul 18, 2015
>
>
>
>
> AFAIK, none of the hardware VT extensions are disabled in the firmware
> on Samus. Have you tried it??
> Noah Vesely
> Jul 18, 2015
>
>
>
>
> Yes. VT-x was enable while VT-d was not.?
> John Lewis
> Jul 18, 2015
>
>
>
>
> Clone
>
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-samus-6300.B
> and run menuconfig to see if there's an option for VT-d.?
> Noah Vesely
> Jul 19, 2015
>
>
>
>
> I can't figure out how to checkout this repository. I cloned the main
> third_part/coreboot repo then checked out the broadwell branch, but
> could not find the same directory you linked. Maybe my git fu could use
> some work.?
> John Lewis
> Jul 20, 2015
>
>
>
>
> Use the last chunk of the URL as the branch argument i.e. "-b
> firmware-samus-6300.B".?
> Noah Vesely
> Jul 20, 2015
>
>
>
>
> Nothing in menuconfig, however, I found the line `#define CONFIG_IOMMU
> 0` in ./build/config.h. I also found `#define CONFIG_ENABLE_VMX 0`.?
> John Lewis
> Jul 21, 2015
>
>
>
>
> VMX is already enabled in the firmware. IOMMU is unrelated. I would have
> to conclude that VT'd is either not supported by that CPU or something
> more needs to be done in coreboot to get it to work.?
> Noah Vesely
> Jul 21, 2015
>
>
>
>
> VT-d is supported by this CPU. See original link to Intel Ark.
>
> VT-d is Intel's specification for their IOMMU technology, so I don't see
> how it's unrelated.?
> John Lewis
> Jul 21, 2015
>
>
>
>
> Take a look at the .config from a shellball ROM (you can extract it
> using cbfstool).
>
> https://johnlewis.ie/extracting-the-shell-ball-rom-using-a-chromeos-image/
> ?
> Noah Vesely
> 9:15 PM
>
>
>
>
> I don't see anything relevant to VT-d; no VT-d keywords (e.g., iommu,
> vt, vmx, hvm, and directio).
>
> http://paste.debian.net/hidden/08ac8494/?
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150725/bbe2b4d8/attachment.html>

From rminnich at gmail.com  Sat Jul 25 16:41:07 2015
From: rminnich at gmail.com (ron minnich)
Date: Sat, 25 Jul 2015 14:41:07 +0000
Subject: [coreboot] Thinkpad ECs (H8)
In-Reply-To: <20150724221616.5fbe3ab5@top-laptop>
References: <20150724221616.5fbe3ab5@top-laptop>
Message-ID: <CAP6exYKToTVQLQzpHmq5JH1tiwwPcr8N-PWwE_9Xru=qbbtL4Q@mail.gmail.com>

w.r.t. the git question, I cloned it too and poked around, doesn't seem to
be anything there
save a few empy branches and a log with one entry.

ron

On Fri, Jul 24, 2015 at 1:33 PM Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
wrote:

> Hi,
>
> I just learned about (and watched) a presentation[1] that is about
> backdooring the Thinkpad ECs.
>
> This information might help with the task of writing a free software EC
> firmware[2].
>
> The information is also very useful to get a better ideas of the
> threats due to having a non-free EC firmware.
> I for instance missed the EC ThinkLight issue, when thinking about the
> security of i945 Lenovo laptops:
> -> The EC code is non-free
> -> There is a long wire that goes from the EC to the ThinkLight (That's
>    a potential antenna, according to the talk the Thinkpad EC
>    microcontrollers speed is around 10Mhz so it seems doable)
> -> Since The i945 Thinkpads are often bought second hand, a broken EC
>    light isn't suspicious if you don't know about this issue.
>
> The talk contains a link to an EC firmware dumper[3]. Unfortunately
> after cloning the it, the git repository contained no code at all.
> Maybe Ralf-Philipp could comment on that?
>
> In the QA, it is also said that it's possible to talk directly to the
> EC hardware to dump the fimrware (and not the EC firmware), from the
> computer. The IO addresses he's mentioning look like EC addresses.
>
> I then wonder if it's also possible to flash it in the same way.
> In that case the fimrware should better be able to power on the
> computer, else some sort of external flashing/recovery would be needed
> (as it is for coreboot).
>
> The talk also contained a link to the original firmware "commented
> assembly".
> I've no idea if it's safe to look at it, but it's better not to do it
> until we know for sure that's it's legally safe.
> The SFLC (Software Freedom Law Center) might help with that.
> The people who looks at it might be prevented from writing legal free
> software firmware for such EC if they do, so beware.
>
> The talk also mention that the H8(The Thinkpad EC) have good
> documentation.
>
> References:
> -----------
> [1] 27c3-4174-en-the_hidden_nemesis.webm
> [2] http://blogs.coreboot.org/blog/tag/h8s/
> [3] http://coderpunks.org/ecdumper
>
> Denis.
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150725/e0004a07/attachment.html>

From andy at skater.priv.at  Sat Jul 18 21:38:05 2015
From: andy at skater.priv.at (Andreas Kreuzinger)
Date: Sat, 18 Jul 2015 21:38:05 +0200
Subject: [coreboot] Finding whether the BIOS is coreboot or not
In-Reply-To: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
References: <CAGXs5wUBz-RmF8hK3+n35UkEc6LhPSrR0=-k0iPTgX6fFszOBA@mail.gmail.com>
Message-ID: <20150718193805.GA2715@skater.priv.at>

Hi,

* Kevin Wilson <wkevils at gmail.com> [2015-07-18 10:03]:
> Is there a way, from a device running Linux,  to which I have access
> to the command line, to know
> whether the BIOS is coreboot or not ? by some utility, or by some sysfs entry ?

Yes, if you have dmidecode present:
ctvdr:~# dmidecode -t bios | grep Vendor
        Vendor: coreboot

Probably it might be possible to set it to something else, but that
seems to be the default.

@ndy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 173 bytes
Desc: Digital signature
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150718/2a3ff03d/attachment.asc>

From peter90609 at gmail.com  Tue Jul 21 11:04:10 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Tue, 21 Jul 2015 17:04:10 +0800
Subject: [coreboot] How to trigger SMI and implement SMM
Message-ID: <CACS=nFN-exefPPqqU=nsFe5vRrGJ4a3Vu9ASeU77Es7EZ5O_7Q@mail.gmail.com>

Hello,

I purpose to trigger SMI event and do something in SMM mode .



I trace the coreboot source code and found that, during the coreboot
environment setup, the file locate at *southbridge/intel/i82801ix/smi.c*
 will be excute. Is it enough for SMI/SMM operation? I didn?t see the code
under cpu/smm be locate in the ramstage.debug symbol.

What is the different purpose between *southbridge/intel/i82801ix/smi.c* and*
/cpu/x86/smm*? How do I trigger the SMI event?

(my platform is QEMU and Coreboot main board is ?emulation?)



Thanks for your kindly reply ~
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150721/3f60f1f6/attachment.html>

From wordpress at blogs.coreboot.org  Wed Jul 22 13:46:21 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Wed, 22 Jul 2015 11:46:21 +0000
Subject: [coreboot] =?utf-8?q?New_on_blogs=2Ecoreboot=2Eorg=3A_=5BGSoC=5D_?=
	=?utf-8?q?End_user_flash_tool_=E2=80=93_week_=236?=
Message-ID: <fb683639da618fdac4b7b04223ae5125@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150722/5c7a70dd/attachment.html>

From wordpress at blogs.coreboot.org  Wed Jul 22 19:52:20 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Wed, 22 Jul 2015 17:52:20 +0000
Subject: [coreboot] New on blogs.coreboot.org: coreboot changelog - Week of
	2015-07-13
Message-ID: <34231bddb9c0793f7544ff9be438b1b6@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150722/4ae9d5f8/attachment.html>

From peter90609 at gmail.com  Fri Jul 24 09:13:08 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Fri, 24 Jul 2015 15:13:08 +0800
Subject: [coreboot] No code in SMM handler address (0xa0000)
Message-ID: <CACS=nFP6JouuwJ9vsPfWOFokQ9v_CAR0yhjxniP2k5M6XppNJw@mail.gmail.com>

hello,
Here I have some questions in smi.c file
(coreboot/src/southbridge/intel/i82801ix/smi.c)

in smm_install function, one statement is to copy handler to SMRAM(0xa0000):
1.I can't find copy source data ( _binary_smm_start ),where is it write? I
watch (_binary_smm_start) memory address,and it has value in it.

2.After execute the memcpy statement,there is nothing change in 0xa0000,the
value in 65535

In smm_relocate function, the pointer goes in the " if " statement and then
"return" , the relocation code did not copy to 0x38000:

3.How do I let the program go through and do the job below the " if "
statement?


thanks~
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150724/032cb709/attachment.html>

From fowlslegs at riseup.net  Sun Jul 26 12:40:36 2015
From: fowlslegs at riseup.net (Noah Vesely)
Date: Sun, 26 Jul 2015 03:40:36 -0700
Subject: [coreboot] VT-d on Pixel 2015 (samus)
In-Reply-To: <CAP6exYJjAUwA7pMxJzDRGEZMfMBKRuwQWJYsvieqFcA9S1jy6g@mail.gmail.com>
References: <55B31740.8060100@riseup.net>
 <CAP6exYJjAUwA7pMxJzDRGEZMfMBKRuwQWJYsvieqFcA9S1jy6g@mail.gmail.com>
Message-ID: <55B4B924.5040909@riseup.net>

Thanks Ron! Took bit to get back to you because a Xen hypervisor update 
in Qubes seemed to put me in a boot loop. I just installed an Arch 
derivative because Arch has good support for this machine and I needed 
some type of test environment to actually run this command.

Anyway, `rdmsr 0x3a` (think this is what you meant to type) returns 0. I 
guess this means all 3 bits are not set in the IA32_FEATURE_CONTROL MSR.

This doesn't immediately make sense to me because (1) the output here 
seems to be telling me VT-x is not activated and the vmx cpu flag is 
present =><= and (2) I wrote in because `xl info` in Xen was reporting 
VT-x, but not VT-d, was activated and I was interested in how I could 
activate the former--isn't 0x3a unrelated to VT-d? Hopefully you can 
clarify this for me.

Noah

On 07/24/2015 11:25 PM, ron minnich wrote:
> what does rdmsr 0 0x3a show you?
>
> ron
>
> On Fri, Jul 24, 2015 at 10:06 PM Noah Vesely <fowlslegs at riseup.net> wrote:
>
>> I've been trying to get VT-d working on John Lewis's build for the 2015
>> Pixel (samus). You can see our conversation at
>> https://plus.google.com/116173342884039282107/posts/TGA4EXYQMfq and I
>> have also pasted it below. So far, I haven't got anywhere, so I thought
>> I would try asking you all as well.
>>
>> Thanks,
>> Noah
>>
>> &%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#
>>
>> Noah Vesely
>>    -  Jul 16, 2015
>>
>> Is it possible to get Intel VT-d working on the Chromebook Pixel 2/
>> Samus? The i7-5600U processor does support it.?
>> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz)
>> ark.intel.com
>> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz) quick
>> reference guide including specifications, features, pricing,
>> compatibility, design documentation, ordering codes, spec codes and more.
>> John Lewis's profile photoNoah Vesely's profile photo
>> 10 comments
>> John Lewis
>> Jul 18, 2015
>>
>>
>>
>>
>> AFAIK, none of the hardware VT extensions are disabled in the firmware
>> on Samus. Have you tried it??
>> Noah Vesely
>> Jul 18, 2015
>>
>>
>>
>>
>> Yes. VT-x was enable while VT-d was not.?
>> John Lewis
>> Jul 18, 2015
>>
>>
>>
>>
>> Clone
>>
>> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-samus-6300.B
>> and run menuconfig to see if there's an option for VT-d.?
>> Noah Vesely
>> Jul 19, 2015
>>
>>
>>
>>
>> I can't figure out how to checkout this repository. I cloned the main
>> third_part/coreboot repo then checked out the broadwell branch, but
>> could not find the same directory you linked. Maybe my git fu could use
>> some work.?
>> John Lewis
>> Jul 20, 2015
>>
>>
>>
>>
>> Use the last chunk of the URL as the branch argument i.e. "-b
>> firmware-samus-6300.B".?
>> Noah Vesely
>> Jul 20, 2015
>>
>>
>>
>>
>> Nothing in menuconfig, however, I found the line `#define CONFIG_IOMMU
>> 0` in ./build/config.h. I also found `#define CONFIG_ENABLE_VMX 0`.?
>> John Lewis
>> Jul 21, 2015
>>
>>
>>
>>
>> VMX is already enabled in the firmware. IOMMU is unrelated. I would have
>> to conclude that VT'd is either not supported by that CPU or something
>> more needs to be done in coreboot to get it to work.?
>> Noah Vesely
>> Jul 21, 2015
>>
>>
>>
>>
>> VT-d is supported by this CPU. See original link to Intel Ark.
>>
>> VT-d is Intel's specification for their IOMMU technology, so I don't see
>> how it's unrelated.?
>> John Lewis
>> Jul 21, 2015
>>
>>
>>
>>
>> Take a look at the .config from a shellball ROM (you can extract it
>> using cbfstool).
>>
>> https://johnlewis.ie/extracting-the-shell-ball-rom-using-a-chromeos-image/
>> ?
>> Noah Vesely
>> 9:15 PM
>>
>>
>>
>>
>> I don't see anything relevant to VT-d; no VT-d keywords (e.g., iommu,
>> vt, vmx, hvm, and directio).
>>
>> http://paste.debian.net/hidden/08ac8494/?
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot



From rminnich at gmail.com  Sun Jul 26 16:58:41 2015
From: rminnich at gmail.com (ron minnich)
Date: Sun, 26 Jul 2015 14:58:41 +0000
Subject: [coreboot] VT-d on Pixel 2015 (samus)
In-Reply-To: <55B4B924.5040909@riseup.net>
References: <55B31740.8060100@riseup.net>
 <CAP6exYJjAUwA7pMxJzDRGEZMfMBKRuwQWJYsvieqFcA9S1jy6g@mail.gmail.com>
 <55B4B924.5040909@riseup.net>
Message-ID: <CAP6exY+Cb-tEvdPgmWYx-fHabf=1a=6rjZ5uVfakO5wAV921FQ@mail.gmail.com>

There are so many bits, so little time. I have utterly forgotten how vt-d
gets enabled.

Anyway, there's two bits and a lock bit. coreboot very deliberately does
nothing with any of them -- this was a design decision a few years ago --
and it leaves them in a state that you can control them. So the 'enable
vt-x' part is easy and kvm will do it for you when you load the module, or
you can do it with the wrmsr command (for each core! -- if you only do one
core it will go badly).

ron

On Sun, Jul 26, 2015 at 3:40 AM Noah Vesely <fowlslegs at riseup.net> wrote:

> Thanks Ron! Took bit to get back to you because a Xen hypervisor update
> in Qubes seemed to put me in a boot loop. I just installed an Arch
> derivative because Arch has good support for this machine and I needed
> some type of test environment to actually run this command.
>
> Anyway, `rdmsr 0x3a` (think this is what you meant to type) returns 0. I
> guess this means all 3 bits are not set in the IA32_FEATURE_CONTROL MSR.
>
> This doesn't immediately make sense to me because (1) the output here
> seems to be telling me VT-x is not activated and the vmx cpu flag is
> present =><= and (2) I wrote in because `xl info` in Xen was reporting
> VT-x, but not VT-d, was activated and I was interested in how I could
> activate the former--isn't 0x3a unrelated to VT-d? Hopefully you can
> clarify this for me.
>
> Noah
>
> On 07/24/2015 11:25 PM, ron minnich wrote:
> > what does rdmsr 0 0x3a show you?
> >
> > ron
> >
> > On Fri, Jul 24, 2015 at 10:06 PM Noah Vesely <fowlslegs at riseup.net>
> wrote:
> >
> >> I've been trying to get VT-d working on John Lewis's build for the 2015
> >> Pixel (samus). You can see our conversation at
> >> https://plus.google.com/116173342884039282107/posts/TGA4EXYQMfq and I
> >> have also pasted it below. So far, I haven't got anywhere, so I thought
> >> I would try asking you all as well.
> >>
> >> Thanks,
> >> Noah
> >>
> >> &%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#&%$#
> >>
> >> Noah Vesely
> >>    -  Jul 16, 2015
> >>
> >> Is it possible to get Intel VT-d working on the Chromebook Pixel 2/
> >> Samus? The i7-5600U processor does support it.?
> >> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz)
> >> ark.intel.com
> >> ARK | Intel? Core? i7-5600U Processor (4M Cache, up to 3.20 GHz) quick
> >> reference guide including specifications, features, pricing,
> >> compatibility, design documentation, ordering codes, spec codes and
> more.
> >> John Lewis's profile photoNoah Vesely's profile photo
> >> 10 comments
> >> John Lewis
> >> Jul 18, 2015
> >>
> >>
> >>
> >>
> >> AFAIK, none of the hardware VT extensions are disabled in the firmware
> >> on Samus. Have you tried it??
> >> Noah Vesely
> >> Jul 18, 2015
> >>
> >>
> >>
> >>
> >> Yes. VT-x was enable while VT-d was not.?
> >> John Lewis
> >> Jul 18, 2015
> >>
> >>
> >>
> >>
> >> Clone
> >>
> >>
> https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-samus-6300.B
> >> and run menuconfig to see if there's an option for VT-d.?
> >> Noah Vesely
> >> Jul 19, 2015
> >>
> >>
> >>
> >>
> >> I can't figure out how to checkout this repository. I cloned the main
> >> third_part/coreboot repo then checked out the broadwell branch, but
> >> could not find the same directory you linked. Maybe my git fu could use
> >> some work.?
> >> John Lewis
> >> Jul 20, 2015
> >>
> >>
> >>
> >>
> >> Use the last chunk of the URL as the branch argument i.e. "-b
> >> firmware-samus-6300.B".?
> >> Noah Vesely
> >> Jul 20, 2015
> >>
> >>
> >>
> >>
> >> Nothing in menuconfig, however, I found the line `#define CONFIG_IOMMU
> >> 0` in ./build/config.h. I also found `#define CONFIG_ENABLE_VMX 0`.?
> >> John Lewis
> >> Jul 21, 2015
> >>
> >>
> >>
> >>
> >> VMX is already enabled in the firmware. IOMMU is unrelated. I would have
> >> to conclude that VT'd is either not supported by that CPU or something
> >> more needs to be done in coreboot to get it to work.?
> >> Noah Vesely
> >> Jul 21, 2015
> >>
> >>
> >>
> >>
> >> VT-d is supported by this CPU. See original link to Intel Ark.
> >>
> >> VT-d is Intel's specification for their IOMMU technology, so I don't see
> >> how it's unrelated.?
> >> John Lewis
> >> Jul 21, 2015
> >>
> >>
> >>
> >>
> >> Take a look at the .config from a shellball ROM (you can extract it
> >> using cbfstool).
> >>
> >>
> https://johnlewis.ie/extracting-the-shell-ball-rom-using-a-chromeos-image/
> >> ?
> >> Noah Vesely
> >> 9:15 PM
> >>
> >>
> >>
> >>
> >> I don't see anything relevant to VT-d; no VT-d keywords (e.g., iommu,
> >> vt, vmx, hvm, and directio).
> >>
> >> http://paste.debian.net/hidden/08ac8494/?
> >>
> >> --
> >> coreboot mailing list: coreboot at coreboot.org
> >> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150726/05548fe0/attachment.html>

From karl at xtronics.com  Mon Jul 27 19:19:50 2015
From: karl at xtronics.com (Karl Schmidt)
Date: Mon, 27 Jul 2015 12:19:50 -0500
Subject: [coreboot] Dead links - missing information?
Message-ID: <55B66836.6040008@xtronics.com>

This page has several dead links and I was unable to find a single coreboot server motherboard for 
sale after following the links.

http://www.coreboot.org/Products

I think I understand why this is happening.

-- 
--------------------------------------------------------------------------------
Link to our website and get free US-48 shipping on your next order.

Karl Schmidt                                  EMail Karl at xtronics.com
Transtronics, Inc.                              WEB https://secure.transtronics.com
3209 West 9th Street                             Ph (785) 841-3089
Lawrence, KS 66049                              FAX (785) 841-3089

The men the American people admire most extravagantly are the greatest liars: the men they detest 
most violently are those who try to tell them the truth.? H.L. Mencken

--------------------------------------------------------------------------------


From mytbk920423 at gmail.com  Tue Jul 28 16:26:29 2015
From: mytbk920423 at gmail.com (Iru Cai)
Date: Tue, 28 Jul 2015 22:26:29 +0800
Subject: [coreboot] coreboot for vexpress-v9 qemu failed
Message-ID: <CALWv5jTvSFpMzBDw3bnjk1wO7hTUZX+4em8-W2b4Zs+iKesDuw@mail.gmail.com>

Hi,

I am using QEMU from Arch Linux x86_64 official repo. I need to test my
built u-boot payload, so I tried to build a QEMU ARM coreboot image.
However, it failed to run and had the following output.

qemu: fatal: Trying to execute code outside RAM or ROM at 0xfffffffe

R00=00000000 R01=00011b70 R02=00000000 R03=ffffffff
R04=00c51878 R05=00000147 R06=00000000 R07=00000000
R08=00000000 R09=00000000 R10=00000000 R11=00000000
R12=00000002 R13=000fffd8 R14=ffffffff R15=fffffffe
PSR=600000ff -ZC- T sys32
s00=00000000 s01=00000000 d00=0000000000000000
s02=00000000 s03=00000000 d01=0000000000000000
s04=00000000 s05=00000000 d02=0000000000000000
s06=00000000 s07=00000000 d03=0000000000000000
s08=00000000 s09=00000000 d04=0000000000000000
s10=00000000 s11=00000000 d05=0000000000000000
s12=00000000 s13=00000000 d06=0000000000000000
s14=00000000 s15=00000000 d07=0000000000000000
s16=00000000 s17=00000000 d08=0000000000000000
s18=00000000 s19=00000000 d09=0000000000000000
s20=00000000 s21=00000000 d10=0000000000000000
s22=00000000 s23=00000000 d11=0000000000000000
s24=00000000 s25=00000000 d12=0000000000000000
s26=00000000 s27=00000000 d13=0000000000000000
s28=00000000 s29=00000000 d14=0000000000000000
s30=00000000 s31=00000000 d15=0000000000000000
s32=00000000 s33=00000000 d16=0000000000000000
s34=00000000 s35=00000000 d17=0000000000000000
s36=00000000 s37=00000000 d18=0000000000000000
s38=00000000 s39=00000000 d19=0000000000000000
s40=00000000 s41=00000000 d20=0000000000000000
s42=00000000 s43=00000000 d21=0000000000000000
s44=00000000 s45=00000000 d22=0000000000000000
s46=00000000 s47=00000000 d23=0000000000000000
s48=00000000 s49=00000000 d24=0000000000000000
s50=00000000 s51=00000000 d25=0000000000000000
s52=00000000 s53=00000000 d26=0000000000000000
s54=00000000 s55=00000000 d27=0000000000000000
s56=00000000 s57=00000000 d28=0000000000000000
s58=00000000 s59=00000000 d29=0000000000000000
s60=00000000 s61=00000000 d30=0000000000000000
s62=00000000 s63=00000000 d31=0000000000000000
FPSCR: 00000000

After I add '-S -s' option to QEMU, I found the problem is in
bootblock_simple.c, and the `main()' function in gdb is:

0x00000192 in ?? ()
=> 0x00000192:    08 b5    push    {r3, lr}
(gdb) disas $pc,+50
Dump of assembler code from 0x192 to 0x1c4:
=> 0x00000192:    push    {r3, lr}
   0x00000194:    bl    0x1704
   0x00000198:    bl    0x18c
   0x0000019c:    bl    0xd10
   0x000001a0:    bl    0x634
   0x000001a4:    bl    0x18e
   0x000001a8:    bl    0x190
   0x000001ac:    ldmia.w    sp!, {r3, lr}
   0x000001b0:    b.w    0x159c
   0x000001b4:    push    {r3, lr}
   0x000001b6:    mrc    15, 0, r3, cr1, cr0, {0}
   0x000001ba:    lsls    r2, r3, #29
   0x000001bc:    bpl.n    0x1c4
   0x000001be:    bl    0x2ac
   0x000001c2:    b.n    0x1cc
End of assembler dump.
(gdb) si
0x00000194 in ?? ()
=> 0x00000194:    01 f0 b6 fa    bl    0x1704
(gdb) b *0x198
Breakpoint 3 at 0x198
(gdb) c
Continuing.

Breakpoint 3, 0x00000198 in ?? ()
=> 0x00000198:    ff f7 f8 ff    bl    0x18c
(gdb) b *0x19c
Breakpoint 4 at 0x19c
(gdb) c
Continuing.

Breakpoint 4, 0x0000019c in ?? ()
=> 0x0000019c:    00 f0 b8 fd    bl    0xd10
(gdb) b *0x1a0
Breakpoint 5 at 0x1a0
(gdb) c
Continuing.
Remote connection closed

So there may be something wrong when setting up the console, however I'm
not so familiar with debugging the ROM so I don't know which function call
raise the problem.

Thanks,
Iru
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150728/938d7292/attachment.html>

From pgeorgi at google.com  Wed Jul 29 20:45:45 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Wed, 29 Jul 2015 20:45:45 +0200
Subject: [coreboot] coreboot changelog - Week of 2015-07-20
Message-ID: <CAE-gjdWScvjS=U22yxWQGvAYr0F9DGANgBHUz+R_8ApR-6kHvA@mail.gmail.com>

(This covers commits 406effd5 up to commit ef0158ec)

Apart from adding the google/glados board, this week?s activity
concentrated on bug fixes in chipsets and mainboards, spanning AMD K8 and
Hudson, Intel Sandy Bridge, Braswell and Skylake, Nvidia Tegra, Rockchip
RK3288 and RISC-V. Most of the changes are too small individually and too
spread out across the code base for a shout-out (or this report becomes
just a fancy kind of ?git log?), but two changes stand out:

Native RAM init on Sandybridge gained support for multiple DIMMs on the
same channel, further improving the reverse engineered code base for that
chipset.

To improve Skylake support, our 8250mem serial port driver now also
supports Skylake's 32bit UART access mode. This may also be useful when
reducing code duplication in our serial console drivers (such as on ARM
SoCs).


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150729/7219a009/attachment.html>

From wordpress at blogs.coreboot.org  Tue Jul 28 18:22:59 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Tue, 28 Jul 2015 16:22:59 +0000
Subject: [coreboot] =?utf-8?q?New_on_blogs=2Ecoreboot=2Eorg=3A_=5BGSoC=5D_?=
	=?utf-8?q?coreboot_for_ARM64_Qemu_=E2=80=93_Week_=237?=
Message-ID: <af25a2b87a04d414c6de81d6d418bad4@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150728/208611e1/attachment.html>

From wordpress at blogs.coreboot.org  Wed Jul 29 03:25:38 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Wed, 29 Jul 2015 01:25:38 +0000
Subject: [coreboot] New on blogs.coreboot.org: [GSoC] EC/H8S firmware week
	#7|#8
Message-ID: <0c820aa55118b9b2fcf0773fbe32d8d9@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150729/94276887/attachment.html>

From peter90609 at gmail.com  Wed Jul 29 16:04:41 2015
From: peter90609 at gmail.com (Yu-Cheng Liu)
Date: Wed, 29 Jul 2015 22:04:41 +0800
Subject: [coreboot] Suggestion about motherboard that implement coreboot ?
Message-ID: <CACS=nFN49A5KOon87SZQFJ4iNoAH0boz_-S0DnAYAJL2QY+8wA@mail.gmail.com>

hello,
I want to trigger the SMI/SMM in the coreboot,and burn it on the
motherboard
what kind of motherboard is suggest to use?
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150729/e9d36450/attachment.html>

From wordpress at blogs.coreboot.org  Wed Jul 29 20:45:42 2015
From: wordpress at blogs.coreboot.org (WordPress)
Date: Wed, 29 Jul 2015 18:45:42 +0000
Subject: [coreboot] New on blogs.coreboot.org: coreboot changelog - Week of
	2015-07-20
Message-ID: <0a0283bd86d182170c4f2b8042851794@blogs.coreboot.org>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150729/fad45dea/attachment.html>

From pgeorgi at google.com  Wed Jul 29 20:54:24 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Wed, 29 Jul 2015 20:54:24 +0200
Subject: [coreboot] Dead links - missing information?
In-Reply-To: <55B66836.6040008@xtronics.com>
References: <55B66836.6040008@xtronics.com>
Message-ID: <CAE-gjdUNF3GwC3QB=Se+86fa6s76WYU6Kpav8zgRccUnrvXJGw@mail.gmail.com>

2015-07-27 19:19 GMT+02:00 Karl Schmidt <karl at xtronics.com>:

> This page has several dead links and I was unable to find a single
> coreboot server motherboard for sale after following the links.
>
> http://www.coreboot.org/Products

Thanks, I cleaned up at least the dead links on that page.
We'll need to decide what it is supposed to cover before that page becomes
really useful again. For example, Chromebooks are pretty much not covered,
despite being the most easily available device on the market that runs
coreboot.

One server board that is for sale and can be equipped with coreboot would
be the ASUS KGPE-D16.


Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150729/131a8fac/attachment.html>

From c-d.hailfinger.devel.2006 at gmx.net  Thu Jul 30 14:01:02 2015
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 30 Jul 2015 14:01:02 +0200
Subject: [coreboot] coreboot conference in Europe, October 2015
Message-ID: <55BA11FE.3040505@gmx.net>

Dear coreboot developers, users and interested parties,

we are currently trying to organize a coreboot conference and developer
meeting in October 2015 in Germany.

This is not intended to be a pure developer meeting, we also hope to
reach out to manufacturers of processors, chipsets, mainboards and
servers/laptops/tablets/desktops with an interest in coreboot and the
possibilities it offers.

My plan (which is not final yet) is to have the Federal Office for
Information Security (BSI) in Germany host the conference in Bonn,
Germany. As a national cyber security authority, the goal of the BSI is
to promote IT security in Germany. For this reason, the BSI has funded
coreboot development in the past for security reasons.

The preliminary plans are to coordinate the exact date of the conference
to be before or after Embedded Linux Conference Europe, scheduled for
October 5-7 in Dublin, Ireland. Planned duration is 3-4 days. This means
we can either use the time window from Thursday Oct 1 to Sunday Oct 4,
or from Thursday Oct 8 to Monday Oct 12. The former has the advantage of
having cheaper hotel rooms available in Bonn, while the latter has the
advantage of avoiding Oct 3, a national holiday in Germany (all shops
closed).

ATTENTION vendors/manufacturers: If your main interest is forging
business relationships and/or strategic coordination and you want to
skip the technical workshops and soldering, we'll try make sure there is
one outreach day of talks, presentations and discussions on a regular
business day. Please indicate that with "(strategic)" next to your name
in the doodle linked below.

If you wonder about how to reach Bonn, there are three options available
by plane:
The closest is Cologne Airport (CGN), 30 minutes by bus to Bonn main
station.
Next is D?sseldorf Airport (DUS), 1 hour by train to Bonn main station.
The airport with most international destinations is Frankfurt Airport
(FRA), 2.5 hours by train to Bonn main station.
There's the option to travel by train as well. Bonn is reachable by
high-speed train (ICE), and other high-speed train stations are
reasonably close (30 minutes).

What I'm looking for right now is a rough show of hands who'd like to
attend so I can book a conference venue. I'd also like feedback on which
weekend would be preferable for you. If you have any questions, please
feel free to ask me directly <c-d.hailfinger.devel.2006 at gmx.net> or our
mailing list <coreboot at coreboot.org>.

Please enter your participation abilities in the doodle below:
http://doodle.com/bw52xs4fc7pxte6d

Regards,
Carl-Daniel Hailfinger


From marcj303 at gmail.com  Thu Jul 30 16:18:41 2015
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 30 Jul 2015 14:18:41 +0000
Subject: [coreboot] Suggestion about motherboard that implement coreboot
	?
In-Reply-To: <CACS=nFN49A5KOon87SZQFJ4iNoAH0boz_-S0DnAYAJL2QY+8wA@mail.gmail.com>
References: <CACS=nFN49A5KOon87SZQFJ4iNoAH0boz_-S0DnAYAJL2QY+8wA@mail.gmail.com>
Message-ID: <CALrs_3hbXSRa2M9RpJrUX3gyF_i6dsk+9N5_vfa-=4=PtUudoA@mail.gmail.com>

Hi,

I recommend that you read the smi section of the datasheet for your
specific cpu/chipset and learn how that works and how you can trigger an
smi.

Regards,
Marc

On Thu, Jul 30, 2015, 2:47 AM Yu-Cheng Liu <peter90609 at gmail.com> wrote:

> hello,
> I want to trigger the SMI/SMM in the coreboot,and burn it on the
> motherboard
> what kind of motherboard is suggest to use?
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150730/168d3939/attachment.html>

From pgeorgi at google.com  Fri Jul 31 20:07:37 2015
From: pgeorgi at google.com (Patrick Georgi)
Date: Fri, 31 Jul 2015 20:07:37 +0200
Subject: [coreboot] ANN: Test builder change
Message-ID: <CAE-gjdUFr9DBWvDZRbvA0LOHaTaDrF4pLW-h75mbhL8xZO8JSA@mail.gmail.com>

Hi all,

I just changed the "coreboot" builder on http://qa.coreboot.org/ to use the
just fixed "what-jenkins-does" build target (defined in
$(top)/Makefile.inc), so all future builds will use that instead of the
hard coded sequence of commands that used to be defined in our build
environment.

I plan to move the "coreboot-gerrit" builder over in about a week. This
means that from that point on, contributions on gerrit that predate the
inclusion of http://review.coreboot.org/#/c/11097/ will break.

Therefore if you have long-running development branches, please remember to
rebase them to a current upstream or you'll get a build error after pushing
them.


Thanks,
Patrick
-- 
Google Germany GmbH, ABC-Str. 19, 20354 Hamburg
Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft:
Hamburg
Gesch?ftsf?hrer: Graham Law, Christine Elizabeth Flores
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20150731/23f6b478/attachment.html>