[coreboot] HPET: Minimum Clock Ticks and HPET_MIN_TICKS
Paul Menzel
paulepanter at users.sourceforge.net
Sat Jan 30 14:29:03 CET 2016
Dear coreboot folks,
thanks to Timothy Pearson’s patch set #13159 (southbridge/amd/sb700:
Set HPET min tick value to RPR recommendation) [1] I became aware of
the Kconfig option `HPET_MIN_TICKS`.
It looks like quite some boards (southbridges) don’t set it and it then
gets set to 0 in `src/arch/x86/acpi.c`.
```
509 void acpi_create_hpet(acpi_hpet_t *hpet)
510 {
511 acpi_header_t *header = &(hpet->header);
512 acpi_addr_t *addr = &(hpet->addr);
513
514 memset((void *)hpet, 0, sizeof(acpi_hpet_t));
515
516 /* Fill out header fields. */
517 memcpy(header->signature, "HPET", 4);
518 memcpy(header->oem_id, OEM_ID, 6);
519 memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
520 memcpy(header->asl_compiler_id, ASLC, 4);
521
522 header->length = sizeof(acpi_hpet_t);
523 header->revision = 1; /* Currently 1. Table added in ACPI 2.0. */
524
525 /* Fill out HPET address. */
526 addr->space_id = 0; /* Memory */
527 addr->bit_width = 64;
528 addr->bit_offset = 0;
529 addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff;
530 addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32;
531
532 hpet->id = *(unsigned int*)CONFIG_HPET_ADDRESS;
533 hpet->number = 0;
534 hpet->min_tick = CONFIG_HPET_MIN_TICKS;
535
536 header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
537 }
```
That’s the case on the ASRock E350M1.
```
$ more /tmp/hpet.dsl
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20160108-32
* Copyright (c) 2000 - 2016 Intel Corporation
*
* Disassembly of hpet.dat, Sat Jan 30 12:37:21 2016
*
* ACPI Data Table [HPET]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
[004h 0004 4] Table Length : 00000038
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : 71
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] Hardware Block ID : 43538210
[028h 0040 12] Timer Block Register : [Generic Address Structure]
[028h 0040 1] Space ID : 00 [SystemMemory]
[029h 0041 1] Bit Width : 40
[02Ah 0042 1] Bit Offset : 00
[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
[02Ch 0044 8] Address : 00000000FED00000
[034h 0052 1] Sequence Number : 00
[035h 0053 2] Minimum Clock Ticks : 0000
[037h 0055 1] Flags (decoded below) : 00
4K Page Protect : 0
64K Page Protect : 0
Raw Table Data: Length 56 (0x38)
0000: 48 50 45 54 38 00 00 00 01 71 43 4F 52 45 20 20 // HPET8....qCORE
0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE
0020: 00 00 00 00 10 82 53 43 00 40 00 00 00 00 D0 FE // ......SC. at ......
0030: 00 00 00 00 00 00 00 00 // ........
```
As Timothy did, I guess this should be fixed. How should that be done?
1. Define a default value in `src/arch/x86/Kconfig` similar to
`HPET_ADDRESS` and allow an override `HPET_MIN_TICKS_OVERRIDE`?
2. Or does this need to be set in every southbridge?
Thanks,
Paul
[1] https://review.coreboot.org/13159
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