Ahhh thanks yh, this will come in handy :)<br>
<br>
-san<br>
<br><br><div><span class="gmail_quote">On 12/14/05, <b class="gmail_sendername">yhlu</b> <<a href="mailto:yinghailu@gmail.com">yinghailu@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
San,<br><br>this is for you. You can disassembly code with HDT at CAR stage now..<br><br>YH<br><br>---------- Forwarded message ----------<br>From: <a href="mailto:svn@openbios.org">svn@openbios.org</a> <<a href="mailto:svn@openbios.org">
svn@openbios.org</a>><br>Date: Dec 14, 2005 12:08 PM<br>Subject: [linuxbios-checkins] r2143 - trunk/LinuxBIOSv2/src/cpu/amd/car<br>To: <a href="mailto:linuxbios-checkins@openbios.org">linuxbios-checkins@openbios.org</a>
<br><br><br>Author: yhlu<br>Date: 2005-12-14 21:08:23 +0100 (Wed, 14 Dec 2005)<br>New Revision: 2143<br><br>Modified:<br> trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc<br>Log:<br>support HDT disassembly when cache as ram auto stage
<br><br><br>Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc<br>===================================================================<br>--- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2005-12-14<br>02:39:33 UTC (rev 2142)
<br>+++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2005-12-14<br>20:08:23 UTC (rev 2143)<br>@@ -1,5 +1,6 @@<br> /* by yhlu 6.2005 */<br>-/* We will use 4K bytes only */<br>+/* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly,
<br>please select the PCI Bus mem for Phys Type*/<br>+/* We may need 4K bytes only */<br> #define CacheSize DCACHE_RAM_SIZE<br> #define CacheBase (0xd0000 - CacheSize)<br><br>@@ -12,9 +13,9 @@<br> /*for normal part %ebx already contain cpu_init_detected from
<br>fallback call */<br><br> cache_as_ram_setup:<br>+<br> /* hope we can skip the double set for normal part */<br> #if USE_FALLBACK_IMAGE == 1<br>-<br> /* check if cpu_init_detected */<br> movl $MTRRdefType_MSR, %ecx
<br> rdmsr<br>@@ -22,9 +23,6 @@<br> movl %eax, %ebx /* We store the status */<br><br> /* Set MtrrFixDramModEn for clear fixed mtrr */<br>- xorl %eax, %eax<br>- xorl %edx, %edx<br>-<br>
enable_fixed_mtrr_dram_modify:<br> movl $SYSCFG_MSR, %ecx<br> rdmsr<br>@@ -32,13 +30,6 @@<br> orl $SYSCFG_MSR_MtrrFixDramModEn, %eax<br> wrmsr<br><br>- /* Set the default memory type and enable fixed and variable MTRRs */
<br>- movl $MTRRdefType_MSR, %ecx<br>- xorl %edx, %edx<br>- /* Enable Variable and Fixed MTRRs */<br>- movl $0x00000c00, %eax<br>- wrmsr<br>-<br> /*Clear all MTRRs */<br>
<br> xorl %edx, %edx<br>@@ -55,12 +46,6 @@<br> jmp clear_fixed_var_mtrr<br> clear_fixed_var_mtrr_out:<br><br>- /* Enable the MTRRs and IORRs in SYSCFG */<br>- movl $SYSCFG_MSR, %ecx<br>
- rdmsr<br>- orl
$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax<br>- wrmsr<br>-<br> #if CacheSize == 0x10000<br> /* enable caching for 64K using fixed mtrr */<br> movl $0x268, %ecx /* fix4k_c0000*/
<br>@@ -69,31 +54,34 @@<br> wrmsr<br> movl $0x269, %ecx<br> wrmsr<br>-#endif<br>+#else<br><br>-#if CacheSize == 0x8000<br>+ #if CacheSize == 0x8000<br> /* enable caching for 32K using fixed mtrr */
<br> movl $0x269, %ecx /* fix4k_c8000*/<br> movl $0x06060606, %eax /* WB IO type */<br> movl %eax, %edx<br> wrmsr<br>-#endif<br>+ #else<br><br> /* enable caching for 16K/8K/4K using fixed mtrr */
<br> movl $0x269, %ecx /* fix4k_cc000*/<br>-#if CacheSize == 0x4000<br>+ #if CacheSize == 0x4000<br> movl $0x06060606, %edx /* WB IO type */<br>-#endif<br>-#if CacheSize == 0x2000<br>+ #endif<br>
+ #if CacheSize == 0x2000<br> movl $0x06060000, %edx /* WB IO type */<br>-#endif<br>-#if CacheSize == 0x1000<br>+ #endif<br>+ #if CacheSize == 0x1000<br> movl $0x06000000, %edx /* WB IO type */
<br>-#endif<br>+ #endif<br> xorl %eax, %eax<br> wrmsr<br>+ #endif<br><br>- /* enable memory access for 0 - 1MB using top_mem */<br>+#endif<br>+<br>+ /* enable memory access for first MBs using top_mem */
<br> movl $TOP_MEM, %ecx<br> xorl %edx, %edx<br>
movl $(((CONFIG_LB_MEM_TOPK << 10) +
TOP_MEM_MASK) &<br>~TOP_MEM_MASK) , %eax<br>@@ -101,7 +89,6 @@<br> #endif /* USE_FALLBACK_IMAGE == 1*/<br><br> #if USE_FALLBACK_IMAGE == 0<br>-<br> /* disable cache */<br> movl %cr0, %eax<br> orl $(0x1<<30),%eax
<br>@@ -119,11 +106,26 @@<br> wrmsr<br><br> movl $0x203, %ecx<br>- movl $0x0000000f, %edx<br>+ movl $0x0000000f, %edx /* AMD 40 bit */<br> movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
<br> wrmsr<br> #endif /* XIP_ROM_SIZE && XIP_ROM_BASE */<br><br>+#if USE_FALLBACK_IMAGE == 1<br>+ /* Set the default memory type and enable fixed and variable MTRRs */<br>+ movl $MTRRdefType_MSR, %ecx
<br>+ xorl %edx, %edx<br>+ /* Enable Variable and Fixed MTRRs */<br>+ movl $0x00000c00, %eax<br>+ wrmsr<br>+<br>+ /* Enable the MTRRs and IORRs in SYSCFG */<br>+ movl $SYSCFG_MSR, %ecx
<br>+ rdmsr<br>+ orl
$(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax<br>+ wrmsr<br>+#endif<br>+<br> /* enable cache */<br> movl %cr0, %eax<br> andl $0x9fffffff,%eax<br>@@ -132,23 +134,22 @@<br>
#if USE_FALLBACK_IMAGE == 1<br><br> /* Read the range with lodsl*/<br>- movl $(CacheBase+CacheSize-4), %esi<br>- std<br>+ cld<br>+ movl $CacheBase, %esi<br> movl $(CacheSize>>2), %ecx
<br> rep lodsl<br> /* Clear the range */<br>- movl $(CacheBase+CacheSize-4), %edi<br>+ movl $CacheBase, %edi<br> movl $(CacheSize>>2), %ecx<br> xorl %eax, %eax
<br> rep stosl<br><br> #endif /*USE_FALLBACK_IMAGE == 1*/<br><br>-<br>+ /* set up the stack pointer */<br> movl $(CacheBase+CacheSize-4), %eax<br> movl %eax, %esp<br><br>-<br> /* Restore the BIST result */
<br> movl %ebp, %eax<br> /* We need to set ebp ? No need */<br><br><br>--<br> To unsubscribe send an email to<br><a href="mailto:linuxbios-checkins+unsubscribe@openbios.org">linuxbios-checkins+unsubscribe@openbios.org
</a><br></blockquote></div><br>