diff -r -u -b -B LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c kreebiste/LinuxBIOS/src/cpu/amd/model_lx/model_lx_init.c
--- LinuxBIOSv2/src/cpu/amd/model_lx/model_lx_init.c	2006-08-02 14:30:32.000000000 +0300
+++ kreebiste/LinuxBIOS/src/cpu/amd/model_lx/model_lx_init.c	2006-08-02 19:49:46.000000000 +0300
@@ -5,7 +5,6 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
-#include <cpu/amd/lxdef.h>
 
 static void vsm_end_post_smi(void)
 {
@@ -19,37 +18,10 @@
 
 static void model_lx_init(device_t dev)
 {
-	
-	msr_t msr;
-	
 	printk_debug("model_lx_init\n");
 
 	/* Turn on caching if we haven't already */
 	
-	/* Instruction Memory Configuration register
-	 * set EBE bit, required when L2 cache is enabled
-	 */ 
-	msr = rdmsr(CPU_IM_CONFIG);
-	msr.lo |= 0x400;
-	wrmsr(CPU_IM_CONFIG, msr);
-	
-	/* Data Memory Subsystem Configuration register
-	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
-	 */
-	msr = rdmsr(CPU_DM_CONFIG0);
-	msr.lo |= 0x4000;
-	wrmsr(CPU_DM_CONFIG0, msr);
-
-	/* invalidate L2 cache */
-	msr.hi = 0x00;
-	msr.lo = 0x10;
-	wrmsr(L2_CONFIG_MSR, msr);
-
-	/* Enable L2 cache */	
-	msr.hi = 0x00;
-	msr.lo = 0x0f;	
-	wrmsr(L2_CONFIG_MSR, msr);
-	
 	x86_enable_cache();
 
 	/* Enable the local cpu apics */
diff -r -u -b -B LinuxBIOSv2/src/include/cpu/amd/lxdef.h kreebiste/LinuxBIOS/src/include/cpu/amd/lxdef.h
--- LinuxBIOSv2/src/include/cpu/amd/lxdef.h	2006-08-02 14:30:32.000000000 +0300
+++ kreebiste/LinuxBIOS/src/include/cpu/amd/lxdef.h	2006-08-02 18:17:31.000000000 +0300
@@ -264,6 +264,10 @@
 #define		RCONF_DMM_LOWER_RCNORM_SHIFT			0
 #define		RCONF_DMM_LOWER_EN_SET					(1<<8)
 
+
+
+/*  ----- GX3 OK  ----  */
+
 #define	CPU_RCONF0							0x1810
 #define	CPU_RCONF1							0x1811
 #define	CPU_RCONF2							0x1812
@@ -272,10 +276,20 @@
 #define	CPU_RCONF5							0x1815
 #define	CPU_RCONF6							0x1816
 #define	CPU_RCONF7							0x1817
+
+/* ------------------------ */
+
+/*  ----- GX3 OK  ----  */
+
 #define	CPU_CR1_MSR							0x1881
 #define	CPU_CR2_MSR							0x1882
 #define	CPU_CR3_MSR							0x1883
 #define	CPU_CR4_MSR							0x1884
+
+/* ------------------------ */
+
+/*  ----- GX3 OK  ----  */
+
 #define	CPU_DC_INDEX						0x1890
 #define	CPU_DC_DATA							0x1891
 #define	CPU_DC_TAG							0x1892
@@ -285,6 +301,9 @@
 #define	CPU_DTB_LRU							0x1899
 #define	CPU_DTB_ENTRY						0x189A
 #define	CPU_DTB_ENTRY_I						0x189B
+
+/* ------------------------ */
+
 #define	CPU_L2TB_INDEX						0x189C
 #define	CPU_L2TB_LRU						0x189D
 #define	CPU_L2TB_ENTRY						0x189E

diff -r -u -b -B LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c kreebiste/LinuxBIOS/src/northbridge/amd/lx/northbridge.c
--- LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c	2006-07-28 19:06:16.000000000 +0300
+++ kreebiste/LinuxBIOS/src/northbridge/amd/lx/northbridge.c	2006-08-02 20:25:16.000000000 +0300
@@ -9,6 +9,7 @@
 #include <bitops.h>
 #include "chip.h"
 #include "northbridge.h"
+#include <cpu/cpu.h>
 #include <cpu/amd/lxdef.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
@@ -274,6 +275,38 @@
 	
 }
 
+
+static void enable_L2_cache(void) {
+	msr_t msr;
+
+	/* Instruction Memory Configuration register
+	 * set EBE bit, required when L2 cache is enabled
+	 */ 
+	msr = rdmsr(CPU_IM_CONFIG);
+	msr.lo |= 0x400;
+	wrmsr(CPU_IM_CONFIG, msr);
+	
+	/* Data Memory Subsystem Configuration register
+	 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
+	 */
+	msr = rdmsr(CPU_DM_CONFIG0);
+	msr.lo |= 0x4000;
+	wrmsr(CPU_DM_CONFIG0, msr);
+
+	/* invalidate L2 cache */
+	msr.hi = 0x00;
+	msr.lo = 0x10;
+	wrmsr(L2_CONFIG_MSR, msr);
+
+	/* Enable L2 cache */	
+	msr.hi = 0x00;
+	msr.lo = 0x0f;	
+	wrmsr(L2_CONFIG_MSR, msr);
+	
+	printk_debug("L2 cache enabled\n");
+}
+
+
 static void northbridge_init(device_t dev) 
 {
 	struct northbridge_amd_lx_config *nb = (struct northbridge_amd_lx_config *)dev->chip_info;
@@ -456,8 +489,9 @@
 		extern void cpubug(void);
 		printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_lx(), so we force the issue here */
+			enable_L2_cache();
 		northbridgeinit();
-		cpubug();	
+			/* cpubug();	GX3*/
 		chipsetinit(nb);
 		setup_lx();
 		/* do this here for now -- this chip really breaks our device model */

diff -r -u -b -B LinuxBIOSv2/src/northbridge/amd/lx/raminit.c kreebiste/LinuxBIOS/src/northbridge/amd/lx/raminit.c
--- LinuxBIOSv2/src/northbridge/amd/lx/raminit.c	2006-07-28 19:06:16.000000000 +0300
+++ kreebiste/LinuxBIOS/src/northbridge/amd/lx/raminit.c	2006-08-01 14:13:43.000000000 +0300
@@ -1,13 +1,10 @@
 #include <cpu/amd/lxdef.h>
 
-#if 0
+
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 }
 
-#endif
-
-
 /* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
  * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
 static void sdram_enable(int controllers, const struct mem_controller *ctrl)
