<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
<head>
<meta content="text/html;charset=ISO-8859-1" http-equiv="Content-Type">
</head>
<body bgcolor="#ffffff" text="#000000">
Richard Smith wrote:
<blockquote
cite="mid8a0c36780609061222q3b513172r37189dcf883cf0d4@mail.gmail.com"
type="cite">
<pre wrap="">On 9/6/06, Ronald G Minnich <a class="moz-txt-link-rfc2396E" href="mailto:rminnich@lanl.gov"><rminnich@lanl.gov></a> wrote:
</pre>
<blockquote type="cite">
<pre wrap="">I will attempt to get you a rom image of a working linuxbios rom
tonight. I have one.
</pre>
</blockquote>
<pre wrap=""><!---->
That would be a magic bullet. If we can boot that, dump the
northbridge settings and compare vs what LB is currently doing then we
know a _lot_. If they are the same then I think we have strong
evidence that something in the newer chips is different.
Please send it to "Alex Mauer" <a class="moz-txt-link-rfc2396E" href="mailto:hawke42@gmail.com"><hawke42@gmail.com></a> and cc me.
</pre>
</blockquote>
when I get another PSU I'll boot my board up with the original bios and
dump the northbridge settings.<br>
The board I am working on is rev D. I have another board in use as a
firewall and that is a rev A so I could possibly see if that works any
better or if there are any details.<br>
<br>
There are a couple of bits in the code I don't quite get. Also the
VT8601A datasheet mentions a BIOS porting guide. Does anyone have a
copy of that. The actual VT8601A datasheet doesn't go into any detail
on configuring ram. <br>
<br>
Have also been looking at an SDRAM datasheet to see how that gets
initialised. One of the bits I don't quite get is writing the SDRAM
mode register (either 0x150 or 0x1d0 ). Can't see how that matches up
to the SDRAM mode register bits and would'nt the MA mapping have an
effect on that. The MA mapping register doesn't get written until
later. <br>
<br>
<br>
Currently using v3 something of gcc will need to check, again when I
get a PSU.<br>
<br>
Ben<br>
<br>
<br>
<br>
</body>
</html>