# Each option used by a part must be defined in
#   define <name> 
#	comment "<string>"
# (i.e. will remain undefined) unless it has
# option is defined or set and the numeric result 
# A comment string must be supplied for every option.
define ARCH
	comment "Default architecture is i386, options are alpha and ppc"
define HAVE_MOVNTI
	comment "This cpu supports the MOVNTI directive"
define CROSS_COMPILE
	comment "Cross compiler prefix"
define CC
	comment "Target C Compiler"
define HOSTCC
	comment "Host C Compiler"
define CPU_OPT
	comment "Additional per-cpu CFLAGS"
define OBJCOPY
	comment "Objcopy command"
define LINUXBIOS_VERSION
	comment "LinuxBIOS version"
define LINUXBIOS_EXTRA_VERSION
        comment "LinuxBIOS extra version"
define LINUXBIOS_BUILD
	comment "Build date"
define LINUXBIOS_COMPILE_TIME
	comment "Build time"
define LINUXBIOS_COMPILE_BY
	comment "Who build this image"
define LINUXBIOS_COMPILE_HOST
	comment "Build host"
define LINUXBIOS_COMPILE_DOMAIN
	comment "Build domain name"
define LINUXBIOS_COMPILER
	comment "Build compiler"
define LINUXBIOS_LINKER
	comment "Build linker"
define LINUXBIOS_ASSEMBLER
	comment "Build assembler"
define CONFIG_CHIP_CONFIGURE
	comment "Use new chip_configure method for configuring (non-pci) devices"
define CONFIG_USE_INIT
	comment "Use stage 1 initialization code"
define HAVE_FALLBACK_BOOT
	comment "Set if fallback booting required"
define USE_FALLBACK_IMAGE
	comment "Set to build a fallback image"
define FALLBACK_SIZE
	comment "Default fallback image size"
define ROM_SIZE
	comment "Size of your ROM"
define ROM_IMAGE_SIZE
	comment "Default image size"
define ROM_SECTION_SIZE
	comment "Default rom section size"
define ROM_SECTION_OFFSET
	comment "Default rom section offset"
define PAYLOAD_SIZE
	comment "Default payload size"
define _ROMBASE
	comment "Base address of LinuxBIOS in ROM"
define _ROMSTART
	comment "Start address of LinuxBIOS in ROM"
define _RESET
	comment "Hardware reset vector address"
define _EXCEPTION_VECTORS
	comment "Address of exception vector table"
define STACK_SIZE
	comment "Default stack size"
define HEAP_SIZE
	comment "Default heap size"
define _RAMBASE
	comment "Base address of LinuxBIOS in RAM"
define _RAMSTART
	comment "Start address of LinuxBIOS in RAM"
define USE_DCACHE_RAM
	comment "Use data cache as temporary RAM if possible"
define DCACHE_RAM_BASE
	comment "Base address of data cache when using it for temporary RAM"
define DCACHE_RAM_SIZE
	comment "Size of data cache when using it for temporary RAM"
define DCACHE_RAM_GLOBAL_VAR_SIZE
	comment "Size of region that for global variable of cache as ram stage"
define XIP_ROM_BASE
	comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
define XIP_ROM_SIZE
	comment "Size of area to cache during LinuxBIOS execution directly from ROM"
define CONFIG_COMPRESS
	comment "Set for compressed image"
define CONFIG_UNCOMPRESSED
	comment "Set for uncompressed image"
define CONFIG_LB_MEM_TOPK
	comment "Kilobytes of memory to initialized before executing code from RAM"
define HAVE_OPTION_TABLE
	comment "Export CMOS option table"
define USE_OPTION_TABLE
	comment "Use option table"
define LB_CKS_RANGE_START
	comment "First CMOS byte to use for LinuxBIOS options"
define LB_CKS_RANGE_END
	comment "Last CMOS byte to use for LinuxBIOS options"
define LB_CKS_LOC
	comment "Pair of bytes to use for CMOS checksum"
define CRT0
	comment "Main initialization target"
define DEBUG
	comment "Enable debugging code"
define CONFIG_CONSOLE_VGA
	comment "Log messages to VGA"
define CONFIG_CONSOLE_VGA_MULTI
        comment "Multi VGA console"
define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
        comment "Use onboard VGA instead of add on VGA card"
define CONFIG_CONSOLE_BTEXT
        comment "Log messages to btext fb console"
define CONFIG_CONSOLE_LOGBUF
	comment "Log messages to buffer"
define CONFIG_CONSOLE_SROM
	comment "Log messages to SROM console"
define CONFIG_CONSOLE_SERIAL8250
	comment "Log messages to 8250 uart based serial console"
define DEFAULT_CONSOLE_LOGLEVEL
	comment "Console will log at this level unless changed"
define MAXIMUM_CONSOLE_LOGLEVEL
 	comment "Error messages up to this level can be printed"
define CONFIG_SERIAL_POST
	comment "Enable SERIAL POST codes"
define NO_POST
	comment "Disable POST codes"
define TTYS0_BASE
	comment "Base address for 8250 uart for the serial console"
define TTYS0_BAUD
	comment "Default baud rate for serial console"
define TTYS0_DIV
	comment "Allow UART divisor to be set explicitly"
define TTYS0_LCS
	comment "Default flow control settings for the 8250 serial console uart"
define MAINBOARD
	comment "Mainboard name"
define MAINBOARD_PART_NUMBER
	comment "Part number of mainboard"
define MAINBOARD_VENDOR
	comment "Vendor of mainboard"
define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
	comment "PCI Vendor ID of mainboard manufacturer"
define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
	comment "PCI susbsystem device id assigned my mainboard manufacturer"
define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
	comment "Default power on after power fail setting"
define CONFIG_SYS_CLK_FREQ
	comment "System clock frequency in MHz"
define CONFIG_MAX_PCI_BUSES
	comment "Maximum number of PCI buses to search for devices"
define CONFIG_SMP
	comment "Define if we support SMP"
define CONFIG_MAX_CPUS
        comment "Maximum CPU count for this machine"
define CONFIG_MAX_PHYSICAL_CPUS
        comment "Maximum physical CPU count for this machine"
define CONFIG_LOGICAL_CPUS
	comment "Should multiple cpus per die be enabled?"
define HAVE_MP_TABLE
	comment "Define to build an MP table"
define SERIAL_CPU_INIT
        comment "Serialize CPU init"
define APIC_ID_OFFSET
	comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
define ENABLE_APIC_EXT_ID
	comment "Enable APIC ext id mode 8 bit"
define LIFT_BSP_APIC_ID
	comment "decide if we lift bsp apic id while ap apic id"
define CONFIG_IDE_STREAM
	comment "Boot from IDE device"
define CONFIG_ROM_STREAM
	comment "Boot image is located in ROM" 
define CONFIG_ROM_STREAM_START
	comment "ROM stream start location"
define CONFIG_COMPRESSED_ROM_STREAM
	comment "compressed boot image is located in ROM and is assumed to be NRV2B (deprecated)" 
define CONFIG_COMPRESSED_ROM_STREAM_NRV2B
	comment "NRV2B compressed boot image is located in ROM" 
define CONFIG_COMPRESSED_ROM_STREAM_LZMA
	comment "LZMA compressed boot image is located in ROM" 
define CONFIG_PRECOMPRESSED_ROM_STREAM
	comment "boot image is already compressed" 
define CONFIG_FS_STREAM
	comment "Boot from a filesystem"
define CONFIG_FS_EXT2
	comment "Enable ext2 filesystem support"
define CONFIG_FS_ISO9660
	comment "Enable ISO9660 filesystem support"
define CONFIG_FS_FAT
	comment "Enable FAT filesystem support"
define AUTOBOOT_DELAY
	comment "Delay (in seconds) before autobooting"
define AUTOBOOT_CMDLINE
	comment "Default command line when autobooting"
define USE_WATCHDOG_ON_BOOT
	comment "Use the watchdog on booting"
define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
	comment "Enable support for plugin Hypertransport busses"
define CONFIG_AGP_PLUGIN_SUPPORT
	comment "Enable support for plugin AGP busses"
define CONFIG_CARDBUS_PLUGIN_SUPPORT
	comment "Enable support cardbus plugin cards"
define CONFIG_PCIX_PLUGIN_SUPPORT
	comment "Enable support for plugin PCI-X busses"
define CONFIG_PCIEXP_PLUGIN_SUPPORT
	comment "Enable support for plugin PCI-E busses"
define HAVE_PIRQ_TABLE
	comment "Define if we have a PIRQ table"
define IRQ_SLOT_COUNT
	comment "Number of IRQ slots"
define CONFIG_PCIBIOS_IRQ
	comment "PCIBIOS IRQ support"
define CONFIG_IOAPIC
	comment "IOAPIC support"
define CONFIG_IDE
	comment "Define to include IDE support"
define IDE_BOOT_DRIVE
	comment "Disk number of boot drive"
define IDE_SWAB
	comment "Swap bytes when reading from IDE device"
define IDE_OFFSET
	comment "Sector at which to start searching for boot image"
define PCIC0_CFGADDR
	comment "Address of PCI Configuration Address Register"
define PCIC0_CFGDATA
	comment "Address of PCI Configuration Data Register"
define ISA_IO_BASE
	comment "Base address of PCI/ISA I/O address range"
define ISA_MEM_BASE
	comment "Base address of PCI/ISA memory address range"
define PNP_CFGADDR
	comment "PNP Configuration Address Register offset"
define PNP_CFGDATA
	comment "PNP Configuration Data Register offset"
define _IO_BASE
	comment "Base address of memory mapped I/O operations"
define EMBEDDED_RAM_SIZE
	comment "Embedded boards generally have fixed RAM size"
define CONFIG_CHIP_NAME
	comment "Compile in the chip name"
define CONFIG_GDB_STUB
	comment "Compile in gdb stub support?"
define HAVE_INIT_TIMER
	comment "Have a init_timer function"
define HAVE_HARD_RESET
	comment "Have hard reset"
define MEMORY_HOLE
	comment "Set to deal with memory hole"
define MAX_REBOOT_CNT
	comment "Set maximum reboots"
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
	comment "Use timer2 to callibrate the x86 time stamp counter"
define INTEL_PPRO_MTRR
	comment ""
define CONFIG_UDELAY_TSC
	comment "Implement udelay with the x86 time stamp counter"
define CONFIG_UDELAY_IO
	comment "Implement udelay with x86 io registers"
define FAKE_SPDROM
	comment "Use this to fake spd rom values"
define HAVE_ACPI_TABLES
	comment "Define to build ACPI tables"
define ACPI_SSDTX_NUM
	comment "extra ssdt num for PCI Device"
define AGP_APERTURE_SIZE
	comment "AGP graphics virtual memory aperture size"
define HT_CHAIN_UNITID_BASE
	comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
define HT_CHAIN_END_UNITID_BASE
        comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
define SB_HT_CHAIN_UNITID_OFFSET_ONLY
        comment "this will decided if only offset SB hypertransport chain"
define K8_SB_HT_CHAIN_ON_BUS0
        comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
define K8_HW_MEM_HOLE_SIZEK
        comment "Opteron E0 later memory hole size in K, 0 mean disable"
define K8_HW_MEM_HOLE_SIZE_AUTO_INC
        comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
define K8_HT_FREQ_1G_SUPPORT
	comment "Optern E0 later could support 1G HT, but still depends MB design"
define CONFIG_PCI_ROM_RUN
	comment "Init PCI device option rom"
define CONFIG_PCI_64BIT_PREF_MEM
        comment "allow PCI device get 4G above Region as pref mem"
define CONFIG_SANDPOINT_ALTIMUS
	comment "Configure Sandpoint with Altimus PMC"
define CONFIG_SANDPOINT_TALUS
	comment "Configure Sandpoint with Talus PMC"
define CONFIG_SANDPOINT_UNITY
	comment "Configure Sandpoint with Unity PMC"
define CONFIG_SANDPOINT_VALIS
	comment "Configure Sandpoint with Valis PMC"
define CONFIG_SANDPOINT_GYRUS
	comment "Configure Sandpoint with Gyrus PMC"
define CONFIG_BRIQ_750FX
	comment "Configure briQ with PowerPC 750FX"
define CONFIG_BRIQ_7400
	comment "Configure briQ with PowerPC G4"
