Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>

Index: src/devices/device.c
===================================================================
--- src/devices/device.c.orig
+++ src/devices/device.c
@@ -292,6 +292,13 @@ void compute_allocate_resource(
 		 * no size.  PCI bridge resources are a good example of this.
 		 */
 		/* Propogate the resource alignment to the bridge register  */
+#if 0
+		if(bridge == (&dev_root.resource[0])) {
+			printk_debug("%s ", dev_path(bus->dev));
+			printk_debug("%s ", dev_path(dev));
+			printk_debug("index %d align change %d %d \n", bridge->index, bridge->align, resource->align);
+		}
+#endif
 		if (resource->align > bridge->align) {
 			bridge->align = resource->align;
 		}
Index: src/devices/hypertransport.c
===================================================================
--- src/devices/hypertransport.c.orig
+++ src/devices/hypertransport.c
@@ -279,20 +279,7 @@ static void ht_collapse_early_enumeratio
 		}
 		/* Has the link failed? */
 		if (ctrl & (1 << 4)) {
-			/*
-			 * Either the link has failed, or we have
-			 * a CRC error.
-			 * Sometimes this can happen due to link
-			 * retrain, so lets knock it down and see
-			 * if its transient
-			 */
-			ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-			pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-			if (ctrl & ((1 << 4) | (1 << 8))) {
-				printk_alert("Detected error on Hypertransport Link\n");
-				return;
-			}
+			return;
 		}
 	} while((ctrl & (1 << 5)) == 0);
 
@@ -359,6 +346,8 @@ unsigned int hypertransport_scan_chain(s
 	struct ht_link prev;
 	device_t last_func = 0;
 	int ht_dev_num = 0;
+	unsigned temp_unitid;
+	unsigned not_use_count;
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
         //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
@@ -396,25 +385,12 @@ unsigned int hypertransport_scan_chain(s
 		/* Wait until the link initialization is complete */
 		do {
 			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-
-			if (ctrl & (1 << 6))
-				goto end_of_chain;	// End of chain
-
-			if (ctrl & ((1 << 4) | (1 << 8))) {
-				/*
-				 * Either the link has failed, or we have
-				 * a CRC error.
-				 * Sometimes this can happen due to link
-				 * retrain, so lets knock it down and see
-				 * if its transient
-				 */
-				ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-				pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-				ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-				if (ctrl & ((1 << 4) | (1 << 8))) {
-					printk_alert("Detected error on Hypertransport Link\n");
-					goto end_of_chain;
-				}
+			/* Is this the end of the hypertransport chain?
+			 * Has the link failed?
+			 * If so further scanning is pointless.
+			 */
+			if (ctrl & ((1 << 6) | (1 << 4))) {
+				goto end_of_chain;
 			}
 		} while((ctrl & (1 << 5)) == 0);
 		
@@ -449,39 +425,53 @@ unsigned int hypertransport_scan_chain(s
 		if (flags & 0x1f) {
 			break;
 		}
-
 		flags &= ~0x1f; /* mask out base Unit ID */
-                flags |= next_unitid & 0x1f;
+
+		count = (flags >> 5) & 0x1f; /* get unit count */
+		not_use_count = 0;
+		temp_unitid = next_unitid;
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+		if(offset_unitid) {
+			if((next_unitid+count)>=0x20) {
+		                temp_unitid = HT_CHAIN_END_UNITID_BASE;
+				//still use the old next_unitid
+				not_use_count = 1;
+			}
+
+		} 
+#endif
+
+                flags |= temp_unitid & 0x1f;
                 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
 
 		/* Update the Unitd id in the device structure */
 		static_count = 1;
 		for(func = dev; func; func = func->sibling) {
-			func->path.u.pci.devfn += (next_unitid << 3);
+			func->path.u.pci.devfn += (temp_unitid << 3);
 			static_count = (func->path.u.pci.devfn >> 3) 
 				- (dev->path.u.pci.devfn >> 3) + 1;
 			last_func = func;
 		}
-
 		/* Compute the number of unitids consumed */
-		count = (flags >> 5) & 0x1f; /* get unit count */
 		printk_spew("%s count: %04x static_count: %04x\n", 
 			dev_path(dev), count, static_count);
 		if (count < static_count) {
 			count = static_count;
 		}
+		if(!not_use_count) 
+			next_unitid +=  count;
 
 		/* Update the Unitid of the next device */
-		ht_unitid_base[ht_dev_num] = next_unitid;
+		ht_unitid_base[ht_dev_num] = temp_unitid;
 		ht_dev_num++;
+
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 		if(offset_unitid) {
-	                real_last_unitid = next_unitid;
         	        real_last_pos = pos;
+			real_last_unitid = temp_unitid;
 			real_last_dev = dev;
 		}
 #endif
-		next_unitid += count;
 
 		/* Setup the hypetransport link */
 		bus->reset_needed |= ht_setup_link(&prev, dev, pos);
@@ -491,7 +481,7 @@ unsigned int hypertransport_scan_chain(s
 			dev->vendor, dev->device, 
 			(dev->enabled? "enabled": "disabled"), next_unitid);
 
-	} while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3)));
+	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f/*(max_devfn >> 3)*/));
  end_of_chain:
 #if OPT_HT_LINK == 1
 	if(bus->reset_needed) {
@@ -503,7 +493,7 @@ unsigned int hypertransport_scan_chain(s
 #endif
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-        if(offset_unitid && (ht_dev_num>0)) {
+        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) ) {
                 uint16_t flags;
                 int i;
 		device_t last_func = 0;
@@ -511,21 +501,23 @@ unsigned int hypertransport_scan_chain(s
                 flags &= ~0x1f;
                 flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
                 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
-
                 for(func = real_last_dev; func; func = func->sibling) {
                         func->path.u.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3);
 			last_func = func;
                 }
-		
 		ht_unitid_base[ht_dev_num-1] = HT_CHAIN_END_UNITID_BASE; // update last one
 		
                 next_unitid = real_last_unitid;
+		
         }
 #endif
 
 	if (next_unitid > 0x1f) {
 		next_unitid = 0x1f;
 	}
+	if( (bus->secondary == 0) && (next_unitid > 0x17)) { 
+		next_unitid = 0x17; // avoid K8 on bus 0
+	}
 
 	/* Die if any leftover Static devices are are found.  
 	 * There's probably a problem in the Config.lb.
@@ -543,7 +535,7 @@ unsigned int hypertransport_scan_chain(s
 	/* Now that nothing is overlapping it is safe to scan the
 	 * children. 
 	 */
-	max = pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max); 
+	max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); 
 	return max; 
 }
 
Index: src/devices/Config.lb
===================================================================
--- src/devices/Config.lb.orig
+++ src/devices/Config.lb
@@ -1,9 +1,12 @@
 uses CONFIG_PCI_ROM_RUN
+
 object device.o
 object root_device.o
 object device_util.o
 object pci_device.o
+
 object hypertransport.o
+
 object pcix_device.o
 object pciexp_device.o
 object agp_device.o
Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c.orig
+++ src/devices/pci_rom.c
@@ -4,6 +4,21 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#if 0
+static void dump_mem(unsigned start, unsigned end)
+{
+        unsigned i;
+        print_debug("dump_mem:");
+        for(i=start;i<end;i++) {
+                if((i & 0xf)==0) {
+                        printk_debug("\n%08x:", i);
+                }
+                printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+        }
+        print_debug("\n");
+ }
+#endif
+
 struct rom_header * pci_rom_probe(struct device *dev)
 {
 	unsigned long rom_address;
@@ -29,6 +44,8 @@ struct rom_header * pci_rom_probe(struct
 				   rom_address|PCI_ROM_ADDRESS_ENABLE);
 	}
 
+//	dump_mem(rom_address, rom_address+256);
+
 	rom_header = (struct rom_header *)rom_address;
 	printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
 		    le32_to_cpu(rom_header->signature),
@@ -40,6 +57,7 @@ struct rom_header * pci_rom_probe(struct
 	}
 
 	rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
+
 	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
Index: src/devices/pci_device.c
===================================================================
--- src/devices/pci_device.c.orig
+++ src/devices/pci_device.c
@@ -254,7 +254,7 @@ struct resource *pci_get_resource(struct
 	return resource;
 }
 
-static void pci_get_rom_resource(struct device *dev, unsigned long index)
+void pci_get_rom_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource;
 	unsigned long value;
Index: src/devices/device_util.c
===================================================================
--- src/devices/device_util.c.orig
+++ src/devices/device_util.c
@@ -389,6 +389,31 @@ resource_t resource_end(struct resource 
 	return end;
 }
 
+void normalize_resource(struct resource *resource)
+{
+        /*
+           increase resource->align and resource->size, so the high bits
+                 is the same in the range
+        */
+        unsigned long long base, end, size;
+        unsigned align;
+        base = resource->base;
+        end = resource_end(resource);
+	
+        size = end + 1ULL  - base;
+
+	if(!size) return;
+
+        align = log2(size);
+        if(size > (1ULL<<align)) align++;
+
+	resource->base = align_up(base, align);
+        resource->align = align;
+        resource->gran = align;
+	resource->size = 1ULL<<align;
+
+}
+
 /**
  * @brief Compute the maximum legal value for resource->base
  * @param resource the resource whose maximum is desired
@@ -489,6 +514,7 @@ void search_global_resources(
 		int i;
 		/* Ignore disabled devices */
 		if (!curdev->have_resources) continue;
+//		printk_debug("search_global_resoures: %s curdev=%x  resources=%x\n", dev_path(curdev), curdev, curdev->resources); //yhlu
 		for(i = 0; i < curdev->resources; i++) {
 			struct resource *resource = &curdev->resource[i];
 			/* If it isn't the right kind of resource ignore it */
@@ -499,6 +525,7 @@ void search_global_resources(
 			if (resource->flags & IORESOURCE_SUBTRACTIVE) {
 				continue;
 			}
+//			report_resource_stored(curdev, resource, " search_global_resources"); //yhlu
 			search(gp, curdev, resource);
 		}
 	}
Index: src/include/usbdebug_direct.h
===================================================================
--- /dev/null
+++ src/include/usbdebug_direct.h
@@ -0,0 +1,17 @@
+#ifndef USBDEBUG_DIRECT_H
+#define USBDEBUG_DIRECT_H
+
+struct ehci_debug_info {
+        void *ehci_caps;
+        void *ehci_regs;
+        void *ehci_debug;
+        unsigned devnum;
+        unsigned endpoint_out;
+        unsigned endpoint_in;
+};
+extern int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
+extern int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
+extern void set_ehci_base(unsigned ehci_base);
+extern void set_ehci_debug(unsigned ehci_deug);
+extern unsigned get_ehci_debug(void);
+#endif
Index: src/include/usb_ch9.h
===================================================================
--- /dev/null
+++ src/include/usb_ch9.h
@@ -0,0 +1,83 @@
+#ifndef USB_CH9_H
+#define USB_CH9_H
+
+#define USB_DIR_OUT                     0               /* to device */
+#define USB_DIR_IN                      0x80            /* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK                   (0x03 << 5)
+#define USB_TYPE_STANDARD               (0x00 << 5)
+#define USB_TYPE_CLASS                  (0x01 << 5)
+#define USB_TYPE_VENDOR                 (0x02 << 5)
+#define USB_TYPE_RESERVED               (0x03 << 5)
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK                  0x1f
+#define USB_RECIP_DEVICE                0x00
+#define USB_RECIP_INTERFACE             0x01
+#define USB_RECIP_ENDPOINT              0x02
+#define USB_RECIP_OTHER                 0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT                  0x04
+#define USB_RECIP_RPIPE                 0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS              0x00
+#define USB_REQ_CLEAR_FEATURE           0x01
+#define USB_REQ_SET_FEATURE             0x03
+#define USB_REQ_SET_ADDRESS             0x05
+#define USB_REQ_GET_DESCRIPTOR          0x06
+#define USB_REQ_SET_DESCRIPTOR          0x07
+#define USB_REQ_GET_CONFIGURATION       0x08
+#define USB_REQ_SET_CONFIGURATION       0x09
+#define USB_REQ_GET_INTERFACE           0x0A
+#define USB_REQ_SET_INTERFACE           0x0B
+#define USB_REQ_SYNCH_FRAME             0x0C
+
+#define USB_REQ_SET_ENCRYPTION          0x0D    /* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION          0x0E
+#define USB_REQ_RPIPE_ABORT             0x0E
+#define USB_REQ_SET_HANDSHAKE           0x0F
+#define USB_REQ_RPIPE_RESET             0x0F
+#define USB_REQ_GET_HANDSHAKE           0x10
+#define USB_REQ_SET_CONNECTION          0x11
+#define USB_REQ_SET_SECURITY_DATA       0x12
+#define USB_REQ_GET_SECURITY_DATA       0x13
+#define USB_REQ_SET_WUSB_DATA           0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE     0x15
+#define USB_REQ_LOOPBACK_DATA_READ      0x16
+#define USB_REQ_SET_INTERFACE_DS        0x17
+
+#define USB_DT_DEBUG                    0x0a
+
+#define USB_DEVICE_DEBUG_MODE           6       /* (special devices only) */
+
+//frim usb_ch9.h
+struct usb_ctrlrequest {
+        uint8_t bRequestType;
+        uint8_t bRequest;
+        uint16_t wValue;
+        uint16_t wIndex;
+        uint16_t wLength;
+} __attribute__ ((packed));
+
+struct usb_debug_descriptor {
+        uint8_t  bLength;
+        uint8_t  bDescriptorType;
+
+        /* bulk endpoints with 8 byte maxpacket */
+        uint8_t  bDebugInEndpoint;
+        uint8_t  bDebugOutEndpoint;
+};
+
+#endif
+
Index: src/include/cpu/x86/bist.h
===================================================================
--- src/include/cpu/x86/bist.h.orig
+++ src/include/cpu/x86/bist.h
@@ -4,7 +4,7 @@
 static void report_bist_failure(unsigned long bist)
 {
 	if (bist != 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
                 printk_emerg("BIST failed: %08x", bist);
 #else
 		print_emerg("BIST failed: ");
Index: src/include/ehci.h
===================================================================
--- /dev/null
+++ src/include/ehci.h
@@ -0,0 +1,132 @@
+#ifndef EHCI_H
+#define EHCI_H
+
+struct ehci_caps {
+        /* these fields are specified as 8 and 16 bit registers,
+         * but some hosts can't perform 8 or 16 bit PCI accesses.
+         */
+        u32             hc_capbase;
+#define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
+#define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
+        u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
+#define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
+#define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
+
+        u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
+#define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
+        u8              portroute [8];   /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+
+        /* USBCMD: offset 0x00 */
+        u32             command;
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK        (1<<11)         /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
+#define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
+#define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
+#define CMD_ASE         (1<<5)          /* async schedule enable */
+#define CMD_PSE         (1<<4)          /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET       (1<<1)          /* reset HC not bus */
+#define CMD_RUN         (1<<0)          /* start/stop HC */
+
+        /* USBSTS: offset 0x04 */
+        u32             status;
+#define STS_ASS         (1<<15)         /* Async Schedule Status */
+#define STS_PSS         (1<<14)         /* Periodic Schedule Status */
+#define STS_RECL        (1<<13)         /* Reclamation */
+#define STS_HALT        (1<<12)         /* Not running (any reason) */
+/* some bits reserved */
+        /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA         (1<<5)          /* Interrupted on async advance */
+#define STS_FATAL       (1<<4)          /* such as some PCI access errors */
+#define STS_FLR         (1<<3)          /* frame list rolled over */
+#define STS_PCD         (1<<2)          /* port change detect */
+#define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
+#define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
+
+        /* USBINTR: offset 0x08 */
+        u32             intr_enable;
+
+        /* FRINDEX: offset 0x0C */
+        u32             frame_index;    /* current microframe number */
+        /* CTRLDSSEGMENT: offset 0x10 */
+        u32             segment;        /* address bits 63:32 if needed */
+        /* PERIODICLISTBASE: offset 0x14 */
+        u32             frame_list;     /* points to periodic list */
+        /* ASYNCLISTADDR: offset 0x18 */
+        u32             async_next;     /* address of next async queue head */
+
+        u32             reserved [9];
+
+        /* CONFIGFLAG: offset 0x40 */
+        u32             configured_flag;
+#define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
+
+        /* PORTSC: offset 0x44 */
+        u32             port_status [0];        /* up to N_PORTS */
+/* 31:23 reserved */
+#define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
+#define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_LED_OFF    (0<<14)
+#define PORT_LED_AMBER  (1<<14)
+#define PORT_LED_GREEN  (2<<14)
+#define PORT_LED_MASK   (3<<14)
+#define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
+#define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_RESET      (1<<8)          /* reset port */
+#define PORT_SUSPEND    (1<<7)          /* suspend port */
+#define PORT_RESUME     (1<<6)          /* resume it */
+#define PORT_OCC        (1<<5)          /* over current change */
+#define PORT_OC         (1<<4)          /* over current active */
+#define PORT_PEC        (1<<3)          /* port enable change */
+#define PORT_PE         (1<<2)          /* port enable */
+#define PORT_CSC        (1<<1)          /* connect status change */
+#define PORT_CONNECT    (1<<0)          /* device connected */
+#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console.  (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+        u32     control;
+#define DBGP_OWNER      (1<<30)
+#define DBGP_ENABLED    (1<<28)
+#define DBGP_DONE       (1<<16)
+#define DBGP_INUSE      (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+#       define DBGP_ERR_BAD     1
+#       define DBGP_ERR_SIGNAL  2
+#define DBGP_ERROR      (1<<6)
+#define DBGP_GO         (1<<5)
+#define DBGP_OUT        (1<<4)
+#define DBGP_LEN(x)     (((x)>>0)&0x0f)
+        u32     pids;
+#define DBGP_PID_GET(x)         (((x)>>16)&0xff)
+#define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
+        u32     data03;
+        u32     data47;
+        u32     address;
+#define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+
+#endif
Index: src/include/device/device.h
===================================================================
--- src/include/device/device.h.orig
+++ src/include/device/device.h
@@ -55,7 +55,11 @@ struct bus {
 	unsigned	disable_relaxed_ordering : 1;
 };
 
-#define MAX_RESOURCES 12 
+#if EXT_CONF_SUPPORT == 1
+	#define MAX_RESOURCES 32 
+#else
+	#define MAX_RESOURCES 12 
+#endif
 #define MAX_LINKS    8 
 /*
  * There is one device structure for each slot-number/function-number
Index: src/include/device/resource.h
===================================================================
--- src/include/device/resource.h.orig
+++ src/include/device/resource.h
@@ -87,6 +87,7 @@ extern struct resource *new_resource(str
 extern struct resource *find_resource(struct device * dev, unsigned index);
 extern resource_t resource_end(struct resource *resource);
 extern resource_t resource_max(struct resource *resource);
+extern void normalize_resource(struct resource *resource);
 extern void report_resource_stored(struct device * dev, struct resource *resource, const char *comment);
 
 typedef void (*resource_search_t)(void *gp, struct device *dev, struct resource *res);
Index: src/cpu/amd/car/copy_and_run.c
===================================================================
--- src/cpu/amd/car/copy_and_run.c.orig
+++ src/cpu/amd/car/copy_and_run.c
@@ -5,9 +5,9 @@
 static inline void print_debug_cp_run(const char *strval, uint32_t val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%08x\r\n", strval, val);
+        printk_ram_debug("%s%08x\r\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+        print_ram_debug(strval); print_ram_debug_hex32(val); print_ram_debug("\r\n");
 #endif
 }
 
@@ -23,7 +23,7 @@ static void copy_and_run(void)
 	uint8_t *src, *dst; 
         unsigned long ilen, olen;
 
-	print_debug("Copying LinuxBIOS to RAM.\r\n");
+	print_ram_debug("Copying LinuxBIOS to ram.\r\n");
 
 #if !CONFIG_COMPRESS 
 	__asm__ volatile (
@@ -55,7 +55,7 @@ static void copy_and_run(void)
 
 	print_debug_cp_run("linxbios_ram.bin   length = ", olen);
 
-	print_debug("Jumping to LinuxBIOS.\r\n");
+	print_ram_debug("Jumping to LinuxBIOS.\r\n");
 
         __asm__ volatile (
                 "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
@@ -95,13 +95,10 @@ static void copy_and_run_ap_code_in_car(
 //        print_debug_cp_run("src=",(uint32_t)src);
 //        print_debug_cp_run("dst=",(uint32_t)dst);
 
-//      dump_mem(src, src+0x100);
-
         olen = unrv2b(src, dst, &ilen);
 //        print_debug_cp_run("linxbios_apc.nrv2b length = ", ilen);
 
 #endif
-//      dump_mem(dst, dst+0x100);
 
 //        print_debug_cp_run("linxbios_apc.bin   length = ", olen);
 
Index: src/cpu/amd/car/cache_as_ram.lds
===================================================================
--- src/cpu/amd/car/cache_as_ram.lds.orig
+++ src/cpu/amd/car/cache_as_ram.lds
@@ -1,10 +1,10 @@
 /* 
  * init sections to place code running with cache as ram.
  * 
- * 2004 by Stefan Reinauer <stepan@openbios.org>
  */
 
 SECTIONS {
+
 	.init . : {
 		_init = .;
 		*(.init.text);
Index: src/cpu/amd/car/clear_init_ram.c
===================================================================
--- src/cpu/amd/car/clear_init_ram.c.orig
+++ src/cpu/amd/car/clear_init_ram.c
@@ -1,13 +1,11 @@
 /* by yhlu 6.2005 */
 /* be warned, this file will be used core 0/node 0 only */
-
 static void __attribute__((noinline)) clear_init_ram(void)
 {
 	// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
 	// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
 	// so noline clear_init_ram
         clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
-
 }
 
 /* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
@@ -15,4 +13,8 @@ static void set_init_ram_access(void)
 {
 	set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRBACK);
 }
+static void set_init_ram_access_wc(void)
+{
+	set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, MTRR_TYPE_WRCOMB);
+}
 
Index: src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- src/cpu/amd/car/post_cache_as_ram.c.orig
+++ src/cpu/amd/car/post_cache_as_ram.c
@@ -40,9 +40,6 @@ static void post_cache_as_ram(void)
         }
 #endif
 
-	unsigned testx = 0x5a5a5a5a;
-	print_debug_pcar("testx = ", testx);
-
 	/* copy data from cache as ram to 
 		ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead.
 	 */
@@ -53,7 +50,7 @@ static void post_cache_as_ram(void)
 	set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_LB_MEM_TOPK) */
 
 //	dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x8000, DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x7c00);
-	print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
+	print_debug("Copying data from cache to ram -- switching to use ram as stack... ");
 
 	/* from here don't store more data in CAR */
 #if 0
@@ -63,13 +60,11 @@ static void post_cache_as_ram(void)
 #endif
 
         memcopy((void *)((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE), (void *)DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
-//        dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
-
         __asm__ volatile (
                 /* set new esp */ /* before _RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - (CONFIG_LB_MEM_TOPK<<10) )
         ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
 #if 0
         __asm__ volatile (
@@ -79,19 +74,18 @@ static void post_cache_as_ram(void)
 
 
 	/* We can put data to stack again */
-
+	/* use print_ram_debug instead in following stage */
         /* only global variable sysinfo in cache need to be offset */
-        print_debug("Done\r\n");
-        print_debug_pcar("testx = ", testx);
+        print_ram_debug("Done\r\n");
 
-	print_debug("Disabling cache as ram now \r\n");
+	print_ram_debug("Disabling cache as ram now \r\n");
 	disable_cache_as_ram_bsp();  
 
-        print_debug("Clearing initial memory region: ");
+        print_ram_debug("Clearing initial memory region: ");
         clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
-        print_debug("Done\r\n");
+        print_ram_debug("Done\r\n");
 
-//	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
+//	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x1c00, (CONFIG_LB_MEM_TOPK<<10) - 0x1000);
 
 #ifndef MEM_TRAIN_SEQ
 #define MEM_TRAIN_SEQ 0
@@ -108,7 +102,7 @@ static void post_cache_as_ram(void)
         copy_and_run();
         /* We will not return */
 
-        print_debug("should not be here -\r\n");
+        print_ram_debug("should not be here -\r\n");
 
 }
 
Index: src/cpu/amd/model_fxx/Config.lb
===================================================================
--- src/cpu/amd/model_fxx/Config.lb.orig
+++ src/cpu/amd/model_fxx/Config.lb
@@ -17,5 +17,4 @@ dir /cpu/amd/dualcore
 dir /cpu/amd/microcode
 driver model_fxx_init.o
 object apic_timer.o
-object model_fxx_update_microcode.o
-object processor_name.o
+object model_fxx_update_microcode.o
\ No newline at end of file
Index: src/cpu/amd/model_fxx/fidvid.c
===================================================================
--- src/cpu/amd/model_fxx/fidvid.c.orig
+++ src/cpu/amd/model_fxx/fidvid.c
@@ -481,12 +481,13 @@ static void init_fidvid_bsp(unsigned bsp
         if(fid>(10-4)*2) {
                 fid = (10-4)*2; //x10 
         }
-
+#if 0
         if(vid>=0x1f) {
                 vid+= 4; //unit is 12.5mV
         } else {
                 vid+= 2; //unit is 25mV
         }
+#endif
 
 	fv.common_fidvid = (fid<<8) | (vid<<16);
 
Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c.orig
+++ src/cpu/amd/model_fxx/model_fxx_init.c
@@ -546,6 +546,8 @@ static void amd_set_name_string_f(device
 extern void model_fxx_update_microcode(unsigned cpu_deviceid);
 int init_processor_name(void);
 
+static unsigned ehci_debug_addr;
+
 void model_fxx_init(device_t dev)
 {
 	unsigned long i;
@@ -565,11 +567,21 @@ void model_fxx_init(device_t dev)
 	} 
 #endif
 
+#if CONFIG_USBDEBUG_DIRECT
+	if(!ehci_debug_addr) 
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 	amd_setup_mtrrs();
 	x86_mtrr_check();
 
+#if CONFIG_USBDEBUG_DIRECT
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
         /* Update the microcode */
 	model_fxx_update_microcode(dev->device);
 
@@ -589,9 +601,6 @@ void model_fxx_init(device_t dev)
 	msr.lo |= (1 << 0);
 	wrmsr(HWCR_MSR, msr);
 	
-	/* Set the processor name string */
-	init_processor_name();
-	
 	enable_cache();
 
 	/* Enable the local cpu apics */
Index: src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_fxx/init_cpus.c.orig
+++ src/cpu/amd/model_fxx/init_cpus.c
@@ -356,7 +356,6 @@ static unsigned init_cpus(unsigned cpu_i
 		return bsp_apicid;
 }
 
-#if CONFIG_LOGICAL_CPUS == 1
 
 static unsigned is_core0_started(unsigned nodeid)
 {
@@ -383,4 +382,3 @@ static void wait_all_core0_started(void)
 
 }
 
-#endif
Index: src/cpu/x86/32bit/entry32.inc
===================================================================
--- src/cpu/x86/32bit/entry32.inc.orig
+++ src/cpu/x86/32bit/entry32.inc
@@ -19,11 +19,11 @@ gdtptr:
 
 	/* selgdt 0x08, flat code segment */
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00	
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */	
 
 	/* selgdt 0x10,flat data segment */
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x93, 0xcf, 0x00	
+	.byte	0x00, 0x93, 0xcf, 0x00
 
 gdt_end:
 	
Index: src/cpu/x86/mtrr/earlymtrr.c
===================================================================
--- src/cpu/x86/mtrr/earlymtrr.c.orig
+++ src/cpu/x86/mtrr/earlymtrr.c
@@ -42,6 +42,7 @@ static void set_var_mtrr(
 
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
 	msr_t basem, maskm;
 	basem.lo = base | type;
 	basem.hi = 0;
Index: src/cpu/x86/mtrr/mtrr.c
===================================================================
--- src/cpu/x86/mtrr/mtrr.c.orig
+++ src/cpu/x86/mtrr/mtrr.c
@@ -282,10 +282,16 @@ static void set_fixed_mtrr_resource(void
 	
 }
 
+#ifndef CONFIG_VAR_MTRR_HOLE
+#define CONFIG_VAR_MTRR_HOLE 1
+#endif
+
 struct var_mtrr_state {
 	unsigned long range_startk, range_sizek;
 	unsigned int reg;
+#if CONFIG_VAR_MTRR_HOLE
 	unsigned long hole_startk, hole_sizek;
+#endif
 	unsigned address_bits;
 };
 
@@ -304,29 +310,40 @@ void set_var_mtrr_resource(void *gp, str
 	if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
 		unsigned long endk = basek + sizek;
 		state->range_sizek = endk - state->range_startk;
+		printk_spew("1 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+                                state->range_startk, state->range_sizek, state->hole_startk, state->hole_sizek);
+
 		return;
 	}
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
+#if CONFIG_VAR_MTRR_HOLE
 		if (state->hole_sizek == 0) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
 			state->hole_sizek  = basek - state->hole_startk;
 			state->range_sizek = endk - state->range_startk;
+			printk_spew("2 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+				state->range_startk, state->range_sizek, state->hole_startk, state->hole_sizek);
 			return;
 		}
+#endif
 		state->reg = range_to_mtrr(state->reg, state->range_startk, 
 			state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
+#if CONFIG_VAR_MTRR_HOLE
 		state->reg = range_to_mtrr(state->reg, state->hole_startk, 
 			state->hole_sizek, basek,  MTRR_TYPE_UNCACHEABLE, state->address_bits);
+#endif
 		state->range_startk = 0;
 		state->range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
                 state->hole_startk = 0;
                 state->hole_sizek = 0;
+#endif
 	}
 	/* Allocate an msr */  
-	printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
+	printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek);
 	state->range_startk = basek;
 	state->range_sizek  = sizek;
 }
@@ -377,8 +394,10 @@ void x86_setup_var_mtrrs(unsigned addres
 	 */
 	var_state.range_startk = 0;
 	var_state.range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
 	var_state.hole_startk = 0;
 	var_state.hole_sizek = 0;
+#endif
 	var_state.reg = 0;
 	var_state.address_bits = address_bits;
 	search_global_resources(
@@ -386,14 +405,19 @@ void x86_setup_var_mtrrs(unsigned addres
 		set_var_mtrr_resource, &var_state);
 
 	/* Write the last range */
+	printk_spew("3 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+                                var_state.range_startk, var_state.range_sizek, var_state.hole_startk, var_state.hole_sizek);
 	var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, 
 		var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
+#if CONFIG_VAR_MTRR_HOLE
 	var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
 		var_state.hole_sizek,  0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
+#endif
 	printk_debug("DONE variable MTRRs\n");
 	printk_debug("Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
 	while(var_state.reg < MTRRS) {
+		printk_spew("clearing var_state.reg=%d\n", var_state.reg);
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
 	printk_spew("call enable_var_mtrr()\n");
Index: src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- src/cpu/x86/lapic/lapic_cpu_init.c.orig
+++ src/cpu/x86/lapic/lapic_cpu_init.c
@@ -13,6 +13,13 @@
 #include <smp/atomic.h>
 #include <smp/spinlock.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/tsc.h>
+
+static inline void print_debug_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
+{
+        printk_debug("%s[%02x]=%08x%08x\n", str, i, val, val2);
+
+}
 
 #if CONFIG_SMP == 1
 
@@ -374,6 +381,7 @@ void initialize_cpus(struct bus *cpu_bus
 {
 	struct device_path cpu_path;
 	struct cpu_info *info;
+	tsc_t tsc;
 
 	/* Find the info struct for this cpu */
 	info = cpu_info();
@@ -400,6 +408,9 @@ void initialize_cpus(struct bus *cpu_bus
 	
         cpus_ready_for_init(); 
 
+        tsc = rdtsc();
+        print_debug_tsc_x("\nFinal              : tsc ", 10,  tsc.hi, tsc.lo);
+
 #if CONFIG_SMP == 1
 	#if SERIAL_CPU_INIT == 0
 	/* start all aps at first, so we can init ECC all together */
@@ -419,6 +430,8 @@ void initialize_cpus(struct bus *cpu_bus
 	/* Now wait the rest of the cpus stop*/
 	wait_other_cpus_stop(cpu_bus);
 #endif
+        tsc = rdtsc();
+        print_debug_tsc_x("\nFinal              : tsc ", 11,  tsc.hi, tsc.lo);
 
 }
 
Index: src/stream/rom_stream.c
===================================================================
--- src/stream/rom_stream.c.orig
+++ src/stream/rom_stream.c
@@ -117,8 +117,8 @@ byte_offset_t stream_skip(byte_offset_t 
 	byte_offset_t bytes;
 	bytes = count;
 	if ((rom + bytes - 1) > rom_end) {
-		printk_warning("%6d:%s() - overflowed source buffer\n",
-			__LINE__, __FUNCTION__);
+		printk_warning("%6d:%s() - overflowed source buffer rom=%x, bytes=%x, rom_end=%x\n",
+			__LINE__, __FUNCTION__, rom, bytes, rom_end);
 		bytes = 0;
 		if (rom <= rom_end) {
 			bytes = (rom_end - rom) + 1;
Index: src/console/Config.lb
===================================================================
--- src/console/Config.lb.orig
+++ src/console/Config.lb
@@ -1,4 +1,5 @@
 uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_USBDEBUG_DIRECT
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_CONSOLE_BTEXT
 uses CONFIG_CONSOLE_LOGBUF
@@ -9,6 +10,9 @@ object printk.o
 if CONFIG_CONSOLE_SERIAL8250
 	driver uart8250_console.o
 end
+if CONFIG_USBDEBUG_DIRECT
+	driver usbdebug_direct_console.o
+end
 if CONFIG_CONSOLE_VGA
 	driver vga_console.o
 end
@@ -24,8 +28,3 @@ object console.o
 object vtxprintf.o
 object vsprintf.o
 
-if CONFIG_USE_INIT
-#	if CONFIG_USE_PRINTK_IN_CAR
-	initobject vtxprintf.o
-#	end
-end
Index: src/console/usbdebug_direct_console.c
===================================================================
--- /dev/null
+++ src/console/usbdebug_direct_console.c
@@ -0,0 +1,58 @@
+#include <console/console.h>
+#include <usbdebug_direct.h>
+#include <pc80/mc146818rtc.h>
+
+struct ehci_debug_info dbg_info;
+
+void set_ehci_base(unsigned ehci_base)
+{
+	unsigned diff;
+	if(!dbg_info.ehci_debug) return;
+	diff = dbg_info.ehci_caps - ehci_base;
+	dbg_info.ehci_regs -= diff;
+	dbg_info.ehci_debug -= diff;
+	dbg_info.ehci_caps = ehci_base;
+}
+void set_ehci_debug(unsigned ehci_debug)
+{
+	dbg_info.ehci_debug = ehci_debug;
+}
+
+unsigned get_ehci_debug(void)
+{
+       return dbg_info.ehci_debug;
+}
+
+static void dbgp_init(void)
+{
+	struct ehci_debug_info *dbg_infox;
+	dbg_infox = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM
+	memcpy(&dbg_info, dbg_infox, sizeof(struct ehci_debug_info) );
+}
+
+static void dbgp_tx_byte(unsigned char data) 
+{
+	if(dbg_info.ehci_debug) 
+		dbgp_bulk_write_x(&dbg_info,&data,1);
+}
+
+static unsigned char dbgp_rx_byte(void) 
+{
+	unsigned char data = 0xff;
+	if(dbg_info.ehci_debug) 
+		dbgp_bulk_read_x(&dbg_info,&data,1);
+	return data;
+}
+
+static int dbgp_tst_byte(void) 
+{
+	return dbg_info.ehci_debug;
+}
+
+static struct console_driver usbdebug_direct_console __console = {
+	.init    = dbgp_init,
+	.tx_byte = dbgp_tx_byte,
+	.rx_byte = dbgp_rx_byte,
+	.tst_byte = dbgp_tst_byte,
+};
+
Index: src/config/Options.lb
===================================================================
--- src/config/Options.lb.orig
+++ src/config/Options.lb
@@ -442,6 +442,11 @@ define CONFIG_CONSOLE_SERIAL8250
 	export always
 	comment "Log messages to 8250 uart based serial console"
 end
+define CONFIG_USBDEBUG_DIRECT
+	default 0
+	export always
+	comment "Log messages to ehci debug port console"
+end
 define DEFAULT_CONSOLE_LOGLEVEL
 	default 7
 	export always
@@ -999,6 +1004,12 @@ define CONFIG_PCI_64BIT_PREF_MEM
         comment "allow PCI device get 4G above Region as pref mem"
 end
 
+define CONFIG_AGESA
+	default 0
+	export always
+	comment "use AMD AGESA to init RAM instead of native code"
+end
+
 define CONFIG_VIDEO_MB
         default none
         export used
Index: src/lib/Config.lb
===================================================================
--- src/lib/Config.lb.orig
+++ src/lib/Config.lb
@@ -1,9 +1,15 @@
 uses HAVE_FALLBACK_BOOT
 uses CONFIG_USE_INIT
 uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USBDEBUG_DIRECT
 
 object clog2.o
 object uart8250.o
+
+if CONFIG_USBDEBUG_DIRECT
+	object usbdebug_direct.o
+end
+
 object memset.o
 object memcpy.o
 object memcmp.o
@@ -15,12 +21,8 @@ object compute_ip_checksum.o
 object version.o
 # Force version.o to recompile every time
 makedefine .PHONY : version.o
-
 if CONFIG_USE_INIT
-#	if CONFIG_USE_PRINTK_IN_CAR
-	initobject uart8250.c
-#	end
-	initobject memset.o
+#	initobject memset.o
 	initobject memcpy.o
-	initobject memcmp.o
+#	initobject memcmp.o
 end
Index: src/lib/nrv2b.c
===================================================================
--- src/lib/nrv2b.c.orig
+++ src/lib/nrv2b.c
@@ -28,6 +28,7 @@
 #if ENDIAN == 0 && BITSIZE == 32
 #define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
 #endif
+
 static unsigned long unrv2b(uint8_t * src, uint8_t * dst, unsigned long *ilen_p)
 {
 	unsigned long ilen = 0, olen = 0, last_m_off = 1;
@@ -37,8 +38,8 @@ static unsigned long unrv2b(uint8_t * sr
 
 	// skip length
 	src += 4;
-	/* FIXME: check olen with the length stored in first 4 bytes */	
 
+	/* FIXME: check olen with len on first 4 bytes */	
 	for (;;) {
 		unsigned int m_off, m_len;
 		while (GETBIT(bb, src, ilen)) {
Index: src/lib/uart8250.c
===================================================================
--- src/lib/uart8250.c.orig
+++ src/lib/uart8250.c
@@ -64,8 +64,6 @@ void uart8250_init(unsigned base_port, u
 	outb(0x0, base_port + UART_IER);
 	/* enable fifo's */
 	outb(0x01, base_port + UART_FCR);
-	/* assert DTR and RTS so the other end is happy */
-	outb(0x03, base_port + UART_MCR);
 	/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
 	outb(0x80 | lcs, base_port + UART_LCR);
 	outb(divisor & 0xFF,   base_port + UART_DLL);
Index: src/lib/usbdebug_direct.c
===================================================================
--- /dev/null
+++ src/lib/usbdebug_direct.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright (C) 2006 Eric Biederman (ebiederm@xmission.com)
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License version
+ *	2 as published by the Free Software Foundation.
+ *
+ *	2006.12.10 yhlu moved it to LinuxBIOS and use struct instead
+ */
+#ifndef __ROMCC__
+#include <console/console.h>
+#else
+#if CONFIG_USE_PRINTK_IN_CAR==0
+#define printk_debug(fmt, arg...)   do {} while(0)
+#endif
+#endif
+
+
+#include <arch/io.h>
+
+#include <usb_ch9.h>
+#include <ehci.h>
+#include <usbdebug_direct.h>
+
+#define USB_DEBUG_DEVNUM 127
+
+#define DBGP_DATA_TOGGLE	0x8800
+#define DBGP_PID_UPDATE(x, tok) \
+	((((x) ^ DBGP_DATA_TOGGLE) & 0xffff00) | ((tok) & 0xff))
+
+#define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f))
+/*
+ * USB Packet IDs (PIDs)
+ */
+
+/* token */
+#define USB_PID_OUT		0xe1
+#define USB_PID_IN		0x69
+#define USB_PID_SOF		0xa5
+#define USB_PID_SETUP		0x2d
+/* handshake */
+#define USB_PID_ACK		0xd2
+#define USB_PID_NAK		0x5a
+#define USB_PID_STALL		0x1e
+#define USB_PID_NYET		0x96
+/* data */
+#define USB_PID_DATA0		0xc3
+#define USB_PID_DATA1		0x4b
+#define USB_PID_DATA2		0x87
+#define USB_PID_MDATA		0x0f
+/* Special */
+#define USB_PID_PREAMBLE	0x3c
+#define USB_PID_ERR		0x3c
+#define USB_PID_SPLIT		0x78
+#define USB_PID_PING		0xb4
+#define USB_PID_UNDEF_0		0xf0
+
+#define USB_PID_DATA_TOGGLE	0x88
+#define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
+
+#define PCI_CAP_ID_EHCI_DEBUG	0xa
+
+#define HUB_ROOT_RESET_TIME	50	/* times are in msec */
+#define HUB_SHORT_RESET_TIME	10
+#define HUB_LONG_RESET_TIME	200
+#define HUB_RESET_TIMEOUT	500
+
+#define DBGP_MAX_PACKET		8
+
+static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug)
+{
+	unsigned ctrl;
+	int loop = 0x100000;
+	do {
+		ctrl = readl(&ehci_debug->control);
+		/* Stop when the transaction is finished */
+		if (ctrl & DBGP_DONE)
+			break;
+	} while(--loop>0); 
+
+	if (!loop) return -1000;
+
+	/* Now that we have observed the completed transaction,
+	 * clear the done bit.
+	 */
+	writel(ctrl | DBGP_DONE, &ehci_debug->control);
+	return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl);
+}
+
+static void dbgp_mdelay(int ms)
+{
+	int i;
+	while (ms--) {
+		for (i = 0; i < 1000; i++)
+			outb(0x1, 0x80);
+	}
+}
+
+static void dbgp_breath(void)
+{
+	/* Sleep to give the debug port a chance to breathe */
+}
+
+static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl)
+{
+	unsigned pids, lpid;
+	int ret;
+
+	int loop = 3;
+retry:
+	writel(ctrl | DBGP_GO, &ehci_debug->control);
+	ret = dbgp_wait_until_complete(ehci_debug);
+	pids = readl(&ehci_debug->pids);
+	lpid = DBGP_PID_GET(pids);
+
+	if (ret < 0)
+		return ret;
+
+	/* If the port is getting full or it has dropped data
+	 * start pacing ourselves, not necessary but it's friendly.
+	 */
+	if ((lpid == USB_PID_NAK) || (lpid == USB_PID_NYET))
+		dbgp_breath();
+	
+	/* If I get a NACK reissue the transmission */
+	if (lpid == USB_PID_NAK) {
+		if (--loop > 0) goto retry;
+	}
+
+	return ret;
+}
+
+static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int size)
+{
+	const unsigned char *bytes = buf;
+	unsigned lo, hi;
+	int i;
+	lo = hi = 0;
+	for (i = 0; i < 4 && i < size; i++)
+		lo |= bytes[i] << (8*i);
+	for (; i < 8 && i < size; i++)
+		hi |= bytes[i] << (8*(i - 4));
+	writel(lo, &ehci_debug->data03);
+	writel(hi, &ehci_debug->data47);
+}
+
+static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size)
+{
+	unsigned char *bytes = buf;
+	unsigned lo, hi;
+	int i;
+	lo = readl(&ehci_debug->data03);
+	hi = readl(&ehci_debug->data47);
+	for (i = 0; i < 4 && i < size; i++)
+		bytes[i] = (lo >> (8*i)) & 0xff;
+	for (; i < 8 && i < size; i++)
+		bytes[i] = (hi >> (8*(i - 4))) & 0xff;
+}
+
+static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, const char *bytes, int size)
+{
+	unsigned pids, addr, ctrl;
+	int ret;
+	if (size > DBGP_MAX_PACKET)
+		return -1;
+
+	addr = DBGP_EPADDR(devnum, endpoint);
+
+	pids = readl(&ehci_debug->pids);
+	pids = DBGP_PID_UPDATE(pids, USB_PID_OUT);
+	
+	ctrl = readl(&ehci_debug->control);
+	ctrl = DBGP_LEN_UPDATE(ctrl, size);
+	ctrl |= DBGP_OUT;
+	ctrl |= DBGP_GO;
+
+	dbgp_set_data(ehci_debug, bytes, size);
+	writel(addr, &ehci_debug->address);
+	writel(pids, &ehci_debug->pids);
+
+	ret = dbgp_wait_until_done(ehci_debug, ctrl);
+	if (ret < 0) {
+		return ret;
+	}
+	return ret;
+}
+
+int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size)
+{
+	return dbgp_bulk_write(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_out, bytes, size);
+}
+
+static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, unsigned endpoint, void *data, int size)
+{
+	unsigned pids, addr, ctrl;
+	int ret;
+
+	if (size > DBGP_MAX_PACKET)
+		return -1;
+
+	addr = DBGP_EPADDR(devnum, endpoint);
+
+	pids = readl(&ehci_debug->pids);
+	pids = DBGP_PID_UPDATE(pids, USB_PID_IN);
+		
+	ctrl = readl(&ehci_debug->control);
+	ctrl = DBGP_LEN_UPDATE(ctrl, size);
+	ctrl &= ~DBGP_OUT;
+	ctrl |= DBGP_GO;
+		
+	writel(addr, &ehci_debug->address);
+	writel(pids, &ehci_debug->pids);
+	ret = dbgp_wait_until_done(ehci_debug, ctrl);
+	if (ret < 0)
+		return ret;
+	if (size > ret)
+		size = ret;
+	dbgp_get_data(ehci_debug, data, size);
+	return ret;
+}
+int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size)
+{
+	return dbgp_bulk_read(dbg_info->ehci_debug, dbg_info->devnum, dbg_info->endpoint_in, data, size);
+}
+
+static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, int requesttype, int request, 
+	int value, int index, void *data, int size)
+{
+	unsigned pids, addr, ctrl;
+	struct usb_ctrlrequest req;
+	int read;
+	int ret;
+
+	read = (requesttype & USB_DIR_IN) != 0;
+	if (size > (read?DBGP_MAX_PACKET:0))
+		return -1;
+	
+	/* Compute the control message */
+	req.bRequestType = requesttype;
+	req.bRequest = request;
+	req.wValue = value;
+	req.wIndex = index;
+	req.wLength = size;
+
+	pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
+	addr = DBGP_EPADDR(devnum, 0);
+
+	ctrl = readl(&ehci_debug->control);
+	ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req));
+	ctrl |= DBGP_OUT;
+	ctrl |= DBGP_GO;
+
+	/* Send the setup message */
+	dbgp_set_data(ehci_debug, &req, sizeof(req));
+	writel(addr, &ehci_debug->address);
+	writel(pids, &ehci_debug->pids);
+	ret = dbgp_wait_until_done(ehci_debug, ctrl);
+	if (ret < 0)
+		return ret;
+
+
+	/* Read the result */
+	ret = dbgp_bulk_read(ehci_debug, devnum, 0, data, size);
+	return ret;
+}
+
+static int ehci_reset_port(struct ehci_regs *ehci_regs, int port)
+{
+	unsigned portsc;
+	unsigned delay_time, delay;
+	int loop;
+
+	/* Reset the usb debug port */
+	portsc = readl(&ehci_regs->port_status[port - 1]);
+	portsc &= ~PORT_PE;
+	portsc |= PORT_RESET;
+	writel(portsc, &ehci_regs->port_status[port - 1]);
+
+	delay = HUB_ROOT_RESET_TIME;
+	for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
+	     delay_time += delay) {
+		dbgp_mdelay(delay);
+
+		portsc = readl(&ehci_regs->port_status[port - 1]);
+		if (portsc & PORT_RESET) {
+			/* force reset to complete */
+			loop = 2;
+			writel(portsc & ~(PORT_RWC_BITS | PORT_RESET), 
+				&ehci_regs->port_status[port - 1]);
+			do {	
+				dbgp_mdelay(delay);
+				portsc = readl(&ehci_regs->port_status[port - 1]);
+				delay_time += delay;
+			} while ((portsc & PORT_RESET) && (--loop > 0));
+			if (!loop) {
+				printk_debug("ehci_reset_port forced done");
+			}
+		}
+
+		/* Device went away? */
+		if (!(portsc & PORT_CONNECT))
+			return -107;//-ENOTCONN;
+
+		/* bomb out completely if something weird happend */
+		if ((portsc & PORT_CSC))
+			return -22;//-EINVAL;
+
+		/* If we've finished resetting, then break out of the loop */
+		if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
+			return 0;
+	}
+	return -16;//-EBUSY;
+}
+
+static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
+{
+	unsigned status;
+	int ret, reps;
+	for (reps = 0; reps < 3; reps++) {
+		dbgp_mdelay(100);
+		status = readl(&ehci_regs->status);
+		if (status & STS_PCD) {
+			ret = ehci_reset_port(ehci_regs, port);
+			if (ret == 0)
+				return 0;
+		}
+	}
+	return -107; //-ENOTCONN;
+}
+
+
+#define DBGP_DEBUG 1
+#if DBGP_DEBUG
+# define dbgp_printk printk_debug
+#else
+#define dbgp_printk(fmt, arg...)   do {} while(0)
+#endif
+static void usbdebug_direct_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info)
+{
+	struct ehci_caps *ehci_caps;
+	struct ehci_regs *ehci_regs;
+	struct ehci_dbg_port *ehci_debug;
+	unsigned dbgp_endpoint_out;
+	unsigned dbgp_endpoint_in;
+	struct usb_debug_descriptor dbgp_desc;
+	unsigned ctrl, devnum;
+	int ret;
+	unsigned delay_time, delay;
+	int loop;
+
+	unsigned cmd,  status, portsc, hcs_params, debug_port, n_ports, new_debug_port;
+	int i;
+	unsigned port_map_tried;
+
+	unsigned playtimes = 3;
+
+	ehci_caps  = (struct ehci_caps *)ehci_bar;
+	ehci_regs  = (struct ehci_regs *)(ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase)));
+	ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
+
+	info->ehci_debug = (void *)0;
+
+try_next_time:
+	port_map_tried = 0;
+
+try_next_port:
+	hcs_params = readl(&ehci_caps->hcs_params);
+	debug_port = HCS_DEBUG_PORT(hcs_params);
+	n_ports    = HCS_N_PORTS(hcs_params);
+
+	dbgp_printk("debug_port: %d\n", debug_port);
+	dbgp_printk("n_ports:    %d\n", n_ports);
+
+#if 0
+        for (i = 1; i <= n_ports; i++) {
+                portsc = readl(&ehci_regs->port_status[i-1]);
+                dbgp_printk("portstatus%d: %08x\n", i, portsc);
+        }
+#endif
+
+	if(port_map_tried && (new_debug_port!=debug_port)) {
+		if(--playtimes) {
+			set_debug_port(debug_port);
+			goto try_next_time;
+		}
+		return;	
+	}
+
+	/* Reset the EHCI controller */
+	loop = 10;
+	cmd = readl(&ehci_regs->command);
+	cmd |= CMD_RESET;
+	writel(cmd, &ehci_regs->command);
+	do {
+		cmd = readl(&ehci_regs->command);
+	} while ((cmd & CMD_RESET) && (--loop > 0));
+
+	if(!loop) {
+		dbgp_printk("can not reset ehci\n");
+		return;
+	}
+	dbgp_printk("ehci reset done\n");
+
+	/* Claim ownership, but do not enable yet */
+	ctrl = readl(&ehci_debug->control);
+	ctrl |= DBGP_OWNER;
+	ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
+	writel(ctrl, &ehci_debug->control);
+
+	/* Start the ehci running */
+	cmd = readl(&ehci_regs->command);
+	cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
+	cmd |= CMD_RUN;
+	writel(cmd, &ehci_regs->command);
+
+	/* Ensure everything is routed to the EHCI */
+	writel(FLAG_CF, &ehci_regs->configured_flag);
+
+	/* Wait until the controller is no longer halted */
+	loop = 10;
+	do {
+		status = readl(&ehci_regs->status);
+	} while ((status & STS_HALT) && (--loop>0));
+
+	if(!loop) {
+		dbgp_printk("ehci can be started\n");
+		return;
+	}
+	dbgp_printk("ehci started\n");
+
+	/* Wait for a device to show up in the debug port */
+	ret = ehci_wait_for_port(ehci_regs, debug_port);
+	if (ret < 0) {
+		dbgp_printk("No device found in debug port %d\n", debug_port);
+		goto next_debug_port;
+	}
+	dbgp_printk("ehci wait for port done\n");
+
+	/* Enable the debug port */
+	ctrl = readl(&ehci_debug->control);
+	ctrl |= DBGP_CLAIM;
+	writel(ctrl, &ehci_debug->control);
+	ctrl = readl(&ehci_debug->control);
+	if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) {
+		dbgp_printk("No device in debug port\n");
+		writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control);
+		goto err;
+	}
+	dbgp_printk("debug ported enabled\n");
+
+	/* Completely transfer the debug device to the debug controller */
+	portsc = readl(&ehci_regs->port_status[debug_port - 1]);
+	portsc &= ~PORT_PE;
+	writel(portsc, &ehci_regs->port_status[debug_port - 1]);
+
+	dbgp_mdelay(100);
+
+	/* Find the debug device and make it device number 127 */
+	for (devnum = 0; devnum <= 127; devnum++) {
+		ret = dbgp_control_msg(ehci_debug, devnum,
+			USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+			USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
+			&dbgp_desc, sizeof(dbgp_desc));
+		if (ret > 0)
+			break;
+	}
+	if (devnum > 127) {
+		dbgp_printk("Could not find attached debug device\n");
+		goto err;
+	}
+	if (ret < 0) {
+		dbgp_printk("Attached device is not a debug device\n");
+		goto err;
+	}
+	dbgp_endpoint_out = dbgp_desc.bDebugOutEndpoint;
+	dbgp_endpoint_in = dbgp_desc.bDebugInEndpoint;
+
+	/* Move the device to 127 if it isn't already there */
+	if (devnum != USB_DEBUG_DEVNUM) {
+		ret = dbgp_control_msg(ehci_debug, devnum,
+			USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+			USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, (void *)0, 0);
+		if (ret < 0) {
+			dbgp_printk("Could not move attached device to %d\n", 
+				USB_DEBUG_DEVNUM);
+			goto err;
+		}
+		devnum = USB_DEBUG_DEVNUM;
+		dbgp_printk("debug device renamed to 127\n");
+	}
+
+	/* Enable the debug interface */
+	ret = dbgp_control_msg(ehci_debug, USB_DEBUG_DEVNUM,
+		USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
+		USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE, 0, (void *)0, 0);
+	if (ret < 0) {
+		dbgp_printk(" Could not enable the debug device\n");
+		goto err;
+	}
+	dbgp_printk("debug interface enabled\n");
+
+	/* Perform a small write to get the even/odd data state in sync
+	 */
+	ret = dbgp_bulk_write(ehci_debug, USB_DEBUG_DEVNUM, dbgp_endpoint_out, " ",1);
+	if (ret < 0) {
+		dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
+		goto err;
+	}
+	dbgp_printk("small write doned\n");
+
+	info->ehci_caps = ehci_caps;
+	info->ehci_regs = ehci_regs;
+	info->ehci_debug = ehci_debug;
+	info->devnum = devnum;
+	info->endpoint_out = dbgp_endpoint_out;
+	info->endpoint_in = dbgp_endpoint_in;
+	
+	return;
+err:
+	/* Things didn't work so remove my claim */
+	ctrl = readl(&ehci_debug->control);
+	ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
+	writel(ctrl, &ehci_debug->control);
+
+next_debug_port:
+	port_map_tried |= (1<<(debug_port-1));
+	if(port_map_tried != ((1<<n_ports) -1)) {
+		new_debug_port = ((debug_port-1+1)%n_ports) + 1;
+		set_debug_port(new_debug_port);
+		goto try_next_port;
+	}
+	if(--playtimes) {
+		set_debug_port(debug_port);
+		goto try_next_time;
+	}
+
+}
+
+
Index: src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c.orig
+++ src/northbridge/amd/amdk8/coherent_ht.c
@@ -1,10 +1,3 @@
-#if USE_DCACHE_RAM
-
-#include "coherent_ht_car.c"
-
-#else
-
-
 /* coherent hypertransport initialization for AMD64 
  * 
  * written by Stefan Reinauer <stepan@openbios.org>
@@ -74,6 +67,7 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include "arch/romcc_io.h"
+
 #include "amdk8.h"
 
 #define enable_bsp_routing()	enable_routing(0)
@@ -84,8 +78,6 @@
 
 #define DEFAULT 0x00010101	/* default row entry */
 
-typedef uint8_t u8;
-typedef uint32_t u32;
 
 #ifndef CROSS_BAR_47_56
 	#define CROSS_BAR_47_56 0
@@ -101,21 +93,25 @@ typedef uint32_t u32;
 
 #ifndef K8_HT_CHECK_PENDING_LINK
 	#if CONFIG_MAX_PHYSICAL_CPUS >= 4
-	#define K8_HT_CHECK_PENDING_LINK 1
+		#define K8_HT_CHECK_PENDING_LINK 1
 	#else
-	#define K8_HT_CHECK_PENDING_LINK 0
+		#define K8_HT_CHECK_PENDING_LINK 0
 	#endif
 #endif
 
 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
-#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
+	#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
+#endif
+
+#ifndef ENABLE_APIC_EXT_ID
+        #define ENABLE_APIC_EXT_ID 0
 #endif
 
 
 static inline void print_linkn (const char *strval, uint8_t byteval) 
 {
 #if 1
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 	printk_debug("%s%02x\r\n", strval, byteval); 
 #else
 	print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
@@ -162,6 +158,19 @@ static void disable_probes(void)
 
 }
 
+static void enable_apic_ext_id(u8 node) 
+{
+#if ENABLE_APIC_EXT_ID==1
+#warning "FIXME Is the right place to enable apic ext id here?"
+
+      u32 val;
+
+        val = pci_read_config32(NODE_HT(node), 0x68);
+        val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
+        pci_write_config32(NODE_HT(node), 0x68, val);
+#endif
+}
+
 static void enable_routing(u8 node)
 {
 	u32 val;
@@ -199,17 +208,6 @@ static void enable_routing(u8 node)
 	print_spew(" done.\r\n");
 }
 
-static void enable_apic_ext_id(u8 node)
-{
-
-	u32 val;
-
-        val = pci_read_config32(NODE_HT(node), 0x68);
-        val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
-        pci_write_config32(NODE_HT(node), 0x68, val);
-}
-
-
 static void fill_row(u8 node, u8 row, u32 value)
 {
 	pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
@@ -259,23 +257,6 @@ static void rename_temp_node(u8 node)
 
 	print_spew(" done.\r\n");
 }
-#if K8_HT_CHECK_PENDING_LINK == 1
-static void wait_ht_stable(uint8_t node)
-{       
-        uint8_t linkn;
-        for(linkn = 0; linkn<3; linkn++) {
-                uint8_t regpos;
-                uint16_t i;
-                uint32_t reg;
-                regpos = 0x98 + 0x20 * linkn;
-                for(i = 0; i < 0xff; i++) { //wait to make sure it is done
-                        reg = pci_read_config32(NODE_HT(node), regpos);
-                        if ((reg & 0x10) == 0) break; // init complete
-                        udelay(10);
-                } 
-        }
-}
-#endif
 
 static int verify_connection(u8 dest)
 {
@@ -293,18 +274,23 @@ static int verify_connection(u8 dest)
 	return 1;
 }
 
-static unsigned read_freq_cap(device_t dev, unsigned pos)
+static uint16_t read_freq_cap(device_t dev, uint8_t pos)
 {
 	/* Handle bugs in valid hypertransport frequency reporting */
-	unsigned freq_cap;
+	uint16_t freq_cap;
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
-	if (!is_cpu_pre_e0()) {
+#if K8_HT_FREQ_1G_SUPPORT == 1
+    #if K8_REV_F_SUPPORT == 0
+	if (!is_cpu_pre_e0())
+    #endif 
+	{
 		return freq_cap;
 	}
+#endif
 
 	id = pci_read_config32(dev, 0);
 
@@ -320,8 +306,8 @@ static int optimize_connection(device_t 
 {
 	static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
 	static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
-	uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask;
-	uint8_t width_cap1, width_cap2, width_cap, width, old_width, ln_width1, ln_width2;
+	uint16_t freq_cap1, freq_cap2;
+	uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
 	uint8_t freq, old_freq;
 	int needs_reset;
 	/* Set link width and frequency */
@@ -369,6 +355,7 @@ static int optimize_connection(device_t 
 	
 	/* See if I am changing node1's width */
 	old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
+	old_width &= 0x77;	
 	needs_reset |= old_width != width;
 
 	/* Set node1's widths */
@@ -379,10 +366,12 @@ static int optimize_connection(device_t 
 
 	/* See if I am changing node2's width */
 	old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
+	old_width &= 0x77;
 	needs_reset |= old_width != width;
 
 	/* Set node2's widths */
 	pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
+
 	return needs_reset;
 }
 
@@ -676,11 +665,6 @@ static void setup_uniprocessor(void)
 	disable_probes();
 }
 
-struct setup_smp_result {
-	int nodes;
-	int needs_reset;
-};
-
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 static int optimize_connection_group(const u8 *opt_conn, int num) {
 	int needs_reset = 0;
@@ -695,21 +679,20 @@ static int optimize_connection_group(con
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-static struct setup_smp_result setup_smp2(void)
+static unsigned setup_smp2(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
-	result.nodes = 2;
-	result.needs_reset = 0;
+	nodes = 2;
 
 	setup_row_local(0, 0); /* it will update the broadcast RT*/
 	
 	val = get_row(0,0);
 	byte = (val>>16) & 0xfe;
 	if(byte<0x2) { /* no coherent connection so get out.*/
-		result.nodes = 1;
-		return result;
+		nodes = 1;
+		return nodes;
 	}
 
 	/* Setup and check a temporary connection to node 1 */
@@ -766,24 +749,19 @@ static struct setup_smp_result setup_smp
 	clear_temp_row(0);
 #endif
 
-	result.needs_reset |= optimize_connection(
-		NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
-		NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
-
-	return result;
+	return nodes;
 }
 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 
-static struct setup_smp_result setup_smp4(int needs_reset)
+static unsigned setup_smp4(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=4;
-	result.needs_reset = needs_reset;
+	nodes=4;
 
 	/* Setup and check temporary connection from Node 0 to Node 2 */
 	val = get_row(0,0);
@@ -791,8 +769,8 @@ static struct setup_smp_result setup_smp
 	byte = get_linkn_last_count(byte);
 
 	if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
-		result.nodes = 2;
-		return result;
+		nodes = 2;
+		return nodes;
 	}
 
 	byte &= 3; /* bit [3,2] is count-1*/
@@ -940,16 +918,7 @@ static struct setup_smp_result setup_smp
 	clear_temp_row(1);
 #endif
 
-	/* optimize physical connections - by LYH */
-	static const u8 opt_conn4[] = {
-		0,2,
-		1,3,
-		2,3,
-	};
-
-	result.needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
-
-	return result;
+	return nodes;
 
 }
 
@@ -957,14 +926,13 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
 
-static struct setup_smp_result setup_smp6(int needs_reset)
+static unsigned setup_smp6(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=6;
-	result.needs_reset = needs_reset;
+	nodes=6;
 
 	/* Setup and check temporary connection from Node 0 to Node 4  through 2*/
         val = get_row(2,2);
@@ -972,8 +940,8 @@ static struct setup_smp_result setup_smp
         byte = get_linkn_last_count(byte);
 
         if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
-                result.nodes = 4;
-                return result;
+                nodes = 4;
+                return nodes;
         }
 
 	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3*/
@@ -982,8 +950,8 @@ static struct setup_smp_result setup_smp
         byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
         byte = get_linkn_last_count(byte);
         if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
-                result.nodes = 4;
-                return result;
+                nodes = 4;
+                return nodes;
         }
 	
 	/* We found 6 nodes so far. Now setup all nodes for 6p */
@@ -1153,17 +1121,7 @@ static struct setup_smp_result setup_smp
 	}
 #endif
 
-	/* optimize physical connections - by LYH */
-	static const uint8_t opt_conn6[] ={
-		2, 4,
-		3, 5,
-#if !CROSS_BAR_47_56
-		4, 5,
-#endif
-	}; 
-	result.needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
-
-	return result;
+	return nodes;
 
 }
 
@@ -1171,14 +1129,13 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
 
-static struct setup_smp_result setup_smp8(int needs_reset)
+static unsigned setup_smp8(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=8;
-	result.needs_reset = needs_reset;
+	nodes=8;
 
 	/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
 	val = get_row(4,4);
@@ -1188,16 +1145,16 @@ static struct setup_smp_result setup_smp
 	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
         byte = get_linkn_last_count(byte); /* Max link to 6*/
         if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
-                result.nodes = 6;
-                return result;
+                nodes = 6;
+                return nodes;
         }
 #endif
 
 #if CROSS_BAR_47_56 
 	byte = get_linkn_last_count(byte); /* Max link to 6*/
 	if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
-		result.nodes = 6;
-		return result;
+		nodes = 6;
+		return nodes;
 	}
 #if TRY_HIGH_FIRST == 1
 	byte = ((val>>16) & 0xfe) - link_connection(4,2);
@@ -1215,8 +1172,8 @@ static struct setup_smp_result setup_smp
         byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
         byte = get_linkn_last_count(byte);
         if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
-                result.nodes = 6;
-                return result;
+                nodes = 6;
+                return nodes;
         }
 #endif
 
@@ -1232,6 +1189,7 @@ static struct setup_smp_result setup_smp
 		3, 6,
 		/*3, 7,*/
 		/*4, 7,*/
+		5, 6,
 #else
 		0, 6, 2, 0,
 		/*0, 7, 2, 0,*/
@@ -1513,19 +1471,7 @@ static struct setup_smp_result setup_smp
 /* ready to enable RT for Node 7 */
 	enable_routing(7);      /* enable routing on node 7 (temp.) */
 
-	static const uint8_t opt_conn8[] ={
-		4, 6,
-#if CROSS_BAR_47_56
-		4, 7,
-		5, 6,
-#endif
-		5, 7,
-		6, 7,
-	};
-	/* optimize physical connections - by LYH */
-	result.needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
-
-	return result;
+	return nodes;
 }
 
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
@@ -1533,36 +1479,36 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 
-static struct setup_smp_result setup_smp(void)
+static unsigned setup_smp(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 
 	print_spew("Enabling SMP settings\r\n");
 		
-	result = setup_smp2();
+	nodes = setup_smp2();
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-	if(result.nodes == 2) 
-		result = setup_smp4(result.needs_reset);
+	if(nodes == 2) 
+		nodes = setup_smp4();
 #endif
 	
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
-	if(result.nodes == 4)
-		result = setup_smp6(result.needs_reset);
+	if(nodes == 4)
+		nodes = setup_smp6();
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
-	if(result.nodes == 6) 
-		result = setup_smp8(result.needs_reset);
+	if(nodes == 6) 
+		nodes = setup_smp8();
 #endif
 
-#if CONFIG_USE_INIT
-	printk_debug("%02x nodes initialized.\r\n", result.nodes);
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("%02x nodes initialized.\r\n", nodes);
 #else
-	print_debug_hex8(result.nodes);
+	print_debug_hex8(nodes);
 	print_debug(" nodes initialized.\r\n");
 #endif
 	
-	return result;
+	return nodes;
 }
 
 static unsigned verify_mp_capabilities(unsigned nodes)
@@ -1601,7 +1547,7 @@ static void clear_dead_routes(unsigned n
 {
 	int last_row;
 	int node, row;
-#if CONFIG_MAX_PHYSICAL_CPUS > 6
+#if CONFIG_MAX_PHYSICAL_CPUS == 8
 	if(nodes==8) return;/* don't touch (7,7)*/
 #endif
 	last_row = nodes;
@@ -1625,9 +1571,9 @@ static void clear_dead_routes(unsigned n
 }
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-static unsigned count_cpus(unsigned nodes)
-{
 #if CONFIG_LOGICAL_CPUS==1
+static unsigned verify_dualcore(unsigned nodes)
+{
 	unsigned node, totalcpus, tmp;
 
 	totalcpus = 0;
@@ -1637,25 +1583,27 @@ static unsigned count_cpus(unsigned node
 	}
 
 	return totalcpus;
-#else
-	return nodes;
-#endif
 		
 }
-static inline unsigned get_nodes(void)
-{
-        return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
-}
+#endif
 
 static void coherent_ht_finalize(unsigned nodes)
 {
-	unsigned total_cpus;
-	unsigned cpu_node_count;
 	unsigned node;
+#if K8_REV_F_SUPPORT == 0
 	int rev_a0;
-	total_cpus = count_cpus(nodes);
-	cpu_node_count = ((total_cpus -1)<<16)|((nodes - 1) << 4);
+#endif
+#if CONFIG_LOGICAL_CPUS==1
+	unsigned total_cpus;
 
+	if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+		total_cpus = verify_dualcore(nodes);
+	}
+	else {
+		total_cpus = nodes;
+	}
+#endif
+	
 	/* set up cpu count and node count and enable Limit
 	 * Config Space Range for all available CPUs.
 	 * Also clear non coherent hypertransport bus range
@@ -1663,7 +1611,9 @@ static void coherent_ht_finalize(unsigne
 	 */
 
 	print_spew("coherent_ht_finalize\r\n");
+#if K8_REV_F_SUPPORT == 0
 	rev_a0 = is_cpu_rev_a0();
+#endif
 	for (node = 0; node < nodes; node++) {
 		device_t dev;
 		uint32_t val;
@@ -1672,7 +1622,11 @@ static void coherent_ht_finalize(unsigne
 		/* Set the Total CPU and Node count in the system */
 		val = pci_read_config32(dev, 0x60);
 		val &= (~0x000F0070);
-		val |= cpu_node_count;
+#if CONFIG_LOGICAL_CPUS==1
+		val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
+#else
+		val |= ((nodes-1)<<16)|((nodes-1)<<4);
+#endif
 		pci_write_config32(dev, 0x60, val);
 
 		/* Only respond to real cpu pci configuration cycles
@@ -1688,23 +1642,27 @@ static void coherent_ht_finalize(unsigne
 			(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
 		pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
 
+#if K8_REV_F_SUPPORT == 0
 		if (rev_a0) {
 			pci_write_config32(dev, 0x94, 0);
 			pci_write_config32(dev, 0xb4, 0);
 			pci_write_config32(dev, 0xd4, 0);
 		}
+#endif
 	}
 
 	print_spew("done\r\n");
 }
 
-static int apply_cpu_errata_fixes(unsigned nodes, int needs_reset)
+static int apply_cpu_errata_fixes(unsigned nodes)
 {
 	unsigned node;
+	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
+#if K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1746,13 +1704,15 @@ static int apply_cpu_errata_fixes(unsign
 				needs_reset = 1; /* Needed? */
 			}
 		}
+#endif
 	}
 	return needs_reset;
 }
 
-static int optimize_link_read_pointers(unsigned nodes, int needs_reset)
+static int optimize_link_read_pointers(unsigned nodes)
 {
 	unsigned node;
+	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
 		device_t f0_dev, f3_dev;
 		uint32_t cmd_ref, cmd;
@@ -1782,58 +1742,98 @@ static int optimize_link_read_pointers(u
 	return needs_reset;
 }
 
-static void startup_other_cores(unsigned nodes)
+static inline unsigned get_nodes(void)
 {
-	unsigned node;
-	for(node = 0; node < nodes; node++) {
-		device_t dev;
-		unsigned siblings;
-		dev = NODE_MC(node);
-		siblings = (pci_read_config32(dev, 0xe8) >> 12) & 0x3;
-
-		if (siblings) {
-			device_t dev_f0;
-			unsigned val;
-			/* Redirect all MC4 accesses and error logging to core0 */
-			val = pci_read_config32(dev, 0x44);
-			val |= (1 << 27); //NbMcaToMstCpuEn bit
-			pci_write_config32(dev, 0x44, val);
-
-			/* Enable the second core */
-			dev_f0 = NODE_HT(node);
-			val = pci_read_config32(dev_f0, 0x68);
-			val |= ( 1 << 5);
-			pci_write_config32(dev_f0, 0x68, val);
-		}
-	}
+        return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
 }
 
+static int optimize_link_coherent_ht(void)
+{
+        int needs_reset = 0;
+
+        unsigned nodes;
 
+        nodes = get_nodes();
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+        if(nodes>1) {
+                needs_reset |= optimize_connection(
+                        NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
+                        NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
+        }
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+        if(nodes>2) {
+        /* optimize physical connections - by LYH */
+                static const u8 opt_conn4[] = {
+                        0,2,
+                        1,3,
+                        2,3,
+                };
+                needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
+        }
+#endif
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 4
+        if(nodes>4) {
+                static const uint8_t opt_conn6[] ={
+                        2, 4,
+                        3, 5,
+        #if !CROSS_BAR_47_56
+                        4, 5,
+        #endif
+                };
+                needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
+        }
+#endif
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 6
+        if(nodes>6) {
+               static const uint8_t opt_conn8[] ={
+                       4, 6,
+        #if CROSS_BAR_47_56
+                       4, 7,
+                       5, 6,
+        #endif
+                       5, 7,
+                       6, 7,
+               };
+                needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
+        }
+#endif
+
+#endif
+
+        needs_reset |= apply_cpu_errata_fixes(nodes);
+        needs_reset |= optimize_link_read_pointers(nodes);
+
+        return needs_reset;
+}
+
+#if RAMINIT_SYSINFO == 1
+static void setup_coherent_ht_domain(void)
+#else
 static int setup_coherent_ht_domain(void)
+#endif
 {
-	struct setup_smp_result result;
-	result.nodes = 1;
-	result.needs_reset = 0;
-
-#if K8_HT_CHECK_PENDING_LINK == 1 
-	//needed?
-        wait_ht_stable(0);
-#endif	
+	unsigned nodes;
+	nodes = 1;
+
 	enable_bsp_routing();
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-	result = setup_smp();
-	result.nodes = verify_mp_capabilities(result.nodes);
-	clear_dead_routes(result.nodes);
+        nodes = setup_smp();
+        nodes = verify_mp_capabilities(nodes);
+        clear_dead_routes(nodes);
 #endif
-	if (result.nodes == 1) {
+
+	if (nodes == 1) {
 		setup_uniprocessor();
 	}
-	coherent_ht_finalize(result.nodes);
-	startup_other_cores(result.nodes);
-	result.needs_reset = apply_cpu_errata_fixes(result.nodes, result.needs_reset);
-	result.needs_reset = optimize_link_read_pointers(result.nodes, result.needs_reset);
-	return result.needs_reset;
-}
+	coherent_ht_finalize(nodes);
 
+#if RAMINIT_SYSINFO == 0
+	return optimize_link_coherent_ht();
 #endif
+}
+
Index: src/northbridge/amd/amdk8/raminit.c
===================================================================
--- src/northbridge/amd/amdk8/raminit.c.orig
+++ src/northbridge/amd/amdk8/raminit.c
@@ -485,6 +485,14 @@ static void sdram_set_registers(const st
 	 * [31:26] Reserved
 	 */
 	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
+	/* MCA NB Status Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
+	/* MCA NB Status high reg */
+	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
+	/* MCA NB address Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
+	/* MCA NB address high reg */
+	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
 	/* DRAM Scrub Control Register
 	 * F3:0x58
 	 * [ 4: 0] DRAM Scrube Rate
@@ -2334,6 +2342,16 @@ static void sdram_enable(int controllers
 	/* And if necessary toggle the the reset on the dimms by hand */
 	memreset(controllers, ctrl);
 
+	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
+#if 0
+	print_debug("prepare to InitDram:");
+	for(i=0; i<100; i++) {
+		print_debug_hex32(i);
+		print_debug("\b\b\b\b\b\b\b\b");
+	}
+	print_debug("\r\n");
+#endif
+
 	for(i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
 		if (!controller_present(ctrl + i))
Index: src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- src/northbridge/amd/amdk8/northbridge.c.orig
+++ src/northbridge/amd/amdk8/northbridge.c
@@ -103,12 +103,6 @@ static unsigned int amdk8_nodeid(device_
 
 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 {
-#if 0
-	printk_debug("%s amdk8_scan_chains max: %d starting...\n", 
-		dev_path(dev), max);
-#endif
-//	I want to put sb chain in bus 0 can I?
-
 	 
 		uint32_t link_type;
 		int i;
@@ -212,10 +206,6 @@ static unsigned int amdk8_scan_chain(dev
 			((dev->link[link].subordinate) << 24);
 		f1_write_config32(config_reg, config_busses);
 
-#if 0
-		printk_debug("%s Hyper transport scan link: %d max: %d\n", 
-			dev_path(dev), link, max);
-#endif
 		/* Now we can scan all of the subordinate busses i.e. the
 		 * chain on the hypertranport link 
 		 */
@@ -224,11 +214,6 @@ static unsigned int amdk8_scan_chain(dev
 		}
 		max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, ht_unitid_base, offset_unitid);
 
-#if 0
-		printk_debug("%s Hyper transport scan link: %d new max: %d\n",
-			dev_path(dev), link, max);
-#endif		
-
 		/* We know the number of busses behind this bridge.  Set the
 		 * subordinate bus number to it's real value
 		 */
@@ -254,11 +239,6 @@ static unsigned int amdk8_scan_chain(dev
 
 		}
 
-#if 0
-		printk_debug("%s Hypertransport scan link: %d done\n",
-			dev_path(dev), link);
-#endif
-
 	return max;
 }
 
@@ -271,11 +251,6 @@ static unsigned int amdk8_scan_chains(de
         nodeid = amdk8_nodeid(dev);
 	
 
-#if 0
-        printk_debug("%s amdk8_scan_chains max: %d starting...\n",
-                dev_path(dev), max);
-#endif
-//      I want to put sb chain in bus 0 
 
         if(nodeid==0) {
                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
@@ -301,10 +276,6 @@ static unsigned int amdk8_scan_chains(de
 
 		max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
         }
-#if 0
-        printk_debug("%s amdk8_scan_chains max: %d done\n",
-                dev_path(dev), max);
-#endif
         return max;
 }
 
@@ -332,12 +303,7 @@ static int reg_useable(unsigned reg, 
 			result = 1;
 		}
 	}
-#if 0
-	printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
-		reg, result, 
-		goal_nodeid, goal_link, 
-		nodeid, link);
-#endif
+
 	return result;
 }
 
@@ -1258,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_
 		if (dev && dev->enabled) {
 			j = pci_read_config32(dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\r\n", dev_path(dev), j);
+			printk_debug("  %s siblings=%d\n", dev_path(dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... 
Index: src/northbridge/amd/amdk8/early_ht.c
===================================================================
--- src/northbridge/amd/amdk8/early_ht.c.orig
+++ src/northbridge/amd/amdk8/early_ht.c
@@ -13,6 +13,8 @@ static void enumerate_ht_chain(void)
 	 * links needs to be programed to point at bus 0.
 	 */
 	unsigned next_unitid, last_unitid;
+	unsigned temp_unitid;
+	unsigned not_use_count;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 	//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
 	unsigned real_last_unitid;
@@ -60,14 +62,21 @@ static void enumerate_ht_chain(void)
 					unsigned ctrl, ctrl_off;
 
 					flags &= ~0x1f;
-					flags |= next_unitid & 0x1f;
 					count = (flags >> 5) & 0x1f;
+					not_use_count = 0;
+					temp_unitid = next_unitid;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-					real_last_unitid = next_unitid;
+					if ( (count + next_unitid) >= 0x20) { 
+						temp_unitid = HT_CHAIN_END_UNITID_BASE;
+						not_use_count = 1;
+					} 
+					real_last_unitid = temp_unitid;
 					real_last_pos = pos;
-					ht_dev_num++ ;
+					ht_dev_num++;
 #endif
-					next_unitid += count;
+					flags |= temp_unitid & 0x1f;
+					if(!not_use_count) 
+						next_unitid += count;
 
 					/* Test for end of chain */
 					ctrl_off = ((flags >> 10) & 1)?
@@ -87,8 +96,9 @@ static void enumerate_ht_chain(void)
 			pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
 		}
 	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	if(ht_dev_num>0) {
+	if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE)) {
 		uint16_t flags;
 		flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); 
                 flags &= ~0x1f;
Index: src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f.c.orig
+++ src/northbridge/amd/amdk8/raminit_f.c
@@ -79,16 +79,13 @@ static inline void print_t(const char *s
 	*/
 
 
-#if 1
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
 		unsigned long reg;
-
 		dev = register_values[i] & ~0xff;
 		where = register_values[i] & 0xff;
 		reg = pci_read_config32(dev, where);
@@ -97,7 +94,6 @@ static void setup_resource_map(const uns
 		pci_write_config32(dev, where, reg);
 	}
 }
-#endif
 
 static int controller_present(const struct mem_controller *ctrl)
 {
@@ -635,218 +631,13 @@ static void sdram_set_registers(const st
 			- poll the DctAccessDone untio it = 1
 		
 	*/
-#if 0
-	static const unsigned int index_register_values[] = {
-	/* Output Driver Compensation Control Register
-	 * Index: 0x00
-	 * [ 1: 0] CkeDrvStren (CKE Drive Strength)
-	 *	00 = 1.0x
-	 *	01 = 1.25x
-	 *	10 = 1.5x (Default)
-	 *	11 = 2.0x
-	 * [ 3: 2] reserved
-	 * [ 5: 4] CsOdtDrvStren (CS/ODT Drive Strength)
-         *      00 = 1.0x
-         *      01 = 1.25x
-         *      10 = 1.5x (Default)
-         *      11 = 2.0x
-         * [ 7: 6] reserved
-	 * [ 9: 8] AddrCmdDrvStren (Address/Command Drive Strength)
-         *      00 = 1.0x
-         *      01 = 1.25x
-         *      10 = 1.5x (Default)
-         *      11 = 2.0x
-         * [11:10] reserved
-	 * [13:12] ClkDrvStren (MEMCLK Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x 
-         *      11 = 1.5x
-         * [15:14] reserved
-         * [17:16] DataDrvStren (Data Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x
-         *      11 = 1.5x
-         * [19:18] reserved
-         * [21:20] DqsDrvStren (DQS Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x
-         *      11 = 1.5x
-         * [27:22] reserved
-         * [29:28] ProcOdt ( Processor On-die Termination)
-         *      00 = 300 ohms +/- 20%
-         *      01 = 150 ohms +/- 20%
-         *      10 = 75 ohms +/- 20%
-         *      11 = reserved
-         * [31:30] reserved
-	 */
-	0x00, 0xcfcccccc, 0x00000000, 
-	0x20, 0xcfcccccc, 0x00000000, 
-	/* Write Data Timing Low Control Register
-	 * Index 0x01
-	 * [ 5: 0] WrDatTimeByte0 (Write Data Byte 0 Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-	 * [ 7: 6] reserved
-         * [13: 8] WrDatTimeByte1 (Write Data Byte 1 Timing Control)
-         * [15:14] reserved
-         * [21:16] WrDatTimeByte2 (Write Data Byte 2 Timing Control)
-         * [23:22] reserved
-         * [29:24] WrDatTimeByte3 (Write Data Byte 3 Timing Control)
-         * [31:30] reserved
-	 */
-	0x01, 0xc0c0c0c0, 0x00000000,
-	0x21, 0xc0c0c0c0, 0x00000000,
-	/* Write Data Timing High Control Register
-	 * Index 0x02
-	 * [ 5: 0] WrDatTimeByte4 (Write Data Byte 4 Timing Control)
-	 * [ 7: 6] reserved
-         * [13: 8] WrDatTimeByte5 (Write Data Byte 5 Timing Control)
-         * [15:14] reserved
-         * [21:16] WrDatTimeByte6 (Write Data Byte 6 Timing Control)
-         * [23:22] reserved
-         * [29:24] WrDatTimeByte7 (Write Data Byte 7 Timing Control)
-         * [31:30] reserved
-	 */
-	0x02, 0xc0c0c0c0, 0x00000000,
-	0x22, 0xc0c0c0c0, 0x00000000,
-
-	/* Write Data ECC Timing Control Register
-	 * Index 0x03
-	 * [ 5: 0] WrChkTime (Write Data ECC Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-         * [31: 6] reserved
-	 */
-	0x03, 0x000000c0, 0x00000000,
-	0x23, 0x000000c0, 0x00000000,
-
-	/* Address Timing Control Register
-	 * Index 0x04
-	 * [ 4: 0] CkeFineDelay (CKE Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [ 5: 5] CkeSetup (CKE Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [ 7: 6] reserved
-	 * [12: 8] CsOdtFineDelay (CS/ODT Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [13:13] CsOdtSetup (CS/ODT Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [15:14] reserved
-	 * [20:16] AddrCmdFineDelay (Address/Command Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [21:21] AddrCmdSetup (Address/Command Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [31:22] reserved
-	 */
-	0x04, 0xffc0c0c0, 0x00000000,
-	0x24, 0xffc0c0c0, 0x00000000,
-
-	/* Read DQS Timing Low Control Register
-	 * Index 0x05
-	 * [ 5: 0] RdDqsTimeByte0 (Read DQS Byte 0 Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-	 * [ 7: 6] reserved
-         * [13: 8] RdDqsTimeByte1 (Read DQS Byte 1 Timing Control)
-         * [15:14] reserved
-         * [21:16] RdDqsTimeByte2 (Read DQS Byte 2 Timing Control)
-         * [23:22] reserved
-         * [29:24] RdDqsTimeByte3 (Read DQS Byte 3 Timing Control)
-         * [31:30] reserved
-	 */
-	0x05, 0xc0c0c0c0, 0x00000000,
-	0x25, 0xc0c0c0c0, 0x00000000,
-
-	/* Read DQS Timing High Control Register
-	 * Index 0x06
-	 * [ 5: 0] RdDqsTimeByte4 (Read DQS Byte 4 Timing Control)
-	 * [ 7: 6] reserved
-         * [13: 8] RdDqsTimeByte5 (Read DQS Byte 5 Timing Control)
-         * [15:14] reserved
-         * [21:16] RdDqsTimeByte6 (Read DQS Byte 6 Timing Control)
-         * [23:22] reserved
-         * [29:24] RdDqsTimeByte7 (Read DQS Byte 7 Timing Control)
-         * [31:30] reserved
-	 */
-	0x06, 0xc0c0c0c0, 0x00000000,
-	0x26, 0xc0c0c0c0, 0x00000000,
-
-	/* Read DQS ECC Timing Control Register
-	 * Index 0x07
-	 * [ 5: 0] RdDqsTimeCheck (Read DQS ECC Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-         * [31: 6] reserved
-	 */
-	0x07, 0x000000c0, 0x00000000,
-	0x27, 0x000000c0, 0x00000000,
-
-	/* DQS Receiver Enable Timing Control Register
-	 * Index 0x10, 0x13, 0x16, 0x19,
-	 * [ 7: 0] Dqs RcvEnDelay (DQS Receiver Enable Delay)
-	 *	0x00 =  0 ps
-	 *	0x01 = 50 ps
-	 *	0x02 = 100 ps
-	 *	...
-	 *	0xae = 8.7 ns
-	 *	0xaf-0xff = reserved
-         * [31: 6] reserved
-	 */
-	0x10, 0x000000ff, 0x00000000,
-	0x13, 0x000000ff, 0x00000000,
-	0x16, 0x000000ff, 0x00000000,
-	0x19, 0x000000ff, 0x00000000,
-	0x30, 0x000000ff, 0x00000000,
-	0x33, 0x000000ff, 0x00000000,
-	0x36, 0x000000ff, 0x00000000,
-	0x39, 0x000000ff, 0x00000000,
-	};
-#endif
-
 	int i;
 	int max;
 
-#if 1
         if (!controller_present(ctrl)) {
-//                print_debug("No memory controller present\r\n");
 		sysinfo->ctrl_present[ctrl->node_id] = 0;
                 return;
         }
-#endif
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 	
 	print_spew("setting up CPU");
@@ -865,20 +656,6 @@ static void sdram_set_registers(const st
 		pci_write_config32(dev, where, reg);
 	}
 
-#if 0
-	// for index regs
-	max = sizeof(index_register_values)/sizeof(index_register_values[0]);
-	for(i = 0; i < max; i += 3) {
-		unsigned long reg;
-		unsigned index;
-		index = register_values[i];
-		reg = pci_read_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index, reg);
-	}
-#endif
-
 	print_spew("done.\r\n");
 }
 
@@ -889,6 +666,19 @@ static int is_dual_channel(const struct 
 	return dcl & DCL_Width128;
 }
 
+static int is_opteron(const struct mem_controller *ctrl)
+{
+	/* Test to see if I am an Opteron.  
+	 * FIXME Testing dual channel capability is correct for now
+	 * but a beter test is probably required.
+	 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
+	 */
+#warning "FIXME implement a better test for opterons"
+	uint32_t nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	return !!(nbcap & NBCAP_128Bit);
+}
+
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -1456,6 +1246,20 @@ static long spd_handle_unbuffered_dimms(
 		} 
 	}
 
+	if (is_opteron(ctrl)) {
+#if 0
+		if ( registered != (dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
+			dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
+	//		die("Mixed buffered and registered dimms not supported");
+		}
+		//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
+		if (!registered) {
+			die("Unbuffered Dimms not supported on Opteron");
+		}
+#endif
+	}
+
+
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_UnBuffDimm;
 	meminfo->is_registered = 1;
@@ -1852,7 +1656,6 @@ static struct spd_set_memclk_result spd_
 		if (latencies < 0) goto hw_error;
 		if (latencies == 0) {
 			continue;
-//			goto dimm_err;
 		}
 
 		/* Compute the lowest cas latency supported */
@@ -1966,23 +1769,6 @@ static int update_dimm_Trfc(const struct
 	uint32_t dth;
 	int value;
 
-#if 0
-	int value2;
-
-	value = spd_read_byte(ctrl->channel0[i], SPD_TRFC);
-	if (value < 0) return -1;
-
-        value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1);
-	if(value2 & 1) value += 256;
-        value <<= 2;
-        value += convert_to_1_4(value2>>1);
-
-	if (value == 0) {
-		value = param->tRFC;
-	}
-	value *= 10;
-	clocks = (value + param->divisor - 1)/param->divisor;
-#endif
 	//get the cs_size --> logic dimm size
 	value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
         if (value < 0) {
@@ -1997,7 +1783,6 @@ static int update_dimm_Trfc(const struct
 
 	old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK);
 	if (old_clocks >= clocks) { // some one did it?
-//		clocks = old_clocks;
 		return 1;
 	}
 	dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3));
@@ -2072,7 +1857,6 @@ static int update_dimm_Tras(const struct
 	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
 	if (old_clocks >= clocks) { // someone did it?
-//		clocks = old_clocks;
 		return 1;
 	}
 	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
@@ -2397,6 +2181,7 @@ static void set_max_async_latency(const 
 	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
 
+	//FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
 	async_lat = 6+6;
 	
 	
@@ -2684,7 +2469,6 @@ static void sdram_set_spd_registers(cons
 	long dimm_mask;
 #if 1
 	if (!sysinfo->ctrl_present[ctrl->node_id]) {
-//		print_debug("No memory controller present\r\n");
 		return;
 	}
 #endif
@@ -2852,6 +2636,7 @@ static void sdram_enable(int controllers
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
         unsigned cpu_f0_f1[8];
+	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 	
 	print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
@@ -2886,6 +2671,14 @@ static void sdram_enable(int controllers
 
 	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
 	memreset(controllers, ctrl);
+#if 0
+	print_debug("prepare to InitDram:");
+	for(i=0; i<10; i++) {
+		print_debug_hex32(i);
+		print_debug("\b\b\b\b\b\b\b\b");
+	}
+	print_debug("\r\n");
+#endif
 
 	for(i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
@@ -3016,10 +2809,6 @@ static void sdram_enable(int controllers
                 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
         }
 
-#if 0
-        dump_pci_devices();
-        dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
-#endif
 
 #if MEM_TRAIN_SEQ ==  0
    #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
@@ -3056,11 +2845,6 @@ static void sdram_enable(int controllers
 	wait_all_core0_mem_trained(sysinfo);
 #endif
 
-#if 0
-        dump_pci_devices();
-        dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
-#endif
-
 }
 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
 {
Index: src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f_dqs.c.orig
+++ src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -107,15 +107,6 @@ static unsigned Get_MCTSysAddr(const str
 
 static unsigned Get_RcvrSysAddr(const struct mem_controller * ctrl, unsigned channel, unsigned cs_idx, struct sys_info *sysinfo)
 {
-#if 0
-	//get SB_64MuxedMode
-	uint32_t dword;
-	dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
-	if((dword & DCM_Mode64BitMux) == DCM_Mode64BitMux) {
-		if(channel) cs_idx += 4; // translate Receiver number to Chipsel
-	}
-#endif
-	
 	return Get_MCTSysAddr(ctrl, cs_idx, sysinfo);
 
 }
@@ -181,43 +172,6 @@ static void set_FSBASE(uint32_t addr_hi)
 
 }
 
-#if 0
-static void write_mem(uint32_t addr_hi, uint32_t addr_lo, uint32_t value) 
-{
-	if(addr_hi == 0) {
-		*((uint32_t *)addr_lo) = value;
-		return;
-	} 
-
-	set_FSBASE(addr_hi);
-
-        __asm__ volatile (
-		"movl %1, %%fs:(%0)\n\t"
-                :: "a" (addr_lo), "b" (value) 
-        );
-	
-}
-
-static uint32_t read_mem(uint32_t addr_hi, uint32_t addr_lo)
-{
-	unsigned value;
-        if(addr_hi == 0) {
-                value = *((uint32_t *)addr_lo);
-		return value; 
-        }
-
-	set_FSBASE(addr_hi);
-
-        __asm__ volatile (
-                "movl %%fs:(%1), %0\n\t"
-                :"=b"(value): "a" (addr_lo)
-        );
-	
-	return value;
-
-}
-#endif
-
 static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo)
 {
         unsigned enabled;
@@ -233,6 +187,7 @@ static unsigned ChipSelPresent(const str
 
 static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo)
 {
+	/* FIXME: process 64Muxed */
         if(!is_Width128) {
         	if(channel) return 0; // no channel b
         }
@@ -701,6 +656,7 @@ static unsigned TrainRcvrEn(const struct
 
 				/* Program current Receiver enable delay */
 				pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly);
+				/* FIXME: 64bit MUX */
 	
 				if(is_Width128) {
 					/* Program current Receiver enable delay chaannel b */
@@ -1164,6 +1120,7 @@ static unsigned TrainDQSPos(const struct
 
 	for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7
 		print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); 
+		//FIXME: process 64MUXedMode
 		if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue;
 		BanksPresent  = 1;
 
@@ -1454,6 +1411,7 @@ static unsigned TrainDQSRdWrPos(const st
 		}
 		channel++;
 		if(!is_Width128){
+			//FIXME: 64MuxMode??	
 			channel++; // skip channel if 64-bit mode
 		}
 	}
@@ -2030,11 +1988,15 @@ static inline void train_ram_on_node(uns
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
 	if(sysinfox->mem_trained[nodeid] == 0x80) {
+	#if 0
 		sysinfo->tom_k = sysinfox->tom_k;
 		sysinfo->tom2_k = sysinfox->tom2_k;
 		sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
 		sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
 		memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
+	#else
+		memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
+	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
 		print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n");
Index: src/northbridge/amd/amdk8/Config.lb
===================================================================
--- src/northbridge/amd/amdk8/Config.lb.orig
+++ src/northbridge/amd/amdk8/Config.lb
@@ -21,7 +21,7 @@ if HAVE_ACPI_TABLES
 	object amdk8_acpi.o
         makerule ssdt.c
                 depends "$(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
-                action  "iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
+                action  "/usr/sbin/iasl -tc $(TOP)/src/northbridge/amd/amdk8/ssdt.dsl"
                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex"
                 action  "mv ssdt.hex ssdt.c"
         end
Index: src/northbridge/amd/amdk8/debug.c
===================================================================
--- src/northbridge/amd/amdk8/debug.c.orig
+++ src/northbridge/amd/amdk8/debug.c
@@ -257,6 +257,48 @@ static void dump_spd_registers(const str
 		}
 	}
 }
+#if 0
+static void dump_smbusx_registers(unsigned index)
+{
+	unsigned device;
+        print_debug("\r\n");
+        for(device = 1; device < 0x80; device++) {
+                int j;
+		if( smbusx_read_byte(index, device, 0) < 0 ) continue;
+#if CONFIG_USE_PRINTK_IN_CAR
+		printk_debug("smbus: %02x", device);
+#else
+                print_debug("smbus: ");
+                print_debug_hex8(device);
+#endif
+                for(j = 0; j < 256; j++) {
+                	int status; 
+                        unsigned char byte;
+                        status = smbusx_read_byte(index, device, j);
+                        if (status < 0) {
+				break;
+                        }
+                        if ((j & 0xf) == 0) {
+#if CONFIG_USE_PRINTK_IN_CAR
+				printk_debug("\r\n%02x: ",j);
+#else
+                	        print_debug("\r\n");
+                                print_debug_hex8(j);
+                                print_debug(": ");
+#endif
+                        }
+                        byte = status & 0xff;
+#if CONFIG_USE_PRINTK_IN_CAR
+                        printk_debug("%02x ", byte);
+#else
+                        print_debug_hex8(byte);
+                        print_debug_char(' ');
+#endif
+                }
+                print_debug("\r\n");
+	}	
+}
+#endif
 static void dump_smbus_registers(void)
 {
 	unsigned device;
Index: src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/incoherent_ht.c.orig
+++ src/northbridge/amd/amdk8/incoherent_ht.c
@@ -162,6 +162,24 @@ static uint16_t ht_read_freq_cap(device_
 
 	return freq_cap;
 }
+static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
+{
+	uint8_t width_cap = pci_read_config8(dev, pos);
+
+	uint32_t id;
+
+	id = pci_read_config32(dev, 0);
+
+	/* netlogic micro cap doesn't support 16 bit yet */
+	if (id == (0x184e | (0x0001 << 16))) {
+		if((width_cap & 0x77) == 0x11) {
+			width_cap &= 0x88;
+		}
+	}
+	
+	return width_cap;
+	
+}
 #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
       (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
 
@@ -223,8 +241,8 @@ static int ht_optimize_link(
 	pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
 
 	/* Get the width capabilities */
-	width_cap1 = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1));
-	width_cap2 = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2));
+	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
+	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
@@ -402,6 +420,8 @@ static int ht_setup_chainx(device_t udev
 
 	uint8_t next_unitid, last_unitid;
 	unsigned uoffs;
+	uint8_t temp_unitid;
+	unsigned not_use_count;
 
 #if RAMINIT_SYSINFO == 0
 	int reset_needed = 0;
@@ -473,24 +493,34 @@ static int ht_setup_chainx(device_t udev
 
 		/* Update the Unitid of the current device */
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
-		flags &= ~0x1f; /* mask out the bse Unit ID */
-		flags |= next_unitid & 0x1f;
-		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
-
-		/* Note the change in device number */
-		dev = PCI_DEV(bus, next_unitid, 0);
-
                 /* Compute the number of unitids consumed */
                 count = (flags >> 5) & 0x1f;
+		flags &= ~0x1f; /* mask out the base Unit ID */
+
+		not_use_count = 0;
+		temp_unitid = next_unitid;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 		if(offset_unitid) {
-	                real_last_unitid = next_unitid;
+			if( (next_unitid + count) >= 0x20) {
+		                temp_unitid = HT_CHAIN_END_UNITID_BASE;
+				// keep to use the old next_unitid
+				not_use_count = 1;
+			} 
         	        real_last_pos = pos;
+			real_last_unitid = temp_unitid;
 			ht_dev_num++;
-		}
+		} 
 #endif
 
-                next_unitid += count;
+		flags |= temp_unitid & 0x1f;
+		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+
+		/* Note the change in device number */
+		dev = PCI_DEV(bus, temp_unitid, 0);
+
+		if(!not_use_count) 
+	                next_unitid += count;
+
 
 		/* Find which side of the ht link we are on,
 		 * by reading which direction our last write to PCI_CAP_FLAGS
@@ -525,7 +555,7 @@ static int ht_setup_chainx(device_t udev
 end_of_chain: ;
 	
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-        if(offset_unitid && (ht_dev_num>0)  ) {
+        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) ) {
                 uint16_t flags;
 		int i;
                 flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
@@ -690,14 +720,7 @@ static int set_ht_link_buffer_counts_cha
                 uint32_t reg;
                 uint8_t nodeid, linkn;
                 uint8_t busn;
-                unsigned devn = 1;
-
-        #if HT_CHAIN_UNITID_BASE != 1
-                #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-                if(i==0) // to check if it is sb ht chain
-                #endif
-                        devn = HT_CHAIN_UNITID_BASE;
-        #endif
+                unsigned devn;
 
                 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
                 if((reg & 3) != 3) continue; // not enabled
@@ -706,10 +729,13 @@ static int set_ht_link_buffer_counts_cha
                 linkn = ((reg & 0xf00)>>8); // link n
                 busn = (reg & 0xff0000)>>16; //busn
 
-                reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
-                if ( (reg & 0xffff) == vendorid ) {
-                        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
-                }
+		for(devn = 0; devn < 0x20; devn++) {
+	                reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
+        	        if ( (reg & 0xffff) == vendorid ) {
+                	        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
+				break;
+                	}
+		}
         }
 
         return reset_needed;
Index: src/pc80/serial.c
===================================================================
--- src/pc80/serial.c.orig
+++ src/pc80/serial.c
@@ -24,7 +24,7 @@
 #define UART_LCS	TTYS0_LCS
 
 
-#if CONFIG_USE_INIT == 0
+#if CONFIG_USE_PRINTK_IN_CAR == 0
 
 /* Data */
 #define UART_RBR 0x00
@@ -92,6 +92,7 @@ static void uart_init(void)
 	outb(UART_LCS, TTYS0_BASE + UART_LCR);
 }
 #else
+#include "../lib/uart8250.c"
 extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
 static void uart_init(void)
 {
Index: src/pc80/usbdebug_direct_serial.c
===================================================================
--- /dev/null
+++ src/pc80/usbdebug_direct_serial.c
@@ -0,0 +1,25 @@
+#include <part/fallback_boot.h>
+#include "../lib/usbdebug_direct.c" 
+static void early_usbdebug_direct_init(void)
+{
+	struct ehci_debug_info *dbg_info = 
+		(struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); 
+	
+	usbdebug_direct_init(EHCI_BAR, EHCI_DEBUG_OFFSET, dbg_info); 
+}
+void usbdebug_direct_tx_byte(unsigned char data)
+{
+	struct ehci_debug_info *dbg_info;
+	dbg_info = (struct ehci_debug_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - sizeof (struct ehci_debug_info)); // in Cache 
+	if (dbg_info->ehci_debug) { 
+		dbgp_bulk_write_x(dbg_info, &data, 1);
+	}
+}
+void usbdebug_direct_ram_tx_byte(unsigned char data)
+{
+	struct ehci_debug_info *dbg_info;
+	dbg_info = (struct ehci_debug_info *)((CONFIG_LB_MEM_TOPK<<10) - sizeof (struct ehci_debug_info)); //in RAM 
+	if (dbg_info->ehci_debug) {
+		dbgp_bulk_write_x(dbg_info, &data, 1);
+	}
+}
Index: src/arch/i386/smp/mpspec.c
===================================================================
--- src/arch/i386/smp/mpspec.c.orig
+++ src/arch/i386/smp/mpspec.c
@@ -26,8 +26,7 @@ void *smp_write_floating_table(unsigned 
 	void *v;
 	
 	/* 16 byte align the table address */
-	addr += 15;
-	addr &= ~15;
+	addr = (addr + 0xf) & (~0xf);
 	v = (void *)addr;
 
 	mf = v;
@@ -52,8 +51,8 @@ void *smp_write_floating_table_physaddr(
 {
         struct intel_mp_floating *mf;
         void *v;
-
-        v = (void *)addr;
+	
+	v = (void *)addr;
         mf = v;
         mf->mpf_signature[0] = '_';
         mf->mpf_signature[1] = 'M';
Index: src/arch/i386/boot/boot.c
===================================================================
--- src/arch/i386/boot/boot.c.orig
+++ src/arch/i386/boot/boot.c
@@ -67,6 +67,19 @@ int elf_check_arch(Elf_ehdr *ehdr)
 	
 }
 
+static void dump_memx(unsigned start, unsigned end)
+{
+        unsigned i;
+        print_debug("dump_mem:");
+        for(i=start;i<end;i++) {
+                if((i & 0xf)==0) {
+                        printk_debug("\n%08x:", i);
+                }
+                printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+        }
+        print_debug("\n");
+}
+
 void jmp_to_elf_entry(void *entry, unsigned long buffer)
 {
 	extern unsigned char _ram_seg, _eram_seg;
@@ -92,6 +105,8 @@ void jmp_to_elf_entry(void *entry, unsig
 	printk_spew("buffer   = 0x%08lx\n", buffer);
 	printk_spew("     elf_boot_notes = 0x%08lx\n", (unsigned long)&elf_boot_notes);
 	printk_spew("adjusted_boot_notes = 0x%08lx\n", adjusted_boot_notes);
+
+//	dump_memx(0xf0000, 0xf0100);
 	
 	/* Jump to kernel */
 	__asm__ __volatile__(
@@ -172,11 +187,12 @@ void jmp_to_elf_entry(void *entry, unsig
 		"	popl	%%ebx\n\t"
 		"	popl	%%edi\n\t"
 		"	popl	%%esi\n\t"
-
 		:: 
 		"g" (lb_start), "g" (buffer), "g" (lb_size),
 		"g" (entry), "g"(adjusted_boot_notes)
 		);
+
+
 }
 
 
Index: src/arch/i386/boot/linuxbios_table.c
===================================================================
--- src/arch/i386/boot/linuxbios_table.c.orig
+++ src/arch/i386/boot/linuxbios_table.c
@@ -365,6 +365,16 @@ unsigned long write_linuxbios_table( 
 		low_table_end = (unsigned long)head;
 	}
 
+	printk_debug("Adjust low_table_end from 0x%08x to ", low_table_end);
+	low_table_end += 0xfff; // 4K align
+	low_table_end &= ~0xfff;
+	printk_debug("0x%08x \n", low_table_end);
+	/* kernel assume this position is reserved */
+	printk_debug("Adjust rom_table_end from 0x%08x to ", rom_table_end);
+	rom_table_end += 0xffff; // 64K align
+	rom_table_end &= ~0xffff;
+	printk_debug("0x%08x \n", rom_table_end);
+
 	if (HAVE_OPTION_TABLE == 1) {
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
Index: src/arch/i386/boot/tables.c
===================================================================
--- src/arch/i386/boot/tables.c.orig
+++ src/arch/i386/boot/tables.c
@@ -10,38 +10,12 @@
 #include <arch/acpi.h>
 #include "linuxbios_table.h"
 
-// Global Descriptor Table, defined in c_start.S
-extern uint8_t gdt;
-extern uint8_t gdt_end;
-
-/* i386 lgdt argument */
-struct gdtarg {
-	unsigned short limit;
-	unsigned int base;
-} __attribute__((packed));
-
-// Copy GDT to new location and reload it
-// 2003-07 by SONE Takeshi
-// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
-void move_gdt(unsigned long newgdt)
-{
-	uint16_t num_gdt_bytes = &gdt_end - &gdt;
-	struct gdtarg gdtarg;
-
-	printk_debug("Moving GDT to %#lx...", newgdt);
-	memcpy((void*)newgdt, &gdt, num_gdt_bytes);
-	gdtarg.base = newgdt;
-	gdtarg.limit = num_gdt_bytes - 1;
-	__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
-	printk_debug("ok\n");
-}
-
 struct lb_memory *write_tables(void)
 {
 	unsigned long low_table_start, low_table_end, new_low_table_end;
 	unsigned long rom_table_start, rom_table_end;
 
-	rom_table_start = 0xf0000;
+	rom_table_start = 0xf0000; 
 	rom_table_end =   0xf0000;
 	/* Start low addr at 16 bytes instead of 0 because of a buglet
 	 * in the generic linux unzip code, as it tests for the a20 line.
@@ -59,55 +33,48 @@ struct lb_memory *write_tables(void)
 	/* write them in the rom area because DSDT can be large (8K on epia-m) which
 	 * pushes linuxbios table out of first 4K if set up in low table area 
          */
-
 	rom_table_end = write_acpi_tables(rom_table_end);
 	rom_table_end = (rom_table_end+1023) & ~1023;
 
-	/* copy the smp block to address 0 */
-	post_code(0x96);
+        /* copy the smp block to address 0 */
+        post_code(0x96);
 
-	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
-	new_low_table_end = write_smp_table(low_table_end);
+        /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
+        new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
 
-#if HAVE_MP_TABLE==1
+#if HAVE_MP_TABLE
         /* Don't write anything in the traditional x86 BIOS data segment,
          * for example the linux kernel smp need to use 0x467 to pass reset vector
          */
-        if(new_low_table_end>0x467){
-                unsigned mptable_size = new_low_table_end - low_table_end - SMP_FLOATING_TABLE_LEN;
-                /* We can not put mptable here, we need to copy them to somewhere else*/
-                if((rom_table_end+mptable_size)<0x100000) {
-                        /* We can copy mptable on rom_table, and leave low space for lbtable  */
-                        printk_debug("move mptable to 0x%0x\n", rom_table_end);
-                        memcpy((unsigned char *)rom_table_end, (unsigned char *)(low_table_end+SMP_FLOATING_TABLE_LEN), mptable_size);
-                        memset((unsigned char *)low_table_end, '\0', mptable_size + SMP_FLOATING_TABLE_LEN);
-                        smp_write_floating_table_physaddr(low_table_end, rom_table_end);
-                        low_table_end += SMP_FLOATING_TABLE_LEN;
-                        rom_table_end += mptable_size;
-                        rom_table_end = (rom_table_end+1023) & ~1023;
-                } else {
-                        /* We can need to put mptable low and from 0x500 */
-                        printk_debug("move mptable to 0x%0x\n", 0x500);
-                        memcpy((unsigned char *)0x500, (unsigned char *)(low_table_end+SMP_FLOATING_TABLE_LEN), mptable_size);
-                        memset((unsigned char *)low_table_end, '\0', 0x500-low_table_end);
-                        smp_write_floating_table_physaddr(low_table_end, 0x500);
-                        low_table_end = 0x500 + mptable_size;
-                }
-        }
-#endif 
-
-	/* Don't write anything in the traditional x86 BIOS data segment */
-	if (low_table_end < 0x500) {
+	if(new_low_table_end>0x467){
+		unsigned mptable_size;
+		unsigned mpc_start;
+		low_table_end += SMP_FLOATING_TABLE_LEN; /* keep the mpf in 1k low, so kernel can find it */
+		mptable_size = new_low_table_end - low_table_end;
+		/* We can not put mptable low, we need to copy them to somewhere else*/
+		if((rom_table_end+mptable_size)<0x100000) {
+			/* We can copy mptable on rom_table  */
+			mpc_start = rom_table_end;
+			rom_table_end += mptable_size;
+			rom_table_end = (rom_table_end+1023) & ~1023;
+		} else {
+			/* We can need to put mptable before rom_table */
+			mpc_start = rom_table_start - mptable_size;
+			mpc_start &= ~1023;
+			rom_table_start = mpc_start;
+		}
+		printk_debug("move mptable from 0x%0x to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size);
+		memcpy((unsigned char *)mpc_start, (unsigned char *)low_table_end, mptable_size);
+		smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start);
+		memset((unsigned char *)low_table_end, '\0', mptable_size);
+	}
+#endif
+	if(low_table_end<0x500) {
 		low_table_end = 0x500;
 	}
 
-	// Relocate the GDT to reserved memory, so it won't get clobbered
-	move_gdt(low_table_end);
-	low_table_end += &gdt_end - &gdt;
-
 	/* The linuxbios table must be in 0-4K or 960K-1M */
-	write_linuxbios_table(
-			      low_table_start, low_table_end,
+	write_linuxbios_table(low_table_start, low_table_end,
 			      rom_table_start, rom_table_end);
 
 	return get_lb_mem();
Index: src/arch/i386/boot/acpi.c
===================================================================
--- src/arch/i386/boot/acpi.c.orig
+++ src/arch/i386/boot/acpi.c
@@ -8,8 +8,8 @@
  * Nick Barker <nick.barker9@btinternet.com>, and those portions
  *  (C) Copyright 2004 Nick Barker
  *
- * Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
- * 2005.9 yhlu add SRAT table generation
+ * Copyright 2005 AMD
+ * 2005.9 yhlu add SRAT related
  */
 
 /* 
@@ -220,7 +220,7 @@ void acpi_create_slit(acpi_slit_t *slit)
         header->length = sizeof(acpi_slit_t);
         header->revision = 1;
 
-//        current = acpi_fill_slit(current);
+        current = acpi_fill_slit(current);
 
         /* recalculate length */
         header->length= current - (unsigned long)slit;
Index: src/arch/i386/include/stdint.h
===================================================================
--- src/arch/i386/include/stdint.h.orig
+++ src/arch/i386/include/stdint.h
@@ -67,5 +67,9 @@ typedef unsigned long int  uintmax_t;
 
 #undef __HAVE_LONG_LONG__
 
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
 
 #endif /* I386_STDINT_H */
Index: src/arch/i386/include/arch/acpi.h
===================================================================
--- src/arch/i386/include/arch/acpi.h.orig
+++ src/arch/i386/include/arch/acpi.h
@@ -17,9 +17,6 @@
 
 #if HAVE_ACPI_TABLES==1
 
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned int u32;
 typedef unsigned long long u64;
 
 #define RSDP_SIG              "RSD PTR "  /* RSDT Pointer signature */
@@ -83,7 +80,7 @@ typedef struct acpi_table_header        
 /* RSDT */
 typedef struct acpi_rsdt {
 	struct acpi_table_header header;
-	u32 entry[6+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX*/
+	u32 entry[6+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
 } __attribute__ ((packed)) acpi_rsdt_t;
 
 /* XSDT */
Index: src/arch/i386/include/arch/cpu.h
===================================================================
--- src/arch/i386/include/arch/cpu.h.orig
+++ src/arch/i386/include/arch/cpu.h
@@ -160,6 +160,7 @@ static void inline get_fms(struct cpuinf
                 c->x86_model += ((tfms >> 16) & 0xF) << 4;
 
 }
+
 #endif
 
 #endif /* ARCH_CPU_H */
Index: src/arch/i386/init/crt0.S.lb
===================================================================
--- src/arch/i386/init/crt0.S.lb.orig
+++ src/arch/i386/init/crt0.S.lb
@@ -37,7 +37,8 @@
 
 #include "crt0_includes.h"
 
-#if USE_DCACHE_RAM == 0
+#if USE_DCACHE_RAM == 0   /* for cache as ram, we will use copy_and_run.c instead */
+
 #ifndef CONSOLE_DEBUG_TX_STRING
 	/* uses:	 esp, ebx, ax, dx */
 # define __CRT_CONSOLE_TX_STRING(string) \
@@ -215,7 +216,7 @@ crt_console_tx_string:
 
 #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
 .section ".rom.data"
-str_copying_to_ram:  .string "Copying LinuxBIOS to RAM.\r\n"
+str_copying_to_ram:  .string "Copying LinuxBIOS to ram.\r\n"
 str_pre_main:        .string "Jumping to LinuxBIOS.\r\n"
 .previous
 
Index: src/arch/i386/lib/console_ram.c
===================================================================
--- /dev/null
+++ src/arch/i386/lib/console_ram.c
@@ -0,0 +1,54 @@
+#if CONFIG_USBDEBUG_DIRECT == 0
+
+#define print_ram_emerg(STR)   print_emerg  (STR)
+#define print_ram_alert(STR)   print_alert  (STR)
+#define print_ram_crit(STR)    print_crit   (STR)
+#define print_ram_err(STR)     print_err    (STR)
+#define print_ram_warning(STR) print_warning(STR)
+#define print_ram_notice(STR)  print_notice (STR)
+#define print_ram_info(STR)    print_info   (STR)
+#define print_ram_debug(STR)   print_debug  (STR)
+#define print_ram_spew(STR)    print_spew   (STR)
+
+#define print_ram_emerg_char(CH)   print_emerg  (CH)
+#define print_ram_alert_char(CH)   print_alert  (CH)
+#define print_ram_crit_char(CH)    print_crit   (CH)
+#define print_ram_err_char(CH)     print_err    (CH)
+#define print_ram_warning_char(CH) print_warning(CH)
+#define print_ram_notice_char(CH)  print_notice (CH)
+#define print_ram_info_char(CH)    print_info   (CH)
+#define print_ram_debug_char(CH)   print_debug  (CH)
+#define print_ram_spew_char(CH)    print_spew   (CH)
+
+#define print_ram_emerg_hex8(HEX)   print_emerg  (HEX)
+#define print_ram_alert_hex8(HEX)   print_alert  (HEX)
+#define print_ram_crit_hex8(HEX)    print_crit   (HEX)
+#define print_ram_err_hex8(HEX)     print_err    (HEX)
+#define print_ram_warning_hex8(HEX) print_warning(HEX)
+#define print_ram_notice_hex8(HEX)  print_notice (HEX)
+#define print_ram_info_hex8(HEX)    print_info   (HEX)
+#define print_ram_debug_hex8(HEX)   print_debug  (HEX)
+#define print_ram_spew_hex8(HEX)    print_spew   (HEX)
+
+#define print_ram_emerg_hex16(HEX)   print_emerg  (HEX)
+#define print_ram_alert_hex16(HEX)   print_alert  (HEX)
+#define print_ram_crit_hex16(HEX)    print_crit   (HEX)
+#define print_ram_err_hex16(HEX)     print_err    (HEX)
+#define print_ram_warning_hex16(HEX) print_warning(HEX)
+#define print_ram_notice_hex16(HEX)  print_notice (HEX)
+#define print_ram_info_hex16(HEX)    print_info   (HEX)
+#define print_ram_debug_hex16(HEX)   print_debug  (HEX)
+#define print_ram_spew_hex16(HEX)    print_spew   (HEX)
+
+#define print_ram_emerg_hex32(HEX)   print_emerg  (HEX)
+#define print_ram_alert_hex32(HEX)   print_alert  (HEX)
+#define print_ram_crit_hex32(HEX)    print_crit   (HEX)
+#define print_ram_err_hex32(HEX)     print_err    (HEX)
+#define print_ram_warning_hex32(HEX) print_warning(HEX)
+#define print_ram_notice_hex32(HEX)  print_notice (HEX)
+#define print_ram_info_hex32(HEX)    print_info   (HEX)
+#define print_ram_debug_hex32(HEX)   print_debug  (HEX)
+#define print_ram_spew_hex32(HEX)    print_spew   (HEX)
+
+#endif
+
Index: src/arch/i386/lib/console.c
===================================================================
--- src/arch/i386/lib/console.c.orig
+++ src/arch/i386/lib/console.c
@@ -4,226 +4,33 @@
 static void __console_tx_byte(unsigned char byte)
 {
 	uart_tx_byte(byte);
+#if CONFIG_USBDEBUG_DIRECT
+	usbdebug_direct_tx_byte(byte);
+#endif
 }
-
-static void __console_tx_nibble(unsigned nibble)
+#if CONFIG_USBDEBUG_DIRECT
+static void __console_ram_tx_byte(unsigned char byte)
 {
-	unsigned char digit;
-	digit = nibble + '0';
-	if (digit > '9') {
-		digit += 39;
-	}
-	__console_tx_byte(digit);
+	uart_tx_byte(byte);
+	usbdebug_direct_ram_tx_byte(byte);
 }
+#endif
 
-static void __console_tx_char(int loglevel, unsigned char byte)
-{
-	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
-		uart_tx_byte(byte);
-	}
-}
+#include "console_print.c"
+#include "console_print_ram.c"
 
-static void __console_tx_hex8(int loglevel, unsigned char value)
-{
-	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
+#else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ 
 
-static void __console_tx_hex16(int loglevel, unsigned short value)
-{
-	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
-		__console_tx_nibble((value >> 12U) & 0x0fU);
-		__console_tx_nibble((value >>  8U) & 0x0fU);
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
+#include "console_printk.c"
+#include "console_printk_ram.c"
 
-static void __console_tx_hex32(int loglevel, unsigned int value)
-{
-	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
-		__console_tx_nibble((value >> 28U) & 0x0fU);
-		__console_tx_nibble((value >> 24U) & 0x0fU);
-		__console_tx_nibble((value >> 20U) & 0x0fU);
-		__console_tx_nibble((value >> 16U) & 0x0fU);
-		__console_tx_nibble((value >> 12U) & 0x0fU);
-		__console_tx_nibble((value >>  8U) & 0x0fU);
-		__console_tx_nibble((value >>  4U) & 0x0fU);
-		__console_tx_nibble(value & 0x0fU);
-	}
-}
+// do_printk
+#include "../../../console/vtxprintf.c"
+#include "printk_init.c"
 
-static void __console_tx_string(int loglevel, const char *str)
-{
-	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
-		unsigned char ch;
-		while((ch = *str++) != '\0') {
-			__console_tx_byte(ch);
-		}
-	}
-}
-
-#define NOINLINE __attribute__((noinline))
-static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
-static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
-static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
-static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
-static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
-
-static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
-static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
-static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
-static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
-static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
-
-static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
-static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
-static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
-static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
-static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
-
-static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
-static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
-static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
-static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
-static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
-
-static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
-static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
-static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
-static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
-static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
-
-static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
-static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
-static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
-static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
-static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
-
-static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
-static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
-static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
-static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
-static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
-
-static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
-static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
-static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
-static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
-static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
-
-static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
-static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
-static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
-static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
-static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
-
-#else  
-/* CONFIG_USE_INIT == 1 */
-
-extern int do_printk(int msg_level, const char *fmt, ...);
-
-#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
-#define printk_alert(fmt, arg...)   do_printk(BIOS_ALERT   ,fmt, ##arg)
-#define printk_crit(fmt, arg...)    do_printk(BIOS_CRIT    ,fmt, ##arg)
-#define printk_err(fmt, arg...)     do_printk(BIOS_ERR     ,fmt, ##arg)
-#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
-#define printk_notice(fmt, arg...)  do_printk(BIOS_NOTICE  ,fmt, ##arg)
-#define printk_info(fmt, arg...)    do_printk(BIOS_INFO    ,fmt, ##arg)
-#define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
-#define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
-
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
-#undef  printk_emerg
-#define printk_emerg(fmt, arg...)   do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
-#undef  printk_alert
-#define printk_alert(fmt, arg...)   do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
-#undef  printk_crit
-#define printk_crit(fmt, arg...)    do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
-#undef  printk_err
-#define printk_err(fmt, arg...)     do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
-#undef  printk_warning
-#define printk_warning(fmt, arg...) do {} while(0)
 #endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
-#undef  printk_notice
-#define printk_notice(fmt, arg...)  do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
-#undef  printk_info
-#define printk_info(fmt, arg...)    do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
-#undef  printk_debug
-#define printk_debug(fmt, arg...)   do {} while(0)
-#endif
-#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
-#undef  printk_spew
-#define printk_spew(fmt, arg...)    do {} while(0)
-#endif
-
-#define print_emerg(STR)   printk_emerg  ("%s", (STR))
-#define print_alert(STR)   printk_alert  ("%s", (STR))
-#define print_crit(STR)    printk_crit   ("%s", (STR))
-#define print_err(STR)     printk_err    ("%s", (STR))
-#define print_warning(STR) printk_warning("%s", (STR))
-#define print_notice(STR)  printk_notice ("%s", (STR))
-#define print_info(STR)    printk_info   ("%s", (STR))
-#define print_debug(STR)   printk_debug  ("%s", (STR))
-#define print_spew(STR)    printk_spew   ("%s", (STR))
-
-#define print_emerg_char(CH)   printk_emerg  ("%c", (CH))
-#define print_alert_char(CH)   printk_alert  ("%c", (CH))
-#define print_crit_char(CH)    printk_crit   ("%c", (CH))
-#define print_err_char(CH)     printk_err    ("%c", (CH))
-#define print_warning_char(CH) printk_warning("%c", (CH))
-#define print_notice_char(CH)  printk_notice ("%c", (CH))
-#define print_info_char(CH)    printk_info   ("%c", (CH))
-#define print_debug_char(CH)   printk_debug  ("%c", (CH))
-#define print_spew_char(CH)    printk_spew   ("%c", (CH))
-
-#define print_emerg_hex8(HEX)   printk_emerg  ("%02x",  (HEX))
-#define print_alert_hex8(HEX)   printk_alert  ("%02x",  (HEX))
-#define print_crit_hex8(HEX)    printk_crit   ("%02x",  (HEX))
-#define print_err_hex8(HEX)     printk_err    ("%02x",  (HEX))
-#define print_warning_hex8(HEX) printk_warning("%02x",  (HEX))
-#define print_notice_hex8(HEX)  printk_notice ("%02x",  (HEX))
-#define print_info_hex8(HEX)    printk_info   ("%02x",  (HEX))
-#define print_debug_hex8(HEX)   printk_debug  ("%02x",  (HEX))
-#define print_spew_hex8(HEX)    printk_spew   ("%02x",  (HEX))
-
-#define print_emerg_hex16(HEX)   printk_emerg  ("%04x", (HEX))
-#define print_alert_hex16(HEX)   printk_alert  ("%04x", (HEX))
-#define print_crit_hex16(HEX)    printk_crit   ("%04x", (HEX))
-#define print_err_hex16(HEX)     printk_err    ("%04x", (HEX))
-#define print_warning_hex16(HEX) printk_warning("%04x", (HEX))
-#define print_notice_hex16(HEX)  printk_notice ("%04x", (HEX))
-#define print_info_hex16(HEX)    printk_info   ("%04x", (HEX))
-#define print_debug_hex16(HEX)   printk_debug  ("%04x", (HEX))
-#define print_spew_hex16(HEX)    printk_spew   ("%04x", (HEX))
-
-#define print_emerg_hex32(HEX)   printk_emerg  ("%08x", (HEX))
-#define print_alert_hex32(HEX)   printk_alert  ("%08x", (HEX))
-#define print_crit_hex32(HEX)    printk_crit   ("%08x", (HEX))
-#define print_err_hex32(HEX)     printk_err    ("%08x", (HEX))
-#define print_warning_hex32(HEX) printk_warning("%08x", (HEX))
-#define print_notice_hex32(HEX)  printk_notice ("%08x", (HEX))
-#define print_info_hex32(HEX)    printk_info   ("%08x", (HEX))
-#define print_debug_hex32(HEX)   printk_debug  ("%08x", (HEX))
-#define print_spew_hex32(HEX)    printk_spew   ("%08x", (HEX))
-
 
-#endif /* CONFIG_USE_INIT */
+#include "console_ram.c" 
 
 #ifndef LINUXBIOS_EXTRA_VERSION
 #define LINUXBIOS_EXTRA_VERSION ""
Index: src/arch/i386/lib/console_print_ram.c
===================================================================
--- /dev/null
+++ src/arch/i386/lib/console_print_ram.c
@@ -0,0 +1,118 @@
+#if CONFIG_USBDEBUG_DIRECT
+
+static void __console_ram_tx_nibble(unsigned nibble)
+{
+	unsigned char digit;
+	digit = nibble + '0';
+	if (digit > '9') {
+		digit += 39;
+	}
+	__console_ram_tx_byte(digit);
+}
+
+static void __console_ram_tx_char(int loglevel, unsigned char byte)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_ram_tx_byte(byte);
+	}
+}
+
+static void __console_ram_tx_hex8(int loglevel, unsigned char value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_ram_tx_nibble((value >>  4U) & 0x0fU);
+		__console_ram_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_ram_tx_hex16(int loglevel, unsigned short value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_ram_tx_nibble((value >> 12U) & 0x0fU);
+		__console_ram_tx_nibble((value >>  8U) & 0x0fU);
+		__console_ram_tx_nibble((value >>  4U) & 0x0fU);
+		__console_ram_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_ram_tx_hex32(int loglevel, unsigned int value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_ram_tx_nibble((value >> 28U) & 0x0fU);
+		__console_ram_tx_nibble((value >> 24U) & 0x0fU);
+		__console_ram_tx_nibble((value >> 20U) & 0x0fU);
+		__console_ram_tx_nibble((value >> 16U) & 0x0fU);
+		__console_ram_tx_nibble((value >> 12U) & 0x0fU);
+		__console_ram_tx_nibble((value >>  8U) & 0x0fU);
+		__console_ram_tx_nibble((value >>  4U) & 0x0fU);
+		__console_ram_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_ram_tx_string(int loglevel, const char *str)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		unsigned char ch;
+		while((ch = *str++) != '\0') {
+			__console_ram_tx_byte(ch);
+		}
+	}
+}
+
+#define NOINLINE __attribute__((noinline))
+static void print_ram_emerg_char(unsigned char byte) { __console_ram_tx_char(BIOS_EMERG, byte); }
+static void print_ram_emerg_hex8(unsigned char value){ __console_ram_tx_hex8(BIOS_EMERG, value); }
+static void print_ram_emerg_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_EMERG, value); }
+static void print_ram_emerg_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_EMERG, value); }
+static void print_ram_emerg(const char *str) { __console_ram_tx_string(BIOS_EMERG, str); }
+
+static void print_ram_alert_char(unsigned char byte) { __console_ram_tx_char(BIOS_ALERT, byte); }
+static void print_ram_alert_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_ALERT, value); }
+static void print_ram_alert_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_ALERT, value); }
+static void print_ram_alert_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_ALERT, value); }
+static void print_ram_alert(const char *str) { __console_ram_tx_string(BIOS_ALERT, str); }
+
+static void print_ram_crit_char(unsigned char byte) { __console_ram_tx_char(BIOS_CRIT, byte); }
+static void print_ram_crit_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_CRIT, value); }
+static void print_ram_crit_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_CRIT, value); }
+static void print_ram_crit_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_CRIT, value); }
+static void print_ram_crit(const char *str) { __console_ram_tx_string(BIOS_CRIT, str); }
+
+static void print_ram_err_char(unsigned char byte) { __console_ram_tx_char(BIOS_ERR, byte); }
+static void print_ram_err_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_ERR, value); }
+static void print_ram_err_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_ERR, value); }
+static void print_ram_err_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_ERR, value); }
+static void print_ram_err(const char *str) { __console_ram_tx_string(BIOS_ERR, str); }
+
+static void print_ram_warning_char(unsigned char byte) { __console_ram_tx_char(BIOS_WARNING, byte); }
+static void print_ram_warning_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_WARNING, value); }
+static void print_ram_warning_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_WARNING, value); }
+static void print_ram_warning_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_WARNING, value); }
+static void print_ram_warning(const char *str) { __console_ram_tx_string(BIOS_WARNING, str); }
+
+static void print_ram_notice_char(unsigned char byte) { __console_ram_tx_char(BIOS_NOTICE, byte); }
+static void print_ram_notice_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_NOTICE, value); }
+static void print_ram_notice_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_NOTICE, value); }
+static void print_ram_notice_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_NOTICE, value); }
+static void print_ram_notice(const char *str) { __console_ram_tx_string(BIOS_NOTICE, str); }
+
+static void print_ram_info_char(unsigned char byte) { __console_ram_tx_char(BIOS_INFO, byte); }
+static void print_ram_info_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_INFO, value); }
+static void print_ram_info_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_INFO, value); }
+static void print_ram_info_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_INFO, value); }
+static void print_ram_info(const char *str) { __console_ram_tx_string(BIOS_INFO, str); }
+
+static void print_ram_debug_char(unsigned char byte) { __console_ram_tx_char(BIOS_DEBUG, byte); }
+static void print_ram_debug_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_DEBUG, value); }
+static void print_ram_debug_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_DEBUG, value); }
+static void print_ram_debug_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_DEBUG, value); }
+static void print_ram_debug(const char *str) { __console_ram_tx_string(BIOS_DEBUG, str); }
+
+static void print_ram_spew_char(unsigned char byte) { __console_ram_tx_char(BIOS_SPEW, byte); }
+static void print_ram_spew_hex8(unsigned char value) { __console_ram_tx_hex8(BIOS_SPEW, value); }
+static void print_ram_spew_hex16(unsigned short value){ __console_ram_tx_hex16(BIOS_SPEW, value); }
+static void print_ram_spew_hex32(unsigned int value) { __console_ram_tx_hex32(BIOS_SPEW, value); }
+static void print_ram_spew(const char *str) { __console_ram_tx_string(BIOS_SPEW, str); }
+
+#endif
+
Index: src/arch/i386/lib/console_print.c
===================================================================
--- /dev/null
+++ src/arch/i386/lib/console_print.c
@@ -0,0 +1,115 @@
+
+static void __console_tx_nibble(unsigned nibble)
+{
+	unsigned char digit;
+	digit = nibble + '0';
+	if (digit > '9') {
+		digit += 39;
+	}
+	__console_tx_byte(digit);
+}
+
+static void __console_tx_char(int loglevel, unsigned char byte)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_tx_byte(byte);
+	}
+}
+
+static void __console_tx_hex8(int loglevel, unsigned char value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_hex16(int loglevel, unsigned short value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_tx_nibble((value >> 12U) & 0x0fU);
+		__console_tx_nibble((value >>  8U) & 0x0fU);
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_hex32(int loglevel, unsigned int value)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		__console_tx_nibble((value >> 28U) & 0x0fU);
+		__console_tx_nibble((value >> 24U) & 0x0fU);
+		__console_tx_nibble((value >> 20U) & 0x0fU);
+		__console_tx_nibble((value >> 16U) & 0x0fU);
+		__console_tx_nibble((value >> 12U) & 0x0fU);
+		__console_tx_nibble((value >>  8U) & 0x0fU);
+		__console_tx_nibble((value >>  4U) & 0x0fU);
+		__console_tx_nibble(value & 0x0fU);
+	}
+}
+
+static void __console_tx_string(int loglevel, const char *str)
+{
+	if (ASM_CONSOLE_LOGLEVEL > loglevel) {
+		unsigned char ch;
+		while((ch = *str++) != '\0') {
+			__console_tx_byte(ch);
+		}
+	}
+}
+
+#define NOINLINE __attribute__((noinline))
+static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
+static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
+static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
+static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
+static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
+
+static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
+static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
+static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
+static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
+static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
+
+static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
+static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
+static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
+static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
+static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
+
+static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
+static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
+static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
+static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
+static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
+
+static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
+static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
+static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
+static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
+static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
+
+static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
+static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
+static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
+static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
+static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
+
+static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
+static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
+static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
+static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
+static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
+
+static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
+static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
+static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
+static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
+static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
+
+static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
+static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
+static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
+static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
+static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
+
Index: src/arch/i386/lib/c_start.S
===================================================================
--- src/arch/i386/lib/c_start.S.orig
+++ src/arch/i386/lib/c_start.S
@@ -263,9 +263,9 @@ gdt:
 	.word	0x0000, 0x0000		/* dummy */
 	.byte	0x00, 0x00, 0x00, 0x00
 
-	/* selgdt 0x10, flat code segment */
+	/* selgdt 0x10, flat code segment */ 
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00	
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */	
 
 	/* selgdt 0x18, flat data segment */
 	.word	0xffff, 0x0000		
Index: src/arch/i386/lib/Config.lb
===================================================================
--- src/arch/i386/lib/Config.lb.orig
+++ src/arch/i386/lib/Config.lb
@@ -1,6 +1,3 @@
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
 object c_start.S
 object cpu.c
 object pci_ops_conf1.c
@@ -9,9 +6,3 @@ object pci_ops_mmconf.c
 object pci_ops_auto.c
 object exception.c
 
-if CONFIG_USE_INIT
-	if CONFIG_USE_PRINTK_IN_CAR
-		initobject printk_init.o
-	end
-end
-
Index: src/arch/i386/lib/cpu.c
===================================================================
--- src/arch/i386/lib/cpu.c.orig
+++ src/arch/i386/lib/cpu.c
@@ -207,7 +207,6 @@ static void set_cpu_ops(struct device *c
 			}
 		}
 	}
-	die("Unknown cpu");
 	return;
  found:
 	cpu->ops = driver->ops;
@@ -223,7 +222,7 @@ void cpu_initialize(void)
 	struct device *cpu;
 	struct cpu_info *info;
 	struct cpuinfo_x86 c;
-
+	
 	info = cpu_info();
 
 	printk_notice("Initializing CPU #%d\n", info->index);
@@ -233,41 +232,37 @@ void cpu_initialize(void)
 		die("CPU: missing cpu device structure");
 	}
 
-	// Check that we haven't been passed bad information as the result of a race 
-	// (i.e. BSP timed out while waiting for us to load secondary_stack)
-
-#if CONFIG_SMP  || CONFIG_IOPIC 
-	if (cpu->path.u.apic.apic_id != lapicid()) {
-		printk_err("CPU #%d Initialization FAILED: APIC ID mismatch (%u != %u)\n",
-				   info->index, cpu->path.u.apic.apic_id, lapicid());
-		// return without setting initialized flag
-	} else {
-#endif
-		/* Find what type of cpu we are dealing with */
-		identify_cpu(cpu);
-		printk_debug("CPU: vendor %s device %x\n",
-			cpu_vendor_name(cpu->vendor), cpu->device);
-
-	        get_fms(&c, cpu->device);
-
-	        printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
-
-			
-		/* Lookup the cpu's operations */
+	/* Find what type of cpu we are dealing with */
+	identify_cpu(cpu);
+	printk_debug("CPU: vendor %s device %x\n",
+		cpu_vendor_name(cpu->vendor), cpu->device);
+
+	get_fms(&c, cpu->device);
+
+	printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
+	
+	/* Lookup the cpu's operations */
+	set_cpu_ops(cpu);
+
+	if(!cpu->ops) { 
+		/* mask out the stepping and try again */
+		cpu->device -= c.x86_mask;
 		set_cpu_ops(cpu);
+		cpu->device += c.x86_mask;
+		if(!cpu->ops) die("Unknown cpu");
+		printk_debug("Using stepping 0 ops instead\n");
+	}
+	
 
-		/* Initialize the cpu */
-		if (cpu->ops && cpu->ops->init) {
-			cpu->enabled = 1;
-			cpu->initialized = 1;
-			cpu->ops->init(cpu);
-		}
+	/* Initialize the cpu */
+	if (cpu->ops && cpu->ops->init) {
+		cpu->enabled = 1;
+		cpu->initialized = 1;
+		cpu->ops->init(cpu);
+	}
 
-		printk_info("CPU #%d Initialized\n", info->index);
-#if CONFIG_SMP  || CONFIG_IOPIC 
+	printk_info("CPU #%d Initialized\n", info->index);
 
-	}
-#endif
 	return;
 }
 
Index: src/arch/i386/lib/console_printk_ram.c
===================================================================
--- /dev/null
+++ src/arch/i386/lib/console_printk_ram.c
@@ -0,0 +1,120 @@
+#if CONFIG_USBDEBUG_DIRECT
+
+extern int do_printk_ram(int msg_level, const char *fmt, ...);
+
+#define printk_ram_emerg(fmt, arg...)   do_printk_ram(BIOS_EMERG   ,fmt, ##arg)
+#define printk_ram_alert(fmt, arg...)   do_printk_ram(BIOS_ALERT   ,fmt, ##arg)
+#define printk_ram_crit(fmt, arg...)    do_printk_ram(BIOS_CRIT    ,fmt, ##arg)
+#define printk_ram_err(fmt, arg...)     do_printk_ram(BIOS_ERR     ,fmt, ##arg)
+#define printk_ram_warning(fmt, arg...) do_printk_ram(BIOS_WARNING ,fmt, ##arg)
+#define printk_ram_notice(fmt, arg...)  do_printk_ram(BIOS_NOTICE  ,fmt, ##arg)
+#define printk_ram_info(fmt, arg...)    do_printk_ram(BIOS_INFO    ,fmt, ##arg)
+#define printk_ram_debug(fmt, arg...)   do_printk_ram(BIOS_DEBUG   ,fmt, ##arg)
+#define printk_ram_spew(fmt, arg...)    do_printk_ram(BIOS_SPEW    ,fmt, ##arg)
+
+#else
+
+#define printk_ram_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk_ram_alert(fmt, arg...)   do_printk(BIOS_ALERT   ,fmt, ##arg)
+#define printk_ram_crit(fmt, arg...)    do_printk(BIOS_CRIT    ,fmt, ##arg)
+#define printk_ram_err(fmt, arg...)     do_printk(BIOS_ERR     ,fmt, ##arg)
+#define printk_ram_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
+#define printk_ram_notice(fmt, arg...)  do_printk(BIOS_NOTICE  ,fmt, ##arg)
+#define printk_ram_info(fmt, arg...)    do_printk(BIOS_INFO    ,fmt, ##arg)
+#define printk_ram_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
+#define printk_ram_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
+
+#endif
+
+
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
+#undef  printk_ram_emerg
+#define printk_ram_emerg(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
+#undef  printk_ram_alert
+#define printk_ram_alert(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
+#undef  printk_ram_crit
+#define printk_ram_crit(fmt, arg...)    do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
+#undef  printk_ram_err
+#define printk_ram_err(fmt, arg...)     do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
+#undef  printk_ram_warning
+#define printk_ram_warning(fmt, arg...) do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
+#undef  printk_ram_notice
+#define printk_ram_notice(fmt, arg...)  do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
+#undef  printk_ram_info
+#define printk_ram_info(fmt, arg...)    do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
+#undef  printk_ram_debug
+#define printk_ram_debug(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
+#undef  printk_ram_spew
+#define printk_ram_spew(fmt, arg...)    do {} while(0)
+#endif
+
+#if CONFIG_USBDEBUG_DIRECT
+
+#define print_ram_emerg(STR)   printk_ram_emerg  ("%s", (STR))
+#define print_ram_alert(STR)   printk_ram_alert  ("%s", (STR))
+#define print_ram_crit(STR)    printk_ram_crit   ("%s", (STR))
+#define print_ram_err(STR)     printk_ram_err    ("%s", (STR))
+#define print_ram_warning(STR) printk_ram_warning("%s", (STR))
+#define print_ram_notice(STR)  printk_ram_notice ("%s", (STR))
+#define print_ram_info(STR)    printk_ram_info   ("%s", (STR))
+#define print_ram_debug(STR)   printk_ram_debug  ("%s", (STR))
+#define print_ram_spew(STR)    printk_ram_spew   ("%s", (STR))
+
+#define print_ram_emerg_char(CH)   printk_ram_emerg  ("%c", (CH))
+#define print_ram_alert_char(CH)   printk_ram_alert  ("%c", (CH))
+#define print_ram_crit_char(CH)    printk_ram_crit   ("%c", (CH))
+#define print_ram_err_char(CH)     printk_ram_err    ("%c", (CH))
+#define print_ram_warning_char(CH) printk_ram_warning("%c", (CH))
+#define print_ram_notice_char(CH)  printk_ram_notice ("%c", (CH))
+#define print_ram_info_char(CH)    printk_ram_info   ("%c", (CH))
+#define print_ram_debug_char(CH)   printk_ram_debug  ("%c", (CH))
+#define print_ram_spew_char(CH)    printk_ram_spew   ("%c", (CH))
+
+#define print_ram_emerg_hex8(HEX)   printk_ram_emerg  ("%02x",  (HEX))
+#define print_ram_alert_hex8(HEX)   printk_ram_alert  ("%02x",  (HEX))
+#define print_ram_crit_hex8(HEX)    printk_ram_crit   ("%02x",  (HEX))
+#define print_ram_err_hex8(HEX)     printk_ram_err    ("%02x",  (HEX))
+#define print_ram_warning_hex8(HEX) printk_ram_warning("%02x",  (HEX))
+#define print_ram_notice_hex8(HEX)  printk_ram_notice ("%02x",  (HEX))
+#define print_ram_info_hex8(HEX)    printk_ram_info   ("%02x",  (HEX))
+#define print_ram_debug_hex8(HEX)   printk_ram_debug  ("%02x",  (HEX))
+#define print_ram_spew_hex8(HEX)    printk_ram_spew   ("%02x",  (HEX))
+
+#define print_ram_emerg_hex16(HEX)   printk_ram_emerg  ("%04x", (HEX))
+#define print_ram_alert_hex16(HEX)   printk_ram_alert  ("%04x", (HEX))
+#define print_ram_crit_hex16(HEX)    printk_ram_crit   ("%04x", (HEX))
+#define print_ram_err_hex16(HEX)     printk_ram_err    ("%04x", (HEX))
+#define print_ram_warning_hex16(HEX) printk_ram_warning("%04x", (HEX))
+#define print_ram_notice_hex16(HEX)  printk_ram_notice ("%04x", (HEX))
+#define print_ram_info_hex16(HEX)    printk_ram_info   ("%04x", (HEX))
+#define print_ram_debug_hex16(HEX)   printk_ram_debug  ("%04x", (HEX))
+#define print_ram_spew_hex16(HEX)    printk_ram_spew   ("%04x", (HEX))
+
+#define print_ram_emerg_hex32(HEX)   printk_ram_emerg  ("%08x", (HEX))
+#define print_ram_alert_hex32(HEX)   printk_ram_alert  ("%08x", (HEX))
+#define print_ram_crit_hex32(HEX)    printk_ram_crit   ("%08x", (HEX))
+#define print_ram_err_hex32(HEX)     printk_ram_err    ("%08x", (HEX))
+#define print_ram_warning_hex32(HEX) printk_ram_warning("%08x", (HEX))
+#define print_ram_notice_hex32(HEX)  printk_ram_notice ("%08x", (HEX))
+#define print_ram_info_hex32(HEX)    printk_ram_info   ("%08x", (HEX))
+#define print_ram_debug_hex32(HEX)   printk_ram_debug  ("%08x", (HEX))
+#define print_ram_spew_hex32(HEX)    printk_ram_spew   ("%08x", (HEX))
+
+#endif
+
Index: src/arch/i386/lib/console_printk.c
===================================================================
--- /dev/null
+++ src/arch/i386/lib/console_printk.c
@@ -0,0 +1,101 @@
+
+extern int do_printk(int msg_level, const char *fmt, ...);
+
+#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
+#define printk_alert(fmt, arg...)   do_printk(BIOS_ALERT   ,fmt, ##arg)
+#define printk_crit(fmt, arg...)    do_printk(BIOS_CRIT    ,fmt, ##arg)
+#define printk_err(fmt, arg...)     do_printk(BIOS_ERR     ,fmt, ##arg)
+#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
+#define printk_notice(fmt, arg...)  do_printk(BIOS_NOTICE  ,fmt, ##arg)
+#define printk_info(fmt, arg...)    do_printk(BIOS_INFO    ,fmt, ##arg)
+#define printk_debug(fmt, arg...)   do_printk(BIOS_DEBUG   ,fmt, ##arg)
+#define printk_spew(fmt, arg...)    do_printk(BIOS_SPEW    ,fmt, ##arg)
+
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
+#undef  printk_emerg
+#define printk_emerg(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
+#undef  printk_alert
+#define printk_alert(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
+#undef  printk_crit
+#define printk_crit(fmt, arg...)    do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
+#undef  printk_err
+#define printk_err(fmt, arg...)     do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
+#undef  printk_warning
+#define printk_warning(fmt, arg...) do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
+#undef  printk_notice
+#define printk_notice(fmt, arg...)  do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
+#undef  printk_info
+#define printk_info(fmt, arg...)    do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
+#undef  printk_debug
+#define printk_debug(fmt, arg...)   do {} while(0)
+#endif
+#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
+#undef  printk_spew
+#define printk_spew(fmt, arg...)    do {} while(0)
+#endif
+
+#define print_emerg(STR)   printk_emerg  ("%s", (STR))
+#define print_alert(STR)   printk_alert  ("%s", (STR))
+#define print_crit(STR)    printk_crit   ("%s", (STR))
+#define print_err(STR)     printk_err    ("%s", (STR))
+#define print_warning(STR) printk_warning("%s", (STR))
+#define print_notice(STR)  printk_notice ("%s", (STR))
+#define print_info(STR)    printk_info   ("%s", (STR))
+#define print_debug(STR)   printk_debug  ("%s", (STR))
+#define print_spew(STR)    printk_spew   ("%s", (STR))
+
+#define print_emerg_char(CH)   printk_emerg  ("%c", (CH))
+#define print_alert_char(CH)   printk_alert  ("%c", (CH))
+#define print_crit_char(CH)    printk_crit   ("%c", (CH))
+#define print_err_char(CH)     printk_err    ("%c", (CH))
+#define print_warning_char(CH) printk_warning("%c", (CH))
+#define print_notice_char(CH)  printk_notice ("%c", (CH))
+#define print_info_char(CH)    printk_info   ("%c", (CH))
+#define print_debug_char(CH)   printk_debug  ("%c", (CH))
+#define print_spew_char(CH)    printk_spew   ("%c", (CH))
+
+#define print_emerg_hex8(HEX)   printk_emerg  ("%02x",  (HEX))
+#define print_alert_hex8(HEX)   printk_alert  ("%02x",  (HEX))
+#define print_crit_hex8(HEX)    printk_crit   ("%02x",  (HEX))
+#define print_err_hex8(HEX)     printk_err    ("%02x",  (HEX))
+#define print_warning_hex8(HEX) printk_warning("%02x",  (HEX))
+#define print_notice_hex8(HEX)  printk_notice ("%02x",  (HEX))
+#define print_info_hex8(HEX)    printk_info   ("%02x",  (HEX))
+#define print_debug_hex8(HEX)   printk_debug  ("%02x",  (HEX))
+#define print_spew_hex8(HEX)    printk_spew   ("%02x",  (HEX))
+
+#define print_emerg_hex16(HEX)   printk_emerg  ("%04x", (HEX))
+#define print_alert_hex16(HEX)   printk_alert  ("%04x", (HEX))
+#define print_crit_hex16(HEX)    printk_crit   ("%04x", (HEX))
+#define print_err_hex16(HEX)     printk_err    ("%04x", (HEX))
+#define print_warning_hex16(HEX) printk_warning("%04x", (HEX))
+#define print_notice_hex16(HEX)  printk_notice ("%04x", (HEX))
+#define print_info_hex16(HEX)    printk_info   ("%04x", (HEX))
+#define print_debug_hex16(HEX)   printk_debug  ("%04x", (HEX))
+#define print_spew_hex16(HEX)    printk_spew   ("%04x", (HEX))
+
+#define print_emerg_hex32(HEX)   printk_emerg  ("%08x", (HEX))
+#define print_alert_hex32(HEX)   printk_alert  ("%08x", (HEX))
+#define print_crit_hex32(HEX)    printk_crit   ("%08x", (HEX))
+#define print_err_hex32(HEX)     printk_err    ("%08x", (HEX))
+#define print_warning_hex32(HEX) printk_warning("%08x", (HEX))
+#define print_notice_hex32(HEX)  printk_notice ("%08x", (HEX))
+#define print_info_hex32(HEX)    printk_info   ("%08x", (HEX))
+#define print_debug_hex32(HEX)   printk_debug  ("%08x", (HEX))
+#define print_spew_hex32(HEX)    printk_spew   ("%08x", (HEX))
+
+
Index: src/arch/i386/lib/printk_init.c
===================================================================
--- src/arch/i386/lib/printk_init.c.orig
+++ src/arch/i386/lib/printk_init.c
@@ -21,12 +21,23 @@ int console_loglevel = DEFAULT_CONSOLE_L
 
 extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
 extern void uart8250_tx_byte(unsigned, unsigned char);
+#if CONFIG_USBDEBUG_DIRECT
+extern void usbdebug_direct_tx_byte(unsigned char);
+extern void usbdebug_direct_ram_tx_byte(unsigned char);
+#endif
 
 void console_tx_byte(unsigned char byte)
 {
-	if (byte == '\n')
+	if (byte == '\n') {
 		uart8250_tx_byte(TTYS0_BASE, '\r');
+#if CONFIG_USBDEBUG_DIRECT
+		usbdebug_direct_tx_byte('\r');
+#endif
+	}
 	uart8250_tx_byte(TTYS0_BASE, byte);
+#if CONFIG_USBDEBUG_DIRECT
+	usbdebug_direct_tx_byte(byte);
+#endif
 }
 
 int do_printk(int msg_level, const char *fmt, ...)
@@ -44,3 +55,31 @@ int do_printk(int msg_level, const char 
 
 	return i;
 }
+#if CONFIG_USBDEBUG_DIRECT
+void console_ram_tx_byte(unsigned char byte)
+{
+	if (byte == '\n') {
+		uart8250_tx_byte(TTYS0_BASE, '\r');
+		usbdebug_direct_ram_tx_byte('\r');
+	}
+	uart8250_tx_byte(TTYS0_BASE, byte);
+	usbdebug_direct_ram_tx_byte(byte);
+}
+
+int do_printk_ram(int msg_level, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	if (msg_level >= console_loglevel) {
+		return 0;
+	}
+
+	va_start(args, fmt);
+	i = vtxprintf(console_ram_tx_byte, fmt, args);
+	va_end(args);
+
+	return i;
+}
+#endif
+
Index: src/drivers/generic/debug/debug_dev.c
===================================================================
--- src/drivers/generic/debug/debug_dev.c.orig
+++ src/drivers/generic/debug/debug_dev.c
@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
+#include <arch/io.h>
 #include "chip.h"
 
 static void print_pci_regs(struct device *dev)
@@ -21,17 +22,53 @@ static void print_pci_regs(struct device
       printk_debug("\n");
 }
 
-static void print_mem(void)
+static void print_mem(unsigned start, unsigned size)
 {
         unsigned int i;
-	unsigned int start = 0xfffff000;
-	for(i=start;i<0xffffffff;i++) {
-             if((i & 0xf)==0) printk_debug("\n %08x:",i);
+	unsigned int end = start + size;
+	for(i=start; i<end; i++) {
+             if((i & 0xf)==0) printk_debug("\n%08x:",i);
              printk_debug(" %02x",(unsigned char)*((unsigned char *)i));
-             }
-	printk_debug(" %02x\n",(unsigned char)*((unsigned char *)i));
+	}
+	printk_debug("\n");
+
+}
+
+static void print_io(unsigned port)
+{
+
+        int i;
+        printk_debug("%04x:\n", port);
+        for(i=0;i<256;i++) {
+                uint8_t val;
+                if ((i & 0x0f) == 0) {
+                        printk_debug("%02x:", i);
+                }
+                val = inb(port);
+                printk_debug(" %02x",val);
+                if ((i & 0x0f) == 0x0f) {
+                        print_debug("\n");
+                }
+                port++;
+        }
+}
+
+static void print_io_mcp55(void)
+{
+	device_t dev;
+	struct resource *res;
+	int i;
+	dev= dev_find_slot(0, PCI_DEVFN(1, 1));
+	if(dev) {
+		for(i=0x68; i>0x60; i-=4) {
+			res = find_resource(dev, i);
+			if(res) {
+				print_io(res->base);
+			}
+		}
+	}
+}
 
- }
 static void print_pci_regs_all(void)
 {
         struct device *dev;
@@ -57,6 +94,60 @@ static void print_pci_regs_all(void)
 	}
 }
 
+static void print_pci_regs_index(struct device *dev, unsigned index_reg, unsigned type, unsigned length)
+{
+        int i;
+        printk_debug("%s\n", dev_path(dev));
+
+        printk_debug(" index reg: %04x type: %02x\n", index_reg, type);
+
+        type<<=28;
+
+        for(i = 0; i < length; i++) {
+                uint32_t val;
+                if ((i & 0x0f) == 0) {
+                        printk_debug("\n%02x:",i);
+                }
+	        pci_write_config32(dev, index_reg, i|type);
+	        val = pci_read_config32(dev, index_reg+0x4);
+
+                printk_debug(" %08x", val);
+        }
+        print_debug("\n");
+}
+#if 0
+static  void print_pci_regs_index_all_k9(void)
+{
+	int nodes = 64;
+	int i;
+	
+	device_t dev[64];
+	
+	for(i=0; i<nodes; i++) {
+		dev[i] = get_node_pci(i, 1);
+	}
+	printk_debug("MMIO:\n");
+	//MMIO
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,2, 64);  
+		print_pci_regs_index(dev[i], 0x110,3, 64);  
+	}
+	//IO
+	printk_debug("MMIO:\n");
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,4, 64);  
+	}
+	//DRAM
+	printk_debug("DRAM:\n");
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,0, 64);  
+		print_pci_regs_index(dev[i], 0x110,1, 64);  
+	}
+}
+#endif
 static void print_cpuid()
 {
 	msr_t msr;
@@ -251,7 +342,13 @@ static void debug_init(device_t dev)
 		print_pci_regs_all();
 		break;
 	case 2: 
-		print_mem();
+		print_mem(0xffe00000, 0x100);
+		print_mem(0xfff00000, 0x100);
+		print_mem(0xfff80000, 0x100);
+		print_mem(0xfff90000, 0x100);
+		print_mem(0xfffa0000, 0x100);
+		print_mem(0xfffb0000, 0x100);
+		print_mem(0xfffc0000, 0x100);
 		break;
 	case 3:
 		print_cpuid();
@@ -271,6 +368,12 @@ static void debug_init(device_t dev)
 	case 8: 
 		hard_reset();
 		break;
+	case 9: 
+		print_io_mcp55();
+		break;
+	case 10: 
+	//	print_pci_regs_index_all_k9();
+		break;
 	}
 }
 
