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<div class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><span style="FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: Tahoma"> Part of my trouble is that when I enable VGA I don't get a boot log, nothing happens, via serial or vga.
<a href="http://Config.lb">Config.lb</a> for MB is below, and <a href="http://config.lb">config.lb</a> for target follows. </span></div>
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<div class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><span style="FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: Tahoma">------------------ MB <a href="http://config.lb">config.lb</a> --------------------------</span></div>
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<p>##<br>## Compute the location and size of where this firmware image<br>## (linuxBIOS plus bootloader) will live in the boot rom chip.<br>##<br>if USE_FALLBACK_IMAGE<br> default ROM_SECTION_SIZE = FALLBACK_SIZE<br> default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
<br>else<br> default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )<br> default ROM_SECTION_OFFSET = 0<br>end</p>
<p>##<br>## Compute the start location and size size of<br>## The linuxBIOS bootloader.<br>##<br>default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)<br>default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
</p>
<p>##<br>## Compute where this copy of linuxBIOS will start in the boot rom<br>##<br>default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )</p>
<p>##<br>## Compute a range of ROM that can cached to speed up linuxBIOS,<br>## execution speed.<br>##<br>## XIP_ROM_SIZE must be a power of 2.<br>## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE<br>##<br>default XIP_ROM_SIZE=65536
<br>default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )</p>
<p>##<br>## Set all of the defaults for an x86 architecture<br>##</p>
<p>arch i386 end</p>
<p>##<br>## Build the objects we have code for in this directory.<br>##</p>
<p>driver mainboard.o</p>
<p>if HAVE_PIRQ_TABLE object irq_tables.o end<br>#object reset.o</p>
<p> </p>
<p><br>##<br>## Romcc output<br>##<br>makerule ./failover.E<br> depends "$(MAINBOARD)/failover.c ./romcc" <br> action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
<br>end</p>
<p>makerule ./failover.inc<br> depends "$(MAINBOARD)/failover.c ./romcc"<br> action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"<br>end</p>
<p>makerule ./auto.E <br> depends "$(MAINBOARD)/auto.c option_table.h ./romcc" <br> action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"<br>end<br>makerule ./auto.inc
<br> depends "$(MAINBOARD)/auto.c option_table.h ./romcc"<br> action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"<br>end</p>
<p>##<br>## Build our 16 bit and 32 bit linuxBIOS entry code<br>##<br>mainboardinit cpu/x86/16bit/entry16.inc<br>mainboardinit cpu/x86/32bit/entry32.inc<br>ldscript /cpu/x86/16bit/entry16.lds<br>ldscript /cpu/x86/32bit/entry32.lds
</p>
<p>##<br>## Build our reset vector (This is where linuxBIOS is entered)<br>##<br>if USE_FALLBACK_IMAGE <br> mainboardinit cpu/x86/16bit/reset16.inc <br> ldscript /cpu/x86/16bit/reset16.lds <br>else<br> mainboardinit cpu/x86/32bit/reset32.inc
<br> ldscript /cpu/x86/32bit/reset32.lds <br>end</p>
<p>### Should this be in the northbridge code?<br>mainboardinit arch/i386/lib/cpu_reset.inc</p>
<p>##<br>## Include an id string (For safe flashing)<br>##<br>mainboardinit arch/i386/lib/id.inc<br>ldscript /arch/i386/lib/id.lds</p>
<p>###<br>### This is the early phase of linuxBIOS startup <br>### Things are delicate and we test to see if we should<br>### failover to another image.<br>###<br>if USE_FALLBACK_IMAGE<br> ldscript /arch/i386/lib/failover.lds
<br> mainboardinit ./failover.inc<br>end</p>
<p>###<br>### O.k. We aren't just an intermediary anymore!<br>###</p>
<p>##<br>## Setup RAM<br>##<br>mainboardinit cpu/x86/fpu/enable_fpu.inc<br>mainboardinit cpu/x86/mmx/enable_mmx.inc<br>mainboardinit ./auto.inc<br>mainboardinit arch/i386/llshell/llshell.inc<br>mainboardinit cpu/x86/mmx/disable_mmx.inc
</p>
<p>##<br>## Include the secondary Configuration files <br>##<br>dir /pc80<br>config chip.h</p>
<p> </p>
<p>chip northbridge/intel/i440bx</p>
<p> device pci_domain 0 on <br> device pci 0.0 on end # host bridge<br> device pci 1.0 on end # PCI bridge<br> device pci 10.0 on end # SCSI storage controller<br> device pci 11.0 on end # Ethernet controller
<br> device pci 12.0 on end # Audio controller<br> <br> device pci f.0 on # VGA controller<br> chip drivers/pci/onboard<br> device pci f.0 on end<br> register "rom_address" = "0xfff80000"
<br> end<br> end<br> <br> device pci 7.0 on # ISA bridge <br> end<br> end</p>
<p> chip cpu/intel/socket_PGA370 end</p>
<p>end</p>
<p> --------------------------------------------------</p>
<p>----------------- <a href="http://config.lb">config.lb</a> target ---------------</p></span></div>
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<p># Config file for asus wkst55 board<br># This will make a target directory of ./wkst55</p>
<p>target wkst55<br>mainboard vmware/wkst55</p>
<p>option ROM_SIZE=(512*1024)-(32*1024)</p>
<p>romimage "normal"<br> option USE_FALLBACK_IMAGE=0<br> option ROM_IMAGE_SIZE=0x10000<br> option LINUXBIOS_EXTRA_VERSION=".0Normal"<br># payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
<br># payload ../../../../tg3--ide_disk.zelf <br># payload ../../../../../lnxieepro100.ebi<br> payload /etc/hosts<br>end</p>
<p>romimage "fallback" <br> option USE_FALLBACK_IMAGE=1<br> option ROM_IMAGE_SIZE=0x10000<br> option LINUXBIOS_EXTRA_VERSION=".0Fallback"<br># payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
<br># payload ../../../../tg3--ide_disk.zelf <br># payload ../../../../../lnxieepro100.ebia<br> payload /etc/hosts<br>end</p>
<p>buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"<br></p>
<p>-----------------------------------------------------------------------</p>
<p> </p>
<p>Regards,</p>
<p>Ceri</p></span></div>
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<p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><b><span lang="EN-US" style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma; mso-ansi-language: EN-US">From:</span></b><span lang="EN-US" style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma; mso-ansi-language: EN-US">
Lu, Yinghai [mailto:<a href="mailto:yinghai.lu@amd.com">yinghai.lu@amd.com</a>] <br><b>Sent:</b> 28 February 2007 17:27<br><b>To:</b> Joe Pub; <a href="mailto:linuxbios@linuxbios.org">linuxbios@linuxbios.org</a><br><b>Subject:
</b> RE: [LinuxBIOS] LinuxBIOS and VMWare</span><span lang="EN-US" style="mso-ansi-language: EN-US"></span></p>
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<p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><span lang="EN-US" style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial; mso-ansi-language: EN-US">Boot log and your MB <a href="http://Config.lb">Config.lb</a>?</span>
</p>
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<p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><span lang="EN-US" style="FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial; mso-ansi-language: EN-US">YH</span></p>
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<p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><b><span lang="EN-US" style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma; mso-ansi-language: EN-US">From:</span></b><span lang="EN-US" style="FONT-SIZE: 10pt; FONT-FAMILY: Tahoma; mso-ansi-language: EN-US">
<a href="mailto:linuxbios-bounces@linuxbios.org">linuxbios-bounces@linuxbios.org</a> [mailto:<a href="mailto:linuxbios-bounces@linuxbios.org">linuxbios-bounces@linuxbios.org</a>] <b>On Behalf Of </b>Joe Pub<br><b>Sent:</b>
Wednesday, February 28, 2007 9:07 AM<br><b>To:</b> <a href="mailto:linuxbios@linuxbios.org">linuxbios@linuxbios.org</a><br><b>Subject:</b> [LinuxBIOS] LinuxBIOS and VMWare</span><span lang="EN-US" style="mso-ansi-language: EN-US">
</span></p>
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<p class="MsoNormal" style="MARGIN: 0cm 0cm 0pt"><span lang="EN-US" style="mso-ansi-language: EN-US"><font face="Times New Roman">Hi There,<br><br>Has anyone had any success with VMWare. I have partially implemented the PC87360 SIO chip which has give me serial and I can boot LinuxBIOS up to the elf payload stage. I'm trying to get the VMWare VGA to work at no avail. Has anyone else has success with this.
<br><br>I have added <br><br>default CONFIG_CONSOLE_VGA=1<br>default CONFIG_PCI_ROM_RUN=1<br><br>to the Optionslb file and adjusted the size of the ROM image by -32KB (sizeof VGA BIOS for VMWare) <br>and also added <br><br>
device pci f.0 on # VGA controller<br> chip drivers/pci/onboard<br> device pci f.0 on end<br> register "rom_address" = "0xfff80000"
<br> end<br> end<br><br>to the </font><a href="http://config.lb/"><font face="Times New Roman">Config.lb</font></a><font face="Times New Roman">.<br><br>When I start VMWare with this image though it does nothing but sit there with no VGA. I have even enabled serial logging back on using CONFIG_CONSOLE_SERIAL8250 but still continue to use CONFIG_PCI_ROM_RUN but nothing then even gets written to the serial port.
<br><br>When does the VGA BIOS rom get called, at what stage?<br><br>Regards,<br>Joe</font></span></p>
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