Modified register_values table to include PCI register size
Modified sdram_set_registers to accommodate register_values table changes
Modified 440BX PAM registers so that all BIOS memory is forwarded to RAM

Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com>

Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c       (revision 2687)
+++ src/northbridge/intel/i440bx/raminit.c       (working copy)
@@ -52,6 +52,10 @@
 #define RAM_COMMAND_MRS               0x3
 #define RAM_COMMAND_CBR               0x4
 
+#define PCI_REGISTER_32BIT            1
+#define PCI_REGISTER_16BIT            2
+#define PCI_REGISTER_8BIT             3
+
 /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as
  * defined in DRAMC[2:0].
  *
@@ -66,7 +70,7 @@
        1, 5, 5, 2, 3, 4
 };
 
-/* Table format: register, bitmask, value. */
+/* Table format: register, bitmask, value, PCI register size. */
 static const long register_values[] = {
        /* NBXCFG - NBX Configuration Register
         * 0x50
@@ -129,7 +133,7 @@
         * [01:00] Reserved
         */
        // TODO
-       NBXCFG, 0x00000000, 0xff00a00c,
+       NBXCFG, 0x00000000, 0xff00a00c,PCI_REGISTER_32BIT,
 
        /* DRAMC - DRAM Control Register
         * 0x57
@@ -154,7 +158,7 @@
         *       111 = Reserved
         */
        /* Choose SDRAM (not registered), and disable refresh for now. */
-       DRAMC, 0x00, 0x8,
+       DRAMC, 0x00, 0x8,PCI_REGISTER_8BIT,
 
        /*
         * PAM[6:0] - Programmable Attribute Map Registers
@@ -181,13 +185,13 @@
         * 11 = Read/Write (all access goes to DRAM)
         */
        // TODO
-       PAM0, 0x00000000, 0x00,
-       PAM1, 0x00000000, 0x00,
-       PAM2, 0x00000000, 0x00,
-       PAM3, 0x00000000, 0x00,
-       PAM4, 0x00000000, 0x00,
-       PAM5, 0x00000000, 0x00,
-       PAM6, 0x00000000, 0x00,
+       PAM0, 0x00000000, 0x30,PCI_REGISTER_8BIT,
+       PAM1, 0x00000000, 0x33,PCI_REGISTER_8BIT,
+       PAM2, 0x00000000, 0x33,PCI_REGISTER_8BIT,
+       PAM3, 0x00000000, 0x33,PCI_REGISTER_8BIT,
+       PAM4, 0x00000000, 0x33,PCI_REGISTER_8BIT,
+       PAM5, 0x00000000, 0x33,PCI_REGISTER_8BIT,
+       PAM6, 0x00000000, 0x33,PCI_REGISTER_8BIT,
 
        /* DRB[0:7] - DRAM Row Boundary Registers
         * 0x60 - 0x67
@@ -205,14 +209,14 @@
         * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
         */
        // TODO
-       DRB0, 0x00, 0x00,
-       DRB1, 0x00, 0x00,
-       DRB2, 0x00, 0x00,
-       DRB3, 0x00, 0x00,
-       DRB4, 0x00, 0x00,
-       DRB5, 0x00, 0x00,
-       DRB6, 0x00, 0x00,
-       DRB7, 0x00, 0x00,
+       DRB0, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB1, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB2, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB3, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB4, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB5, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB6, 0x00, 0x00,PCI_REGISTER_8BIT,
+       DRB7, 0x00, 0x00,PCI_REGISTER_8BIT,
 
        /* FDHC - Fixed DRAM Hole Control Register
         * 0x68
@@ -227,7 +231,7 @@
         * [5:0] Reserved
         */
        /* No memory holes. */
-       FDHC, 0x00, 0x00,
+       FDHC, 0x00, 0x00, PCI_REGISTER_8BIT,
 
        /* RPS - SDRAM Row Page Size Register
         * 0x74 - 0x75
@@ -239,7 +243,7 @@
         *        TODO
         */
        // TODO
-       RPS, 0x0000, 0x0000,
+       RPS, 0x0000, 0x0000,PCI_REGISTER_16BIT,
 
        /* SDRAMC - SDRAM Control Register
         * 0x76 - 0x77
@@ -275,7 +279,7 @@
         *         0 = 3 clocks of RAS# precharge
         *         1 = 2 clocks of RAS# precharge
         */
-       SDRAMC, 0x0000, 0x0000,
+       SDRAMC, 0x0000, 0x0000,PCI_REGISTER_16BIT,
 
        /* PGPOL - Paging Policy Register
         * 0x78 - 0x79
@@ -298,7 +302,7 @@
         *         1xxx = Infinite (pages are not closed for idle condition)
         */
        // TODO
-       PGPOL, 0x0000, 0xff00,
+       PGPOL, 0x0000, 0xff00,PCI_REGISTER_16BIT,
 
        /* PMCR - Power Management Control Register
         * 0x7a
@@ -331,7 +335,7 @@
        // TODO: Only do this later?
        // PMCR, 0x00, 0x14,
        // PMCR, 0x00, 0x10,
-       PMCR, 0x00, 0x00,
+       PMCR, 0x00, 0x00,PCI_REGISTER_8BIT,
 };
 
 /*-----------------------------------------------------------------------------
@@ -425,12 +429,24 @@
        max = sizeof(register_values) / sizeof(register_values[0]);
 
        /* Set registers as specified in the register_values array. */
-       for (i = 0; i < max; i += 3) {
-              reg = pci_read_config32(ctrl->d0, register_values[i]);
+       for (i = 0; i < max; i += 4) {
+              switch(register_values[i+3]){
+                     case PCI_REGISTER_8BIT: reg = pci_read_config8(ctrl->d0, register_values[i]); break;
+                     case PCI_REGISTER_16BIT: reg = pci_read_config16(ctrl->d0, register_values[i]);break;
+                     case PCI_REGISTER_32BIT: reg = pci_read_config32(ctrl->d0, register_values[i]);break;
+                     default: print_debug("Invalid PCI register size in table\n");
+              }
+
               reg &= register_values[i + 1];
               reg |= register_values[i + 2] & ~(register_values[i + 1]);
-              pci_write_config32(ctrl->d0, register_values[i], reg);
 
+              switch(register_values[i+3]){
+                     case PCI_REGISTER_8BIT: pci_write_config8(ctrl->d0, register_values[i],reg);break;
+                     case PCI_REGISTER_16BIT: pci_write_config16(ctrl->d0, register_values[i],reg);break;
+                     case PCI_REGISTER_32BIT: pci_write_config32(ctrl->d0, register_values[i],reg);break;
+                     default: print_debug("Invalid PCI register size in table\n");
+              }
+
               PRINT_DEBUG("    Set register 0x");
               PRINT_DEBUG_HEX32(register_values[i]);
               PRINT_DEBUG(" to 0x");
