Index: src/cpu/intel/socket_423/socket_423.c
===================================================================
--- src/cpu/intel/socket_423/socket_423.c	(revision 0)
+++ src/cpu/intel/socket_423/socket_423.c	(revision 0)
@@ -0,0 +1,33 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0f07 */
+#include "../microcode/964-m01f0712.inc"
+/* 0x0f0a */
+#include "../microcode/983-m02f0a15.inc"
+/* 0x0f12 */
+#include "../microcode/1070-m02f122f.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* It appears that only P4s were ever manufactured in Socket 423,
+ *  and there are their IDs */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f07 },
+	{ X86_VENDOR_INTEL, 0x0f0a },
+	{ X86_VENDOR_INTEL, 0x0f12 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_423_ops = {
+	CHIP_NAME("Socket 423 Pentium 4 CPU")
+};
Index: src/cpu/intel/socket_423/Config.lb
===================================================================
--- src/cpu/intel/socket_423/Config.lb	(revision 0)
+++ src/cpu/intel/socket_423/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_423.o 
Index: src/cpu/intel/socket_423/chip.h
===================================================================
--- src/cpu/intel/socket_423/chip.h	(revision 0)
+++ src/cpu/intel/socket_423/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_423_ops;
+
+struct cpu_intel_socket_423_config {
+};
Index: src/cpu/intel/socket_603/socket_603.c
===================================================================
--- src/cpu/intel/socket_603/socket_603.c	(revision 0)
+++ src/cpu/intel/socket_603/socket_603.c	(revision 0)
@@ -0,0 +1,52 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */ 
+/* 0x0f0a */
+#include "../microcode/983-m02f0a15.inc"
+/* 0x0f11 */
+#include "../microcode/1143-m02f110a.inc"
+/* 0x0f12 */
+#include "../microcode/1070-m02f122f.inc"
+/* 0x0f22 */
+#include "../microcode/1142-m02f2205.inc"
+/* 0x0f24 */
+#include "../microcode/1107-m10f2421.inc"
+/* 0x0f25 */
+#include "../microcode/1346-m10f252c.inc"
+/* 0x0f26 */
+#include "../microcode/1336-m02f2610.inc"
+/* 0x0f27 */
+#include "../microcode/1102-m08f2739.inc"
+/* 0x0f29 */
+#include "../microcode/1340-m08f292f.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* Note: It is impossible to tell what Xeons are Socket 603 vs 604 from the info
+ * on Intel's website. Also, socket 603 CPUs work in 604 systems. Hence, 
+ * combined for good reasons. */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f0a },
+	{ X86_VENDOR_INTEL, 0x0f11 },
+	{ X86_VENDOR_INTEL, 0x0f12 },
+	{ X86_VENDOR_INTEL, 0x0f22 },
+	{ X86_VENDOR_INTEL, 0x0f24 },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f26 },
+	{ X86_VENDOR_INTEL, 0x0f27 },
+	{ X86_VENDOR_INTEL, 0x0f29 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_603_ops = {
+	CHIP_NAME("Socket 603 CPU")
+};
Index: src/cpu/intel/socket_603/Config.lb
===================================================================
--- src/cpu/intel/socket_603/Config.lb	(revision 0)
+++ src/cpu/intel/socket_603/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_603.o 
Index: src/cpu/intel/socket_603/chip.h
===================================================================
--- src/cpu/intel/socket_603/chip.h	(revision 0)
+++ src/cpu/intel/socket_603/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_603_ops;
+
+struct cpu_intel_socket_603_config {
+};
Index: src/cpu/intel/socket_604/Config.lb
===================================================================
--- src/cpu/intel/socket_604/Config.lb	(revision 0)
+++ src/cpu/intel/socket_604/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_604.o 
Index: src/cpu/intel/socket_604/socket_604.c
===================================================================
--- src/cpu/intel/socket_604/socket_604.c	(revision 0)
+++ src/cpu/intel/socket_604/socket_604.c	(revision 0)
@@ -0,0 +1,61 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */ 
+/* 0x0f22 */
+#include "../microcode/1142-m02f2205.inc"
+/* 0x0f24 */
+#include "../microcode/1107-m10f2421.inc"
+/* 0x0f25 */
+#include "../microcode/1346-m10f252c.inc"
+/* 0x0f26 */
+#include "../microcode/1336-m02f2610.inc"
+/* 0x0f27 */
+#include "../microcode/1102-m08f2739.inc"
+/* 0x0f29 */
+#include "../microcode/1340-m08f292f.inc"
+/* 0x0f34 */
+#include "../microcode/1468-m1df3417.inc"
+/* 0x0f41 */
+#include "../microcode/1471-mbdf4117.inc"
+/* 0x0f43 */
+#include "../microcode/1460-m9df4305.inc"
+/* 0x0f48 */
+#include "../microcode/1735-m01f480c.inc"
+/* 0x0f49 */
+#include "../microcode/1462-mbdf4903.inc"
+/* 0x0f4a */
+#include "../microcode/1637-m5cf4a04.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* Note: It is impossible to tell what Xeons are Socket 603 vs 604 from the info
+ * on Intel's website. Also, socket 603 CPUs work in 604 systems. Hence, 
+ * combined for good reasons. */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f22 },
+	{ X86_VENDOR_INTEL, 0x0f24 },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f26 },
+	{ X86_VENDOR_INTEL, 0x0f27 },
+	{ X86_VENDOR_INTEL, 0x0f29 },
+	{ X86_VENDOR_INTEL, 0x0f34 },
+	{ X86_VENDOR_INTEL, 0x0f41 },
+	{ X86_VENDOR_INTEL, 0x0f43 },
+	{ X86_VENDOR_INTEL, 0x0f48 },
+	{ X86_VENDOR_INTEL, 0x0f49 },
+	{ X86_VENDOR_INTEL, 0x0f4a },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_604_ops = {
+	CHIP_NAME("Socket 604 CPU")
+};
Index: src/cpu/intel/socket_604/chip.h
===================================================================
--- src/cpu/intel/socket_604/chip.h	(revision 0)
+++ src/cpu/intel/socket_604/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_604_ops;
+
+struct cpu_intel_socket_604_config {
+};
Index: src/cpu/intel/socket_m_p/Config.lb
===================================================================
--- src/cpu/intel/socket_m_p/Config.lb	(revision 0)
+++ src/cpu/intel/socket_m_p/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_m_p.o 
Index: src/cpu/intel/socket_m_p/socket_m_p.c
===================================================================
--- src/cpu/intel/socket_m_p/socket_m_p.c	(revision 0)
+++ src/cpu/intel/socket_m_p/socket_m_p.c	(revision 0)
@@ -0,0 +1,50 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x06d8 */
+#include "../microcode/1854-m86d821.inc"
+/* 0x06e8 */
+#include "../microcode/1624-m206e839.inc"
+/* 0x06ec */
+#include "../microcode/1869-m806ec59.inc"
+/* 0x06f2 */
+#include "../microcode/2129-m206f257.inc"
+/* 0x06f6 */
+#include "../microcode/2149-m46f6c9.inc"
+/* 0x06fa */
+#include "../microcode/2096-m806fa92.inc"
+/* 0x06fb */
+#include "../microcode/2107-m406fbB4.inc"
+/* 0x06fd */
+#include "../microcode/2099-m16fda1.inc"
+/* 0x10676 - no microcode updates yet */
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* Note: Intel does not explicitly state which CPUs are Socket M vs Socket P on their website, but there was a large overlap of the ones I could identify. Hence, this includes all Socket M and P CPUs, along with onboard Core, Core 2, and (Core/Core2 based) Celeron M CPUs, for convenience's sake */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x06e8 },
+	{ X86_VENDOR_INTEL, 0x06ec },
+	{ X86_VENDOR_INTEL, 0x06f2 },
+	{ X86_VENDOR_INTEL, 0x06f6 },
+	{ X86_VENDOR_INTEL, 0x06fa },
+	{ X86_VENDOR_INTEL, 0x06fb },
+	{ X86_VENDOR_INTEL, 0x06fd },
+	/* I don't know if we'll be able to see all 5 digits, so both are included */
+	{ X86_VENDOR_INTEL, 0x10676 },
+	{ X86_VENDOR_INTEL, 0x0676 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_m_p_ops = {
+	CHIP_NAME("Socket M CPU")
+};
Index: src/cpu/intel/socket_m_p/chip.h
===================================================================
--- src/cpu/intel/socket_m_p/chip.h	(revision 0)
+++ src/cpu/intel/socket_m_p/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_m_p_ops;
+
+struct cpu_intel_socket_m_p_config {
+};
Index: src/cpu/intel/model_69x/Config.lb
===================================================================
--- src/cpu/intel/model_69x/Config.lb	(revision 3036)
+++ src/cpu/intel/model_69x/Config.lb	(working copy)
@@ -1,9 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/fpu
-dir /cpu/x86/mmx
-dir /cpu/x86/sse
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/intel/microcode
-driver model_69x_init.o
Index: src/cpu/intel/model_69x/model_69x_init.c
===================================================================
--- src/cpu/intel/model_69x/model_69x_init.c	(revision 3036)
+++ src/cpu/intel/model_69x/model_69x_init.c	(working copy)
@@ -1,48 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-
-static uint32_t microcode_updates[] = {
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
-
-static void model_69x_init(device_t dev)
-{
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-	x86_setup_mtrrs(36);
-	x86_mtrr_check();
-	
-	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init     = model_69x_init,
-};
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x0695 }, /* Pentium M */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
Index: src/cpu/intel/socket_mFCPGA478/Config.lb
===================================================================
--- src/cpu/intel/socket_mFCPGA478/Config.lb	(revision 3036)
+++ src/cpu/intel/socket_mFCPGA478/Config.lb	(working copy)
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mFCPGA478.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
Index: src/cpu/intel/socket_mFCPGA478/chip.h
===================================================================
--- src/cpu/intel/socket_mFCPGA478/chip.h	(revision 3036)
+++ src/cpu/intel/socket_mFCPGA478/chip.h	(working copy)
@@ -1,4 +0,0 @@
-extern struct chip_operations cpu_intel_socket_mFCPGA478_ops;
-
-struct cpu_intel_socket_mFCPGA478_config {
-};
Index: src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c
===================================================================
--- src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c	(revision 3036)
+++ src/cpu/intel/socket_mFCPGA478/socket_mFCPGA478.c	(working copy)
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-
-struct chip_operations cpu_intel_socket_mFCPGA478_ops = {
-	CHIP_NAME("Socket mFCPGA478 CPU")
-};
Index: src/cpu/intel/socket_PGA370/Config.lb
===================================================================
--- src/cpu/intel/socket_PGA370/Config.lb	(revision 3036)
+++ src/cpu/intel/socket_PGA370/Config.lb	(working copy)
@@ -1,3 +0,0 @@
-config chip.h
-object socket_PGA370.o
-dir /cpu/intel/model_6xx
Index: src/cpu/intel/socket_PGA370/chip.h
===================================================================
--- src/cpu/intel/socket_PGA370/chip.h	(revision 3036)
+++ src/cpu/intel/socket_PGA370/chip.h	(working copy)
@@ -1,4 +0,0 @@
-extern struct chip_operations cpu_intel_socket_PGA370_ops;
-
-struct cpu_intel_socket_PGA370_config {
-};
Index: src/cpu/intel/socket_PGA370/socket_PGA370.c
===================================================================
--- src/cpu/intel/socket_PGA370/socket_PGA370.c	(revision 3036)
+++ src/cpu/intel/socket_PGA370/socket_PGA370.c	(working copy)
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-
-struct chip_operations cpu_intel_socket_PGA370_ops = {
-	CHIP_NAME("Socket PGA370 CPU")
-};
Index: src/cpu/intel/socket_370/Config.lb
===================================================================
--- src/cpu/intel/socket_370/Config.lb	(revision 0)
+++ src/cpu/intel/socket_370/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_370.o 
Index: src/cpu/intel/socket_370/socket_370.c
===================================================================
--- src/cpu/intel/socket_370/socket_370.c	(revision 0)
+++ src/cpu/intel/socket_370/socket_370.c	(revision 0)
@@ -0,0 +1,61 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0665 */
+#include "../microcode/398-MU166503.inc"
+/* 0x0672 */
+#include "../microcode/540-mu267238.inc"
+/* 0x0673 */
+#include "../microcode/531-mu26732e.inc"
+/* 0x0681 */
+#include "../microcode/538-MU168111.inc"
+/* 0x0683 */
+#include "../microcode/729-MU268310.inc"
+/* 0x0686 */
+#include "../microcode/618-MU268602.inc"
+/* 0x068a */
+#include "../microcode/692-MU168a05.inc"
+/* 0x06a0 */
+#include "../microcode/566-mu26a003.inc"
+/* 0x06a1 */
+#include "../microcode/588-mu26a101.inc"
+/* 0x06a4 */
+#include "../microcode/620-MU26a401.inc"
+/* 0x06b1 */
+#include "../microcode/738-MU16b11d.inc"
+/* 0x06b4 */
+#include "../microcode/885-MU16b402.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* Slot 1 CPU IDs. Note that the same ID is sometimes used for Celeron,
+ * Pentium, and Xeon families, in various packages. This also includes
+ * Mobile Pentium II and Celeron families */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0665 },
+	{ X86_VENDOR_INTEL, 0x0672 },
+	{ X86_VENDOR_INTEL, 0x0673 },
+	{ X86_VENDOR_INTEL, 0x0681 },
+	{ X86_VENDOR_INTEL, 0x0683 },
+	{ X86_VENDOR_INTEL, 0x0686 },
+	{ X86_VENDOR_INTEL, 0x068a },
+	{ X86_VENDOR_INTEL, 0x06a0 },
+	{ X86_VENDOR_INTEL, 0x06a1 },
+	{ X86_VENDOR_INTEL, 0x06a4 },
+	{ X86_VENDOR_INTEL, 0x06b1 },
+	{ X86_VENDOR_INTEL, 0x06b4 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_370_ops = {
+	CHIP_NAME("Socket 370 Pentium III CPU")
+};
Index: src/cpu/intel/socket_370/chip.h
===================================================================
--- src/cpu/intel/socket_370/chip.h	(revision 0)
+++ src/cpu/intel/socket_370/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_370_ops;
+
+struct cpu_intel_socket_370_config {
+};
Index: src/cpu/intel/model_6dx/Config.lb
===================================================================
--- src/cpu/intel/model_6dx/Config.lb	(revision 3036)
+++ src/cpu/intel/model_6dx/Config.lb	(working copy)
@@ -1,9 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/fpu
-dir /cpu/x86/mmx
-dir /cpu/x86/sse
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/intel/microcode
-driver model_6dx_init.o
Index: src/cpu/intel/model_6dx/model_6dx_init.c
===================================================================
--- src/cpu/intel/model_6dx/model_6dx_init.c	(revision 3036)
+++ src/cpu/intel/model_6dx/model_6dx_init.c	(working copy)
@@ -1,48 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-
-static uint32_t microcode_updates[] = {
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
-
-static void model_6dx_init(device_t dev)
-{
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-	x86_setup_mtrrs(36);
-	x86_mtrr_check();
-	
-	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init     = model_6dx_init,
-};
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x06D6 }, /* Pentium M on 90nm with 2MiB of L2 cache */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
Index: src/cpu/intel/socket_771/Config.lb
===================================================================
--- src/cpu/intel/socket_771/Config.lb	(revision 0)
+++ src/cpu/intel/socket_771/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_771.o 
Index: src/cpu/intel/socket_771/socket_771.c
===================================================================
--- src/cpu/intel/socket_771/socket_771.c	(revision 0)
+++ src/cpu/intel/socket_771/socket_771.c	(revision 0)
@@ -0,0 +1,40 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+/* 0x0676/0x10676 - no microcode update for this CPU */
+/* 0x06f6 */
+#include "../microcode/2149-m46f6c9.inc"
+/* 0x06f7 */
+#include "../microcode/2151-m406f767.inc"
+/* 0x06fb */
+#include "../microcode/2107-m406fbB4.inc"
+/* 0x0f64 */
+#include "../microcode/1644-m34f6404.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* These are all Xeon CPUs */
+struct cpu_device_id cpu_table[] = {
+	/* Not sure if we'll see all 5 characters, so add both */
+	{ X86_VENDOR_INTEL, 0x0676 },
+	{ X86_VENDOR_INTEL, 0x10676 },
+	{ X86_VENDOR_INTEL, 0x06f6 },
+	{ X86_VENDOR_INTEL, 0x06f7 },
+	{ X86_VENDOR_INTEL, 0x06fb },
+	{ X86_VENDOR_INTEL, 0x0f64 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_771_ops = {
+	CHIP_NAME("Socket LGA771 CPU")
+};
Index: src/cpu/intel/socket_771/chip.h
===================================================================
--- src/cpu/intel/socket_771/chip.h	(revision 0)
+++ src/cpu/intel/socket_771/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_771_ops;
+
+struct cpu_intel_socket_771_config {
+};
Index: src/cpu/intel/socket_495/Config.lb
===================================================================
--- src/cpu/intel/socket_495/Config.lb	(revision 0)
+++ src/cpu/intel/socket_495/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_495.o 
Index: src/cpu/intel/socket_495/chip.h
===================================================================
--- src/cpu/intel/socket_495/chip.h	(revision 0)
+++ src/cpu/intel/socket_495/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_495_ops;
+
+struct cpu_intel_socket_495_config {
+};
Index: src/cpu/intel/socket_495/socket_495.c
===================================================================
--- src/cpu/intel/socket_495/socket_495.c	(revision 0)
+++ src/cpu/intel/socket_495/socket_495.c	(revision 0)
@@ -0,0 +1,28 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0686 */
+#include "../microcode/618-MU268602.inc"
+/* 0x068a */
+#include "../microcode/692-MU168a05.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0686 },
+	{ X86_VENDOR_INTEL, 0x068a },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_495_ops = {
+	CHIP_NAME("Socket 495 CPU")
+};
Index: src/cpu/intel/socket_775/Config.lb
===================================================================
--- src/cpu/intel/socket_775/Config.lb	(revision 0)
+++ src/cpu/intel/socket_775/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_775.o 
Index: src/cpu/intel/socket_775/chip.h
===================================================================
--- src/cpu/intel/socket_775/chip.h	(revision 0)
+++ src/cpu/intel/socket_775/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_775_ops;
+
+struct cpu_intel_socket_775_config {
+};
Index: src/cpu/intel/socket_775/socket_775.c
===================================================================
--- src/cpu/intel/socket_775/socket_775.c	(revision 0)
+++ src/cpu/intel/socket_775/socket_775.c	(revision 0)
@@ -0,0 +1,83 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 
+/* 0x06f2 */
+#include "../microcode/2129-m206f257.inc"
+/* 0x06f6 */
+#include "../microcode/2149-m46f6c9.inc"
+/* 0x06f7 */
+#include "../microcode/2151-m406f767.inc"
+/* 0x06fa */
+#include "../microcode/2096-m806fa92.inc"
+/* 0x06fb */
+#include "../microcode/2107-m406fbB4.inc"
+/* 0x06fd */
+#include "../microcode/2099-m16fda1.inc"
+/* 0x0f25 */
+#include "../microcode/1346-m10f252c.inc"
+/* 0x0f34 */
+#include "../microcode/1468-m1df3417.inc"
+/* 0x0f41 */
+#include "../microcode/1471-mbdf4117.inc"
+/* 0x0f43 */
+#include "../microcode/1460-m9df4305.inc"
+/* 0x0f44 */
+#include "../microcode/1469-m9df4406.inc"
+/* 0x0f47 */
+#include "../microcode/1470-m9df4703.inc"
+/* 0x0f49 */
+#include "../microcode/1462-mbdf4903.inc"
+/* 0x0f4a */
+#include "../microcode/1637-m5cf4a04.inc"
+/* 0x0f62 */
+#include "../microcode/1639-m04f620f.inc"
+/* 0x0f64 */
+#include "../microcode/1644-m34f6404.inc"
+/* 0x0f65 */
+#include "../microcode/2185-m04f650b.inc"
+/* 0x10661 */
+#include "../microcode/2111-m801066133.inc"
+/* 0x10676 - no microcode update for this CPU */
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x06f2 },
+	{ X86_VENDOR_INTEL, 0x06f6 },
+	{ X86_VENDOR_INTEL, 0x06f7 },
+	{ X86_VENDOR_INTEL, 0x06fa },
+	{ X86_VENDOR_INTEL, 0x06fb },
+	{ X86_VENDOR_INTEL, 0x06fd },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f34 },
+	{ X86_VENDOR_INTEL, 0x0f41 },
+	{ X86_VENDOR_INTEL, 0x0f43 },
+	{ X86_VENDOR_INTEL, 0x0f44 },
+	{ X86_VENDOR_INTEL, 0x0f47 },
+	{ X86_VENDOR_INTEL, 0x0f49 },
+	{ X86_VENDOR_INTEL, 0x0f4a },
+	{ X86_VENDOR_INTEL, 0x0f62 },
+	{ X86_VENDOR_INTEL, 0x0f64 },
+	{ X86_VENDOR_INTEL, 0x0f65 },	
+	/* Not sure if we'll see all 5 characters, so add both */
+	{ X86_VENDOR_INTEL, 0x0661 },
+	{ X86_VENDOR_INTEL, 0x10661 },
+	{ X86_VENDOR_INTEL, 0x0676 },
+	{ X86_VENDOR_INTEL, 0x10676 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_775_ops = {
+	CHIP_NAME("Socket LGA771 CPU")
+};
Index: src/cpu/intel/socket_478/Config.lb
===================================================================
--- src/cpu/intel/socket_478/Config.lb	(revision 0)
+++ src/cpu/intel/socket_478/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_478.o 
Index: src/cpu/intel/socket_478/chip.h
===================================================================
--- src/cpu/intel/socket_478/chip.h	(revision 0)
+++ src/cpu/intel/socket_478/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_478_ops;
+
+struct cpu_intel_socket_478_config {
+};
Index: src/cpu/intel/socket_478/socket_478.c
===================================================================
--- src/cpu/intel/socket_478/socket_478.c	(revision 0)
+++ src/cpu/intel/socket_478/socket_478.c	(revision 0)
@@ -0,0 +1,61 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0f0a */
+#include "../microcode/983-m02f0a15.inc"
+/* 0x0f12 */
+#include "../microcode/1070-m02f122f.inc"
+/* 0x0f13 */
+#include "../microcode/1072-m04f1305.inc"
+/* 0x0f24 */
+#include "../microcode/1107-m10f2421.inc"
+/* 0x0f25 */
+#include "../microcode/1346-m10f252c.inc"
+/* 0x0f27 */
+#include "../microcode/1102-m08f2739.inc"
+/* 0x0f29 */
+#include "../microcode/1340-m08f292f.inc"
+/* 0x0f33 */
+#include "../microcode/1467-m0df330c.inc"
+/* 0x0f34 */
+#include "../microcode/1468-m1df3417.inc"
+/* 0x0f41 */
+#include "../microcode/1471-mbdf4117.inc"
+/* 0x0f43 */
+#include "../microcode/1460-m9df4305.inc"
+/* 0x0f49 */
+#include "../microcode/1462-mbdf4903.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0f0a },
+	{ X86_VENDOR_INTEL, 0x0f12 },
+	{ X86_VENDOR_INTEL, 0x0f13 },
+	{ X86_VENDOR_INTEL, 0x0f24 },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f27 },
+	{ X86_VENDOR_INTEL, 0x0f29 },
+	{ X86_VENDOR_INTEL, 0x0f33 },
+	{ X86_VENDOR_INTEL, 0x0f34 },
+	{ X86_VENDOR_INTEL, 0x0f41 },
+/* intel.com says f42 is a Celeron D, but there's no microcode for it. 
+It may have been a typo, so I've added f43 just in case */ 
+	{ X86_VENDOR_INTEL, 0x0f42 },
+	//{ X86_VENDOR_INTEL, 0x0f43 },
+	{ X86_VENDOR_INTEL, 0x0f49 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_478_ops = {
+	CHIP_NAME("Socket 478 Pentium 4 CPU")
+};
Index: src/cpu/intel/socket_479/Config.lb
===================================================================
--- src/cpu/intel/socket_479/Config.lb	(revision 0)
+++ src/cpu/intel/socket_479/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver socket_479.o 
Index: src/cpu/intel/socket_479/chip.h
===================================================================
--- src/cpu/intel/socket_479/chip.h	(revision 0)
+++ src/cpu/intel/socket_479/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_479_ops;
+
+struct cpu_intel_socket_479_config {
+};
Index: src/cpu/intel/socket_479/socket_479.c
===================================================================
--- src/cpu/intel/socket_479/socket_479.c	(revision 0)
+++ src/cpu/intel/socket_479/socket_479.c	(revision 0)
@@ -0,0 +1,40 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0695 */
+#include "../microcode/1376-m8069547.inc"
+/* 0x0696 */
+#include "../microcode/621-mu169601.inc"
+/* 0x06b1 */
+#include "../microcode/738-MU16b11d.inc"
+/* 0x06b4 */
+#include "../microcode/885-MU16b402.inc"
+/* 0x06d6 */
+#include "../microcode/1355-m206d618.inc"
+/* 0x06d8 */
+#include "../microcode/1854-m86d821.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0695 },
+	{ X86_VENDOR_INTEL, 0x0696 },
+	{ X86_VENDOR_INTEL, 0x06b1 },
+	{ X86_VENDOR_INTEL, 0x06b4 },
+	{ X86_VENDOR_INTEL, 0x06d6 },
+	{ X86_VENDOR_INTEL, 0x06d8 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_socket_479_ops = {
+	CHIP_NAME("Socket 479 CPU")
+};
Index: src/cpu/intel/slot_1/Config.lb
===================================================================
--- src/cpu/intel/slot_1/Config.lb	(revision 0)
+++ src/cpu/intel/slot_1/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver slot_1.o 
Index: src/cpu/intel/slot_1/slot_1.c
===================================================================
--- src/cpu/intel/slot_1/slot_1.c	(revision 0)
+++ src/cpu/intel/slot_1/slot_1.c	(revision 0)
@@ -0,0 +1,60 @@
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+u32 microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+/* 0x0633 */
+#include "../microcode/308-MU163336.inc"
+/* 0x0634 */
+#include "../microcode/309-MU163437.inc"
+/* 0x0650 */
+#include "../microcode/433-MU165045.inc"
+/* 0x0651 */
+#include "../microcode/436-MU165142.inc"
+/* 0x0652 */
+#include "../microcode/423-MU26522b.inc"
+/* 0x0653 */
+#include "../microcode/452-MU165310.inc"
+/* 0x066a */
+#include "../microcode/401-MU166a0d.inc"
+/* 0x0672 */
+#include "../microcode/540-mu267238.inc"
+/* 0x0673 */
+#include "../microcode/531-mu26732e.inc"
+/* 0x0681 */
+#include "../microcode/538-MU168111.inc"
+/* 0x0683 */
+#include "../microcode/729-MU268310.inc"
+/* 0x0686 */
+#include "../microcode/618-MU268602.inc"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+/* Slot 1 CPU IDs. Note that the same ID is sometimes used for Celeron,
+ * Pentium, and Xeon families, in various packages. This also includes
+ * Mobile Pentium II and Celeron families */
+struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x0633 },
+	{ X86_VENDOR_INTEL, 0x0634 },
+	{ X86_VENDOR_INTEL, 0x0650 },
+	{ X86_VENDOR_INTEL, 0x0651 },
+	{ X86_VENDOR_INTEL, 0x0652 },
+	{ X86_VENDOR_INTEL, 0x0653 },
+	{ X86_VENDOR_INTEL, 0x0672 },
+	{ X86_VENDOR_INTEL, 0x0673 },
+	{ X86_VENDOR_INTEL, 0x0681 },
+	{ X86_VENDOR_INTEL, 0x0683 },
+	{ X86_VENDOR_INTEL, 0x0686 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_slot_1_ops = {
+	CHIP_NAME("Intel Slot 1 CPU")
+};
\ No newline at end of file
Index: src/cpu/intel/slot_1/chip.h
===================================================================
--- src/cpu/intel/slot_1/chip.h	(revision 0)
+++ src/cpu/intel/slot_1/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_slot_1_ops;
+
+struct cpu_intel_slot_1_config {
+};
Index: src/cpu/intel/intel_shared/intel_init.c
===================================================================
--- src/cpu/intel/intel_shared/intel_init.c	(revision 0)
+++ src/cpu/intel/intel_shared/intel_init.c	(revision 0)
@@ -0,0 +1,53 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#ifdef CONFIG_SMP
+#if CONFIG_SMP
+#include <cpu/intel/hyperthreading.h>
+#endif
+#endif
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+struct cpu_device_id cpu_table[];
+#ifndef NO_MICROCODE_UPDATES
+u32 microcode_updates[];
+#endif
+
+static void intel_init(device_t dev)
+{
+	/* Turn on L1 caching if we haven't already */
+	x86_enable_cache();
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+
+#ifndef NO_MICROCODE_UPDATES
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+#endif
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+#ifdef CONFIG_SMP
+#if CONFIG_SMP
+	/* Start up my cpu siblings */
+	intel_sibling_init(dev);
+#endif
+#endif
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init     = intel_init,
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
Index: src/cpu/intel/intel_shared/Config.lb
===================================================================
--- src/cpu/intel/intel_shared/Config.lb	(revision 0)
+++ src/cpu/intel/intel_shared/Config.lb	(revision 0)
@@ -0,0 +1,11 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
Index: src/cpu/intel/slot_2/Config.lb
===================================================================
--- src/cpu/intel/slot_2/Config.lb	(revision 3036)
+++ src/cpu/intel/slot_2/Config.lb	(working copy)
@@ -1,3 +0,0 @@
-config chip.h
-object slot_2.o
-dir /cpu/intel/model_6xx
Index: src/cpu/intel/slot_2/slot_2.c
===================================================================
--- src/cpu/intel/slot_2/slot_2.c	(revision 3036)
+++ src/cpu/intel/slot_2/slot_2.c	(working copy)
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-
-struct chip_operations cpu_intel_slot_2_ops = {
-	CHIP_NAME("Slot 2 CPU")
-};
Index: src/cpu/intel/slot_2/chip.h
===================================================================
--- src/cpu/intel/slot_2/chip.h	(revision 3036)
+++ src/cpu/intel/slot_2/chip.h	(working copy)
@@ -1,4 +0,0 @@
-extern struct chip_operations cpu_intel_slot_2_ops;
-
-struct cpu_intel_slot_2_config {
-};
Index: src/cpu/intel/model_6xx/microcode_MU16810d.h
===================================================================
--- src/cpu/intel/model_6xx/microcode_MU16810d.h	(revision 3036)
+++ src/cpu/intel/model_6xx/microcode_MU16810d.h	(working copy)
@@ -1,140 +0,0 @@
-	/*
-	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000. 
-
-	  These microcode updates are distributed for the sole purpose of 
-	  installation in the BIOS or Operating System of computer systems
-	  which include an Intel P6 family microprocessor sold or distributed
-	  to or by you.  You are authorized to copy and install this material
-	  on such systems.  You are not authorized to use this material for
-	  any other purpose.  
-	*/
-
-/*  MU16810d.inc  */
-	0x00000001,	0x0000000d,	0x09211999,	0x00000681,
-	0x31708166,	0x00000001,	0x00000001,	0x00000000,
-	0x00000000,	0x00000000,	0x00000000,	0x00000000,
-	0x710e5240,	0xab8bc2df,	0x6e652d5a,	0xcc16718b,
-	0xaa5c7d1a,	0x43ac1ba0,	0xbdf8684e,	0x82565fa7,
-	0x1d108edc,	0x96d2d5a2,	0x85f783a0,	0x16e4cba1,
-	0xbc311213,	0xc36c45a2,	0x443b8d2b,	0xfdc5e9ce,
-	0xbb6f8637,	0x47011b8b,	0xf3898e4a,	0xb3e90f68,
-	0x60af6e3a,	0xff9d3de4,	0x9fb2333c,	0x5a1a39ce,
-	0xffd75d72,	0xa60cc2c0,	0x5729267c,	0xfc6d2da7,
-	0x8a2c8ae7,	0x71aba5ba,	0xb639ff31,	0x8d1642b8,
-	0x3aa67efc,	0x9f786473,	0xaedec560,	0x1acb694f,
-	0x97582a6f,	0x8dc17ea5,	0x19636cfe,	0xb5032243,
-	0xc46f764f,	0x3a5d3833,	0xf3d1a2b9,	0xc22e59be,
-	0x15e0b2f3,	0xe58eff24,	0xc679600d,	0x21a3a845,
-	0xc11cc921,	0xed2f5061,	0x2d4db0d1,	0xcc0cc78f,
-	0x80197c08,	0x20739d8a,	0xc92ec866,	0xacef343b,
-	0x47c0913a,	0xee8a69e4,	0xa7b0157e,	0x4c3607a9,
-	0xcc7ff7ea,	0xb0a36667,	0x41d1bcf0,	0xf54c42d2,
-	0x946c590e,	0x6da18fe9,	0xf20df0e6,	0x984a2160,
-	0x479becd3,	0xfb11dd36,	0xbb816653,	0x60c605c2,
-	0xf52efe8b,	0x90a9f863,	0x69654bfa,	0xf0f03f7c,
-	0xbf0498d5,	0x68708d82,	0xdab94924,	0x92371217,
-	0x603feed7,	0xf0ff8329,	0x9c8769df,	0x6d40ab73,
-	0xd8fd132a,	0x9335543f,	0x40fd3abb,	0xf25665a0,
-	0x93fe56a6,	0x682a3b24,	0xf3a0f14a,	0x97e92084,
-	0x4e8736a3,	0xf322db48,	0xb65de2ad,	0x6af68474,
-	0xfd6dae0d,	0x953afb0e,	0x6ef22a82,	0xfa7a3d7b,
-	0xb5fe683f,	0x647579c3,	0xd184e7db,	0x99ec7c97,
-	0x66486a26,	0xf08c8290,	0x94eb3fce,	0x6305e16e,
-	0xd61dd210,	0x9b8bdbba,	0x41a4b4f5,	0xfca38a75,
-	0x9c55c7a4,	0x6a4b1f02,	0xf277077a,	0x900e3d03,
-	0x4f173146,	0xf6fbf7c8,	0xb2636cb2,	0x6329a9d7,
-	0xf2697eb4,	0x90f80f6f,	0x65de6167,	0xfc6cd065,
-	0xb4326188,	0x67507c3a,	0xdf3179ff,	0x91207c0b,
-	0x6408ad58,	0xf7e7d2fe,	0x999af7c0,	0x6a994828,
-	0xdaecedf4,	0x93cba457,	0x4d924b31,	0xf12b5ae1,
-	0x9563d541,	0x65bd28f8,	0xfa87a363,	0x983adc3d,
-	0x45c4f64d,	0xfae3e1ef,	0xb2eb287f,	0x6050f699,
-	0xfb28cfb6,	0x999b1d45,	0x65027980,	0xf4e507d0,
-	0xbbd059b7,	0x64cb2688,	0xd29dff15,	0x90927c2c,
-	0x6d52471a,	0xf64fc745,	0x9e4050ff,	0x68b66e3f,
-	0xd0a1dd96,	0x9fe8a5a3,	0x454c936b,	0xf926115d,
-	0x9bfb60ff,	0x604049aa,	0xf3509e5c,	0x9d6cf26f,
-	0x4d777c5a,	0xfd7cd5ff,	0xb15d4f35,	0x6b1aa6e3,
-	0xfa279f20,	0x94916fae,	0x9b04dbcc,	0x600defd9,
-	0xf2977cd8,	0x65fa64be,	0x968feaee,	0xc11681af,
-	0x66568af6,	0xa539a4ee,	0xcfed5cb1,	0x108445de,
-	0xa603dfdd,	0xbf5ada02,	0x14b868c5,	0xb2d3b8d2,
-	0xbabf3637,	0x0c25bfbc,	0xb7a4c247,	0xf2837e05,
-	0x062ce963,	0xfcb65c46,	0xc6d190e7,	0x4dfce123,
-	0xcb0bf4c7,	0x8bff9d9d,	0x6794e002,	0x2879661e,
-	0xa5e93199,	0x77be4be8,	0x22fe3324,	0xb943e4ef,
-	0x73463d52,	0x31471050,	0xb68fd63f,	0x84cad24f,
-	0x343d922b,	0x42b9ab31,	0x88ee1549,	0xe913e2ab,
-	0x4a127048,	0x5057f79f,	0x636eb512,	0x42e02f9c,
-	0xd3a8b863,	0x9bc40609,	0x4a18edb5,	0x86a4bdaa,
-	0x91819a4b,	0x12a11e17,	0x8a6d7f21,	0xf42998d9,
-	0x132b6bbd,	0xe3239feb,	0xf52519d7,	0xada08128,
-	0xe6febacf,	0x44e15a80,	0xa977610a,	0xf56a8665,
-	0x4693b6f0,	0xb8386320,	0xfcf7d071,	0xb8a1128d,
-	0xb2a45d18,	0x075a2095,	0x98ebde53,	0xe8762eaf,
-	0x838ba96f,	0x4f0239d3,	0xf295395e,	0xb3c38631,
-	0x7ea7a143,	0x157a4e43,	0x46f8173f,	0xfbc18d4a,
-	0xc401e17a,	0xc4620358,	0xd2ab5437,	0xa01db06f,
-	0x58ce91fc,	0x850de1a3,	0x9b542dba,	0xee77f038,
-	0xddd3ced6,	0xc225d2ce,	0x63a3f765,	0x3342a06c,
-	0x6a780c2f,	0xfaa925b2,	0x366ebeec,	0xbcc9abea,
-	0xc7b3fa4e,	0xf4f1123d,	0x5198702c,	0x3e3458b7,
-	0x0b1ce9a1,	0x51b1bd7f,	0x711e791e,	0x927d8bed,
-	0x91dbaea9,	0x7eefbda9,	0x7a19edd9,	0xdf7b8dce,
-	0x5bb40613,	0x0b0c1e0f,	0x85b82c98,	0x18da4dc1,
-	0xc5fd78ac,	0x57c1e31d,	0x4c4001b5,	0xe31d2643,
-	0xa6afbf58,	0xad200e68,	0xf0114ba4,	0xd6a620f2,
-	0xc753a720,	0xac9022a0,	0x28a41f01,	0x22a4ba95,
-	0xc00b7531,	0x23d42795,	0xcd836a86,	0x90262708,
-	0x3292cad0,	0x40022e39,	0xc1581b0a,	0xe5101550,
-	0x6538096b,	0x208c549d,	0x3ce2bf88,	0xa71df38e,
-	0x3dec3685,	0xca3949f1,	0x79f3ad1b,	0x3ee8b300,
-	0x9d305fc6,	0x7a2e5288,	0xbe81a2f2,	0x7ada0c06,
-	0x191c7f01,	0x58dfcbd1,	0xc78dee72,	0x72364226,
-	0x1866de12,	0x8d22305c,	0x943a0f0e,	0xc81967ff,
-	0x4d55fb0f,	0xaf199be1,	0x90bbda61,	0x4e7c234f,
-	0x90cfec16,	0x9b4bcf26,	0x21622023,	0x0926f0fa,
-	0x1d504377,	0xa58db427,	0x8d93ce2b,	0x90bfe900,
-	0x29e67397,	0x2c1261ed,	0x4ace9474,	0xd5c60282,
-	0xe53fb300,	0x8a61a0ab,	0xa7aa0918,	0x4389d7c5,
-	0xd09d605c,	0x6c5bedb5,	0xd6d54c51,	0x433dea21,
-	0x7ad9e677,	0x813bff76,	0x5a162c75,	0x1ee0661f,
-	0x9b6c2030,	0x8e8dc989,	0xcd4bc9fc,	0x4454675b,
-	0x8d583c9c,	0xe3400094,	0x116ebb83,	0xe847bc9a,
-	0x2a4622dd,	0x2a901e6f,	0xd789b1c0,	0x094e2bbb,
-	0x056e563f,	0x9f17e606,	0x8bc79b8d,	0xd2c535c1,
-	0x06a45a27,	0x9dc56771,	0xa06649e2,	0x5ff25ac8,
-	0x6554961e,	0x98e583d9,	0x38ba93da,	0xdee1de18,
-	0x037cb9d5,	0x6b17f195,	0x3431faaf,	0x13860a0d,
-	0x28bca10d,	0x0a54c011,	0x9957cdb6,	0x3aa1f429,
-	0x9d41b7b3,	0x9aea5be2,	0x60c7ce6b,	0x4cd1c10b,
-	0x24ddddcd,	0xe28412ba,	0xa03a5466,	0xa1896879,
-	0x59edcb87,	0x1b241765,	0x157bf161,	0xf219f950,
-	0xe86ff526,	0x262005d9,	0x11769531,	0xbca15d95,
-	0x28f5ef17,	0x1f27e725,	0xc32631d2,	0x07249e61,
-	0x1ba851e3,	0x4f49b577,	0xe2a1df5e,	0x826fa7ff,
-	0xc34e1e2e,	0x7fe26024,	0xbc19800f,	0x0d368dc9,
-	0xe03da0c6,	0xadaa4f9c,	0x9ad1e43c,	0x96f84e44,
-	0x0b6cd695,	0x1bb46971,	0x942d6e5b,	0x6316170d,
-	0x3164509f,	0xc6659450,	0xb2a0370a,	0xabc208e8,
-	0x6d479811,	0x3684bc0e,	0x80b7b101,	0xa50b7bb5,
-	0x43d21233,	0xb423559d,	0xf41dcd16,	0xdfd3c276,
-	0x3e586469,	0xd9b7630a,	0xb88f9e44,	0x0cda6f4d,
-	0xe5bf5844,	0x8709f788,	0xdae37da6,	0x1fb41777,
-	0x1d903f69,	0x34383b69,	0xd409ae70,	0xd1c99758,
-	0xdedfd7a4,	0xa4bdf018,	0xf4058202,	0x8565d66f,
-	0x5365aed9,	0xfa69742e,	0x2cfbfbcf,	0x88a00b60,
-	0x506c0713,	0x2866475b,	0x3e1df573,	0xb86f7feb,
-	0x31d23a7f,	0xc6320e6a,	0x3ebbc2a5,	0x83a1d4ef,
-	0x15169f5f,	0x42a61753,	0x893e553e,	0x4ddbc66d,
-	0x7449ec1f,	0x76f65d22,	0x0622e13b,	0x32986f89,
-	0x21181b4b,	0x99a80c0a,	0xd6fe00b0,	0x282c0e81,
-	0x9fc1cf88,	0x919b855d,	0x618257d8,	0x82c448b8,
-	0xe22537a1,	0xa90de388,	0xba73b90c,	0xd765eeb0,
-	0x62b2727e,	0xa08dfe20,	0x70b3c8c5,	0x3ef04007,
-	0x9f73732b,	0x2201edd7,	0xb836219c,	0xf913af7c,
-	0xf50f64ca,	0x93ac107a,	0xf509f84a,	0x6f6026f6,
-	0xd9bb8eac,	0x4b268cfa,	0xa65a3fa6,	0x9837cb75,
-	0x784fb835,	0x2060576d,	0xb1604cae,	0xb9da4116,
-	0xab320cf2,	0x60a1b501,	0x0c73fa79,	0x8d5a6f1e,
-	0x57688086,	0x218e4005,	0xca054e3d,	0xc1a3c3ec,
Index: src/cpu/intel/model_6xx/microcode_MU16830c.h
===================================================================
--- src/cpu/intel/model_6xx/microcode_MU16830c.h	(revision 3036)
+++ src/cpu/intel/model_6xx/microcode_MU16830c.h	(working copy)
@@ -1,140 +0,0 @@
-	/*
-	  Copyright  Intel Corporation, 1995, 96, 97, 98, 99, 2000. 
-
-	  These microcode updates are distributed for the sole purpose of 
-	  installation in the BIOS or Operating System of computer systems
-	  which include an Intel P6 family microprocessor sold or distributed
-	  to or by you.  You are authorized to copy and install this material
-	  on such systems.  You are not authorized to use this material for
-	  any other purpose.  
-	*/
-
-/*  MU16830c.inc  */
-	0x00000001,	0x0000000c,	0x01102000,	0x00000683,
-	0xb1605bca,	0x00000001,	0x00000001,	0x00000000,
-	0x00000000,	0x00000000,	0x00000000,	0x00000000,
-	0x7d021266,	0xd3890df1,	0x08a3a61b,	0x3c9bd396,
-	0x516b77d0,	0xf119ce39,	0xd63a44b0,	0x523efada,
-	0x1a0c3ed7,	0x04711f21,	0x515f945e,	0xbb5f13ba,
-	0x254eabfc,	0x5bd1e959,	0x67373898,	0x61605a8f,
-	0x6ea7c5a9,	0x5e64a058,	0xc0a019ee,	0x56af4cfe,
-	0x1acd6406,	0x4e7eb040,	0xf2ebd7ef,	0xc659db4f,
-	0xfe77108b,	0xfdceb47b,	0xf0757eb8,	0xb1622949,
-	0xdceb744b,	0x19e2ad26,	0xe9c745ab,	0xb385f196,
-	0x9ecc3483,	0x0a126045,	0x5320d6be,	0x8557a583,
-	0x7faf0073,	0x5ab281b4,	0x34dbbac6,	0x8a0bc7cd,
-	0x52584248,	0x3c3ef309,	0x41403737,	0x8200991d,
-	0x7e0dfb86,	0xea1e3a8f,	0x5b87ca8a,	0x004be481,
-	0x74e9fd6f,	0x80d518d6,	0xf10672c8,	0x2b8936b5,
-	0xd7092242,	0xbaa950a4,	0xaa6a2305,	0xeccbb48b,
-	0x43f6b561,	0x8607570a,	0x6143ba7b,	0x4c534447,
-	0x45d97f76,	0x0ccf7b83,	0xd89482bd,	0x32c46a60,
-	0x6db7b842,	0x0f7ad008,	0x4ce4968c,	0x2af52761,
-	0x26a2a653,	0x5806f996,	0xfe844901,	0x6164e754,
-	0xaf9287ab,	0x1f495a8d,	0x6cd70b5e,	0x681df673,
-	0xc94dc88f,	0x4b9650f8,	0xdfc826d9,	0xb5710e59,
-	0x80ed0f08,	0x615ce9c2,	0x0864130d,	0xc604520e,
-	0x9be149db,	0xeefb463f,	0x15b7e000,	0xc3bf13ab,
-	0x29d75556,	0x99420678,	0x505b5858,	0x6dadaeae,
-	0xf87f8f56,	0xe9be5867,	0xd772475a,	0x0a4642c0,
-	0xc59b2b86,	0x9e0f0a7f,	0x4c54834f,	0xb39f1d7c,
-	0xd52dac56,	0x1fdde74b,	0x60fddc1c,	0x367321f1,
-	0x98a7c9bd,	0x9a7896d2,	0x8d1f200b,	0x7975e907,
-	0x0e7d4411,	0x1671c027,	0x438550a2,	0x385dfc21,
-	0xb26c638d,	0x9b43b0d2,	0x03a0512d,	0x6b195c14,
-	0x9db53322,	0x78512b73,	0x86714a5b,	0x9b900bb3,
-	0xdbd702f9,	0xcdb985cb,	0x1033fd1e,	0xc75ed099,
-	0x8a8c99fc,	0x12c5b949,	0x913249a0,	0xbd40f4b1,
-	0x87406189,	0x977927e0,	0x76915a37,	0x79ffa5f2,
-	0x5e1812b8,	0x8e7eb819,	0x6bfc46a5,	0x8d80c798,
-	0x56d5a7ec,	0x5904350a,	0x82a1b59a,	0x27c64a52,
-	0x4effaac0,	0x8e1519ec,	0x29ffed29,	0x3eaccc55,
-	0x823e79c1,	0xdb5f2295,	0xb6ab9c23,	0xb301f2c5,
-	0xe17f14f3,	0xf4e8892a,	0x107c9db8,	0x6a8a8ff4,
-	0xaf9df422,	0xb14bd8f4,	0x00fa2a4c,	0x15324701,
-	0x95e86a3b,	0xf74566e1,	0x386a788f,	0x9333e875,
-	0xdea61190,	0x307a5338,	0xd9cec152,	0xe77165da,
-	0x54187a14,	0x9a7d99bf,	0x4b31e986,	0x7d7ed557,
-	0x626bb548,	0x434c4a78,	0x562b1588,	0xe0d15f63,
-	0x524473f7,	0x484459e1,	0xbe617125,	0xb96f7eb8,
-	0xb86620f7,	0xcc1e09b1,	0x7ad3b154,	0xae1f697e,
-	0x11d0bfb1,	0xb1218568,	0x83a44b34,	0xeecec8bc,
-	0xa06b01d8,	0xccadf143,	0xe1f9702c,	0x1e7c3d0d,
-	0xd907d836,	0x780b3a02,	0x9a5e81fa,	0x0015cf61,
-	0xbd148c0c,	0x84a65389,	0x99e77502,	0x0d630a94,
-	0xd7f97779,	0x75567907,	0xa859be05,	0x8baab7b7,
-	0x4f1a8101,	0x9992f951,	0xdd918c8a,	0x12b3ca17,
-	0x117358b4,	0xf27a4783,	0xe3363be6,	0x3847f05d,
-	0xb642595a,	0x4fbb98ae,	0xd6259c55,	0x3c72ff94,
-	0xa9c3e102,	0x256e26c1,	0x2faf190b,	0xaaa1d198,
-	0x8e25fc06,	0x8aa6fc5d,	0x9b994d46,	0x15045f23,
-	0x23813558,	0x0173ef1b,	0xe4198a76,	0x36aa0de4,
-	0x341d7595,	0xe186740f,	0xec371375,	0x1a4cabbe,
-	0x6241897f,	0x388bd888,	0x2542e1f7,	0x61620df5,
-	0x209f9d94,	0xca90f89b,	0x286a3e92,	0xea1cc30f,
-	0x838ba96f,	0x4f0239d3,	0xf295395e,	0xb3c38631,
-	0x7ea7a143,	0x157a4e43,	0x46f8173f,	0xfbc18d4a,
-	0xc401e17a,	0xc4620358,	0xd2ab5437,	0xa01db06f,
-	0x58ce91fc,	0x850de1a3,	0x9b542dba,	0xee77f038,
-	0xddd3ced6,	0xc225d2ce,	0x63a3f765,	0x3342a06c,
-	0x6a780c2f,	0xfaa925b2,	0x366ebeec,	0xbcc9abea,
-	0xc7b3fa4e,	0xf4f1123d,	0x5198702c,	0x3e3458b7,
-	0x0b1ce9a1,	0x51b1bd7f,	0x711e791e,	0x927d8bed,
-	0x91dbaea9,	0x7eefbda9,	0x7a19edd9,	0xdf7b8dce,
-	0x5bb40613,	0x0b0c1e0f,	0x85b82c98,	0x18da4dc1,
-	0xc5fd78ac,	0x57c1e31d,	0x4c4001b5,	0xe31d2643,
-	0xa6afbf58,	0xad200e68,	0xf0114ba4,	0xd6a620f2,
-	0xc753a720,	0xac9022a0,	0x28a41f01,	0x22a4ba95,
-	0xc00b7531,	0x23d42795,	0xcd836a86,	0x90262708,
-	0x3292cad0,	0x40022e39,	0xc1581b0a,	0xe5101550,
-	0x6538096b,	0x208c549d,	0x3ce2bf88,	0xa71df38e,
-	0x3dec3685,	0xca3949f1,	0x79f3ad1b,	0x3ee8b300,
-	0x9d305fc6,	0x7a2e5288,	0xbe81a2f2,	0x7ada0c06,
-	0x191c7f01,	0x58dfcbd1,	0xc78dee72,	0x72364226,
-	0x1866de12,	0x8d22305c,	0x943a0f0e,	0xc81967ff,
-	0x4d55fb0f,	0xaf199be1,	0x90bbda61,	0x4e7c234f,
-	0x90cfec16,	0x9b4bcf26,	0x21622023,	0x0926f0fa,
-	0x1d504377,	0xa58db427,	0x8d93ce2b,	0x90bfe900,
-	0x29e67397,	0x2c1261ed,	0x4ace9474,	0xd5c60282,
-	0xe53fb300,	0x8a61a0ab,	0xa7aa0918,	0x4389d7c5,
-	0xd09d605c,	0x6c5bedb5,	0xd6d54c51,	0x433dea21,
-	0x7ad9e677,	0x813bff76,	0x5a162c75,	0x1ee0661f,
-	0x9b6c2030,	0x8e8dc989,	0xcd4bc9fc,	0x4454675b,
-	0x8d583c9c,	0xe3400094,	0x116ebb83,	0xe847bc9a,
-	0x2a4622dd,	0x2a901e6f,	0xd789b1c0,	0x094e2bbb,
-	0x056e563f,	0x9f17e606,	0x8bc79b8d,	0xd2c535c1,
-	0x06a45a27,	0x9dc56771,	0xa06649e2,	0x5ff25ac8,
-	0x6554961e,	0x98e583d9,	0x38ba93da,	0xdee1de18,
-	0x037cb9d5,	0x6b17f195,	0x3431faaf,	0x13860a0d,
-	0x28bca10d,	0x0a54c011,	0x9957cdb6,	0x3aa1f429,
-	0x9d41b7b3,	0x9aea5be2,	0x60c7ce6b,	0x4cd1c10b,
-	0x24ddddcd,	0xe28412ba,	0xa03a5466,	0xa1896879,
-	0x59edcb87,	0x1b241765,	0x157bf161,	0xf219f950,
-	0xe86ff526,	0x262005d9,	0x11769531,	0xbca15d95,
-	0x28f5ef17,	0x1f27e725,	0xc32631d2,	0x07249e61,
-	0x1ba851e3,	0x4f49b577,	0xe2a1df5e,	0x826fa7ff,
-	0xc34e1e2e,	0x7fe26024,	0xbc19800f,	0x0d368dc9,
-	0xe03da0c6,	0xadaa4f9c,	0x9ad1e43c,	0x96f84e44,
-	0x0b6cd695,	0x1bb46971,	0x942d6e5b,	0x6316170d,
-	0x3164509f,	0xc6659450,	0xb2a0370a,	0xabc208e8,
-	0x6d479811,	0x3684bc0e,	0x80b7b101,	0xa50b7bb5,
-	0x43d21233,	0xb423559d,	0xf41dcd16,	0xdfd3c276,
-	0x3e586469,	0xd9b7630a,	0xb88f9e44,	0x0cda6f4d,
-	0xe5bf5844,	0x8709f788,	0xdae37da6,	0x1fb41777,
-	0x1d903f69,	0x34383b69,	0xd409ae70,	0xd1c99758,
-	0xdedfd7a4,	0xa4bdf018,	0xf4058202,	0x8565d66f,
-	0x5365aed9,	0xfa69742e,	0x2cfbfbcf,	0x88a00b60,
-	0x506c0713,	0x2866475b,	0x3e1df573,	0xb86f7feb,
-	0x31d23a7f,	0xc6320e6a,	0x3ebbc2a5,	0x83a1d4ef,
-	0x15169f5f,	0x42a61753,	0x893e553e,	0x4ddbc66d,
-	0x7449ec1f,	0x76f65d22,	0x0622e13b,	0x32986f89,
-	0x21181b4b,	0x99a80c0a,	0xd6fe00b0,	0x282c0e81,
-	0x9fc1cf88,	0x919b855d,	0x618257d8,	0x82c448b8,
-	0xe22537a1,	0xa90de388,	0xba73b90c,	0xd765eeb0,
-	0x62b2727e,	0xa08dfe20,	0x70b3c8c5,	0x3ef04007,
-	0x9f73732b,	0x2201edd7,	0xb836219c,	0xf913af7c,
-	0xf50f64ca,	0x93ac107a,	0xf509f84a,	0x6f6026f6,
-	0xd9bb8eac,	0x4b268cfa,	0xa65a3fa6,	0x9837cb75,
-	0x784fb835,	0x2060576d,	0xb1604cae,	0xb9da4116,
-	0xab320cf2,	0x60a1b501,	0x0c73fa79,	0x8d5a6f1e,
-	0x57688086,	0x218e4005,	0xca054e3d,	0xc1a3c3ec,
Index: src/cpu/intel/model_6xx/Config.lb
===================================================================
--- src/cpu/intel/model_6xx/Config.lb	(revision 3036)
+++ src/cpu/intel/model_6xx/Config.lb	(working copy)
@@ -1,9 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/fpu
-dir /cpu/x86/mmx
-dir /cpu/x86/sse
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/intel/microcode
-driver model_6xx_init.o
Index: src/cpu/intel/model_6xx/model_6xx_init.c
===================================================================
--- src/cpu/intel/model_6xx/model_6xx_init.c	(revision 3036)
+++ src/cpu/intel/model_6xx/model_6xx_init.c	(working copy)
@@ -1,63 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/intel/microcode.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-
-static uint32_t microcode_updates[] = {
-	/* WARNING - Intel has a new data structure that has variable length
-	 * microcode update lengths.  They are encoded in int 8 and 9.  A
-	 * dummy header of nulls must terminate the list.
-	 */
-#include "microcode_MU16810d.h"	
-#include "microcode_MU16830c.h"
-	/*  Dummy terminator  */
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-        0x0, 0x0, 0x0, 0x0,
-};
-
-
-static void model_6xx_init(device_t dev)
-{
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-	x86_setup_mtrrs(36);
-	x86_mtrr_check();
-	
-	/* Update the microcode */
-	intel_update_microcode(microcode_updates);
-
-	/* Enable the local cpu apics */
-	setup_lapic();
-};
-
-static struct device_operations cpu_dev_ops = {
-	.init     = model_6xx_init,
-};
-static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_INTEL, 0x0665 }, /* Celeron (Mendocino) */
-	{ X86_VENDOR_INTEL, 0x0672 },
-	{ X86_VENDOR_INTEL, 0x0673 },
-	{ X86_VENDOR_INTEL, 0x0681 },
-	{ X86_VENDOR_INTEL, 0x0683 },
-	{ X86_VENDOR_INTEL, 0x0686 },
-	{ X86_VENDOR_INTEL, 0x06A0 },
-	{ X86_VENDOR_INTEL, 0x06A1 },
-	{ X86_VENDOR_INTEL, 0x06A4 },
-	{ X86_VENDOR_INTEL, 0x06B4 }, /* Mobile Celeron FCBGA */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver driver __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
Index: src/cpu/intel/intel_generic/Config.lb
===================================================================
--- src/cpu/intel/intel_generic/Config.lb	(revision 0)
+++ src/cpu/intel/intel_generic/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+dir /cpu/intel/intel_shared
+
+driver intel_generic.o 
Index: src/cpu/intel/intel_generic/intel_generic.c
===================================================================
--- src/cpu/intel/intel_generic/intel_generic.c	(revision 0)
+++ src/cpu/intel/intel_generic/intel_generic.c	(revision 0)
@@ -0,0 +1,85 @@
+#define NO_MICROCODE_UPDATES
+#include "../intel_shared/intel_init.c"
+#include "chip.h"
+
+/* CPU IDs for all >=PPro x86 and x86_64 Intel CPUs, as of 12/30/2007, without 
+ * the microcode updates. Microcode updates should be done later, with recent 
+ * kernels this is done automatically, just put the latest microcode update file
+ * in /etc/firmware */
+struct cpu_device_id cpu_table[] = {
+/* TODO!!! */
+	{ X86_VENDOR_INTEL, 0x0611 },
+	{ X86_VENDOR_INTEL, 0x0612 },
+	{ X86_VENDOR_INTEL, 0x0616 },
+	{ X86_VENDOR_INTEL, 0x0617 },
+	{ X86_VENDOR_INTEL, 0x0619 },
+	{ X86_VENDOR_INTEL, 0x0633 },
+	{ X86_VENDOR_INTEL, 0x0634 },
+	{ X86_VENDOR_INTEL, 0x0650 },
+	{ X86_VENDOR_INTEL, 0x0651 },
+	{ X86_VENDOR_INTEL, 0x0652 },
+	{ X86_VENDOR_INTEL, 0x0660 },
+	{ X86_VENDOR_INTEL, 0x0665 },
+	{ X86_VENDOR_INTEL, 0x066a },
+	{ X86_VENDOR_INTEL, 0x066d },
+	{ X86_VENDOR_INTEL, 0x0671 },
+	{ X86_VENDOR_INTEL, 0x0672 },
+	{ X86_VENDOR_INTEL, 0x0673 },
+	{ X86_VENDOR_INTEL, 0x0680 },
+	{ X86_VENDOR_INTEL, 0x0681 },
+	{ X86_VENDOR_INTEL, 0x0683 },
+	{ X86_VENDOR_INTEL, 0x0686 },
+	{ X86_VENDOR_INTEL, 0x068a },
+	{ X86_VENDOR_INTEL, 0x0695 },
+	{ X86_VENDOR_INTEL, 0x0696 },
+	{ X86_VENDOR_INTEL, 0x06a0 },
+	{ X86_VENDOR_INTEL, 0x06a1 },
+	{ X86_VENDOR_INTEL, 0x06a4 },
+	{ X86_VENDOR_INTEL, 0x06b1 },
+	{ X86_VENDOR_INTEL, 0x06b4 },
+	{ X86_VENDOR_INTEL, 0x06d6 },
+	{ X86_VENDOR_INTEL, 0x06d8 },
+	{ X86_VENDOR_INTEL, 0x06e8 },
+	{ X86_VENDOR_INTEL, 0x06ec },
+	{ X86_VENDOR_INTEL, 0x06f2 },
+	{ X86_VENDOR_INTEL, 0x06f6 },
+	{ X86_VENDOR_INTEL, 0x06f7 },
+	{ X86_VENDOR_INTEL, 0x06fa },
+	{ X86_VENDOR_INTEL, 0x06fb },
+	{ X86_VENDOR_INTEL, 0x06fd },
+	{ X86_VENDOR_INTEL, 0x0f07 },
+	{ X86_VENDOR_INTEL, 0x0f0a },
+	{ X86_VENDOR_INTEL, 0x0f11 },
+	{ X86_VENDOR_INTEL, 0x0f12 },
+	{ X86_VENDOR_INTEL, 0x0f13 },
+	{ X86_VENDOR_INTEL, 0x0f22 },
+	{ X86_VENDOR_INTEL, 0x0f24 },
+	{ X86_VENDOR_INTEL, 0x0f25 },
+	{ X86_VENDOR_INTEL, 0x0f26 },
+	{ X86_VENDOR_INTEL, 0x0f27 },
+	{ X86_VENDOR_INTEL, 0x0f29 },
+	{ X86_VENDOR_INTEL, 0x0f32 },
+	{ X86_VENDOR_INTEL, 0x0f33 },
+	{ X86_VENDOR_INTEL, 0x0f34 },
+	{ X86_VENDOR_INTEL, 0x0f41 },
+	{ X86_VENDOR_INTEL, 0x0f43 },
+	{ X86_VENDOR_INTEL, 0x0f44 },
+	{ X86_VENDOR_INTEL, 0x0f47 },
+	{ X86_VENDOR_INTEL, 0x0f48 },
+	{ X86_VENDOR_INTEL, 0x0f49 },
+	{ X86_VENDOR_INTEL, 0x0f4a },
+	{ X86_VENDOR_INTEL, 0x0f62 },
+	{ X86_VENDOR_INTEL, 0x0f64 },
+	{ X86_VENDOR_INTEL, 0x0f68 },
+/* For these, I'm not sure if we can read all 5 digits, 
+ * so I've included both possible IDs */
+	{ X86_VENDOR_INTEL, 0x10661 },
+	{ X86_VENDOR_INTEL, 0x10676 },
+	{ X86_VENDOR_INTEL, 0x0661 },
+	{ X86_VENDOR_INTEL, 0x0676 },
+	{ 0, 0 },
+};
+
+struct chip_operations cpu_intel_intel_generic_ops = {
+	CHIP_NAME("Intel CPU")
+};
Index: src/cpu/intel/intel_generic/chip.h
===================================================================
--- src/cpu/intel/intel_generic/chip.h	(revision 0)
+++ src/cpu/intel/intel_generic/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_intel_generic_ops;
+
+struct cpu_intel_intel_generic_config {
+};
Index: src/cpu/intel/socket_mPGA479M/Config.lb
===================================================================
--- src/cpu/intel/socket_mPGA479M/Config.lb	(revision 3036)
+++ src/cpu/intel/socket_mPGA479M/Config.lb	(working copy)
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mPGA479M.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
Index: src/cpu/intel/socket_mPGA479M/chip.h
===================================================================
--- src/cpu/intel/socket_mPGA479M/chip.h	(revision 3036)
+++ src/cpu/intel/socket_mPGA479M/chip.h	(working copy)
@@ -1,4 +0,0 @@
-extern struct chip_operations cpu_intel_socket_mPGA479M_ops;
-
-struct cpu_intel_socket_mPGA479M_config {
-};
Index: src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c
===================================================================
--- src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c	(revision 3036)
+++ src/cpu/intel/socket_mPGA479M/socket_mPGA479M.c	(working copy)
@@ -1,7 +0,0 @@
-#include <device/device.h>
-#include "chip.h"
-
-
-struct chip_operations cpu_intel_socket_mPGA479M_ops = {
-	CHIP_NAME("Socket mPGA479M CPU")
-};
Index: src/mainboard/a-trend/atc-6220/Config.lb
===================================================================
--- src/mainboard/a-trend/atc-6220/Config.lb	(revision 3036)
+++ src/mainboard/a-trend/atc-6220/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/gigabyte/ga-6bxc/Config.lb
===================================================================
--- src/mainboard/gigabyte/ga-6bxc/Config.lb	(revision 3036)
+++ src/mainboard/gigabyte/ga-6bxc/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/digitallogic/adl855pc/Config.lb
===================================================================
--- src/mainboard/digitallogic/adl855pc/Config.lb	(revision 3036)
+++ src/mainboard/digitallogic/adl855pc/Config.lb	(working copy)
@@ -184,7 +184,7 @@
 		end
 	end
 	device apic_cluster 0 on 
-		chip cpu/intel/socket_mPGA479M
+		chip cpu/intel/socket_479
 			device apic 0 on end
 		end
 	end
Index: src/mainboard/biostar/m6tba/Config.lb
===================================================================
--- src/mainboard/biostar/m6tba/Config.lb	(revision 3036)
+++ src/mainboard/biostar/m6tba/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/azza/pt-6ibd/Config.lb
===================================================================
--- src/mainboard/azza/pt-6ibd/Config.lb	(revision 3036)
+++ src/mainboard/azza/pt-6ibd/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/tyan/s1846/Config.lb
===================================================================
--- src/mainboard/tyan/s1846/Config.lb	(revision 3036)
+++ src/mainboard/tyan/s1846/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
===================================================================
--- src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	(revision 3036)
+++ src/mainboard/compaq/deskpro_en_sff_p600/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/msi/ms6178/Config.lb
===================================================================
--- src/mainboard/msi/ms6178/Config.lb	(revision 3036)
+++ src/mainboard/msi/ms6178/Config.lb	(working copy)
@@ -79,7 +79,7 @@
 
 chip northbridge/intel/i82810			# Northbridge
   device apic_cluster 0 on			# APIC cluster
-    chip cpu/intel/socket_PGA370		# CPU
+    chip cpu/intel/socket_370			# CPU
       device apic 0 on end			# APIC
     end
   end
Index: src/mainboard/asus/mew-am/Config.lb
===================================================================
--- src/mainboard/asus/mew-am/Config.lb	(revision 3036)
+++ src/mainboard/asus/mew-am/Config.lb	(working copy)
@@ -85,7 +85,7 @@
 # TODO: On-board graphics.
 chip northbridge/intel/i82810		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# CPU
+    chip cpu/intel/socket_370		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/asus/p2b/Config.lb
===================================================================
--- src/mainboard/asus/p2b/Config.lb	(revision 3036)
+++ src/mainboard/asus/p2b/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/asus/p2b-f/Config.lb
===================================================================
--- src/mainboard/asus/p2b-f/Config.lb	(revision 3036)
+++ src/mainboard/asus/p2b-f/Config.lb	(working copy)
@@ -82,7 +82,7 @@
 
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/asus/p3b-f/Config.lb
===================================================================
--- src/mainboard/asus/p3b-f/Config.lb	(revision 3036)
+++ src/mainboard/asus/p3b-f/Config.lb	(working copy)
@@ -83,7 +83,7 @@
 # TODO
 chip northbridge/intel/i440bx		# Northbridge
   device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+    chip cpu/intel/slot_1		# CPU
       device apic 0 on end		# APIC
     end
   end
Index: src/mainboard/asus/mew-vm/Config.lb
===================================================================
--- src/mainboard/asus/mew-vm/Config.lb	(revision 3036)
+++ src/mainboard/asus/mew-vm/Config.lb	(working copy)
@@ -176,7 +176,7 @@
 			device pci 1f.6 off end # AC'97 Modem (MC'97)
 		end
 	end
-	chip cpu/intel/socket_PGA370
+	chip cpu/intel/socket_370
 	end
 end
 
