With this set of changes, the lx target loads VSA and configures the PCI bus, 
with VSA operating correctly. This is tested with AMD's recently released 
new-model VSA code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.

Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.

Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.

Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the 
domain AND the PCI device, which is a mistake: can't scan from the 
PCI device too. 

Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.

Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error, since there are 
some no-pci devices in the tree now. For future: only complain about leftover
PCI devices ...

Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk. 

Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean to me, 
the way it went in. 

Index: mainboard/pcengines/alix1c/dts
===================================================================
--- mainboard/pcengines/alix1c/dts	(revision 570)
+++ mainboard/pcengines/alix1c/dts	(working copy)
@@ -25,11 +25,16 @@
 	cpus {
 		enabled;
 	};
+	apic {
+		/config/("northbridge/amd/geodelx/apic");
+		enabled;
+	};
 	domain0 {
-		/config/("northbridge/amd/geodelx/dts");
+		/config/("northbridge/amd/geodelx/domain");
 		enabled;
 		pcidomain = "0";
 		device0,0 {
+		/config/("northbridge/amd/geodelx/pci");
 			enabled;
 			pcipath = "1,0";
 		};
Index: device/device.c
===================================================================
--- device/device.c	(revision 570)
+++ device/device.c	(working copy)
@@ -67,6 +67,12 @@
 static struct device devs[MAX_DEVICES];
 
 /**
+ * the number of devices that have been allocated 
+ */
+static int devcnt;
+
+
+/**
  * The device creator.
  * 
  * reserves a piece of memory for a device in the tree
@@ -76,9 +82,9 @@
 
 static struct device *new_device(void)
 {
-	static int devcnt=0;
 	devcnt++;
 
+	printk(BIOS_SPEW, "%s: devcnt %d\n", __FUNCTION__, devcnt);
 	/* Should we really die here? */
 	if (devcnt>=MAX_DEVICES) {
 		die("Too many devices. Increase MAX_DEVICES\n");
@@ -155,6 +161,7 @@
 			dev->ops = c->ops;
 		last_dev_p = &dev->next;
 	}
+	devcnt = 0;
 }
 
 /**
Index: device/pci_device.c
===================================================================
--- device/pci_device.c	(revision 570)
+++ device/pci_device.c	(working copy)
@@ -1136,9 +1136,9 @@
 	if (old_devices) {
 		struct device *left;
 		for (left = old_devices; left; left = left->sibling) {
-			printk(BIOS_ERR, "%s\n", dev_path(left));
+			printk(BIOS_SPEW, "%s\n", left->dtsname);
 		}
-		die("PCI: Left over static devices.\n");
+		banner(BIOS_SPEW, "PCI: Left over static devices.\n");
 	}
 
 	/* For all children that implement scan_bus() (i.e. bridges)
Index: northbridge/amd/geodelx/domain
===================================================================
--- northbridge/amd/geodelx/domain	(revision 0)
+++ northbridge/amd/geodelx/domain	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	constructor = "geodelx_north_constructors";
+	domainid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Index: northbridge/amd/geodelx/geodelx.c
===================================================================
--- northbridge/amd/geodelx/geodelx.c	(revision 570)
+++ northbridge/amd/geodelx/geodelx.c	(working copy)
@@ -380,9 +380,12 @@
 };
 
 /** Operations for when the northbridge is running a PCI device. */
+/** Note that phase3 scan is done in the domain, 
+ * and MUST NOT be done here too 
+ */
 static struct device_operations geodelx_pci_ops = {
 	.constructor			= default_device_constructor,
-	.phase3_scan			= pci_domain_scan_bus,
+	.phase3_scan			= 0,
 	.phase4_read_resources		= pci_domain_read_resources,
 	.phase4_set_resources		= geodelx_northbridge_set_resources,
 	.phase5_enable_resources	= enable_childrens_resources,
Index: northbridge/amd/geodelx/pci
===================================================================
--- northbridge/amd/geodelx/pci	(revision 0)
+++ northbridge/amd/geodelx/pci	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	constructor = "geodelx_north_constructors";
+	pciid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Index: northbridge/amd/geodelx/apic
===================================================================
--- northbridge/amd/geodelx/apic	(revision 0)
+++ northbridge/amd/geodelx/apic	(revision 0)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	constructor = "geodelx_north_constructors";
+	apicid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Index: util/dtc/flattree.c
===================================================================
--- util/dtc/flattree.c	(revision 570)
+++ util/dtc/flattree.c	(working copy)
@@ -551,6 +551,10 @@
 				fprintf(f, "\t.id = {.type=DEVICE_ID_PCI,.u={.pci={ %s }}},\n", 
 					prop->val.val);
 			}
+			if (streq(prop->name, "apicid")){
+				fprintf(f, "\t.id = {.type=DEVICE_ID_APIC,.u={.pci={ %s }}},\n", 
+					prop->val.val);
+			}
 		}
 	}
 	/* Process the properties specified in the mainboard dts. 
