Cache the ROM to speed up stage2 and payload decompression.

Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.

Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.

Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_p
re_payload().

"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI.  The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI  bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c
===================================================================
--- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c	2008-02-05 19:25:22.000000000 -0700
@@ -658,7 +658,8 @@
 #define SYSMEM_RCONF_WRITETHROUGH	8
 #define DEVRC_RCONF_DEFAULT		0x21
 #define ROMBASE_RCONF_DEFAULT		0xFFFC0000
-#define ROMRC_RCONF_DEFAULT		0x25
+#define ROMRC_RCONF_SAFE		0x25
+#define ROMRC_RCONF_DEFAULT		0x04
 
 /**
  * TODO.
@@ -848,3 +849,15 @@
 
 	printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__);
 }
+
+void geode_pre_payload(void)
+{
+	struct msr msr;
+
+	/* Set ROM cache properties for runtime. */
+	msr = rdmsr(CPU_RCONF_DEFAULT);
+	msr.hi &= ~(0xFF << 24);        	// clear ROMRC
+	msr.hi |= ROMRC_RCONF_SAFE << 24;	// set WS, CD, WP
+	wrmsr(CPU_RCONF_DEFAULT, msr);
+}
+
Index: coreboot-v3/mainboard/adl/msm800sev/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/adl/msm800sev/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/mainboard/adl/msm800sev/stage1.c	2008-02-05 19:21:35.000000000 -0700
@@ -53,3 +53,9 @@
 	cs5536_disable_internal_uart();
 	w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
 }
+
+void mainboard_pre_payload(void)
+{
+	geode_pre_payload();
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Index: coreboot-v3/mainboard/amd/norwich/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/amd/norwich/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/mainboard/amd/norwich/stage1.c	2008-02-05 19:22:01.000000000 -0700
@@ -46,3 +46,9 @@
 	 */
 	cs5536_setup_onchipuart();
 }
+
+void mainboard_pre_payload(void)
+{
+	geode_pre_payload();
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Index: coreboot-v3/mainboard/artecgroup/dbe61/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/artecgroup/dbe61/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/mainboard/artecgroup/dbe61/stage1.c	2008-02-05 19:21:18.000000000 -0700
@@ -61,3 +61,9 @@
 	 */
 	cs5536_setup_onchipuart();
 }
+
+void mainboard_pre_payload(void)
+{
+	geode_pre_payload();
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Index: coreboot-v3/mainboard/emulation/qemu-x86/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/emulation/qemu-x86/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/mainboard/emulation/qemu-x86/stage1.c	2008-02-05 19:06:23.000000000 -0700
@@ -30,3 +30,8 @@
 void disable_car(void)
 {
 }
+
+
+void pre_payload(void)
+{
+}
Index: coreboot-v3/mainboard/pcengines/alix1c/stage1.c
===================================================================
--- coreboot-v3.orig/mainboard/pcengines/alix1c/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/mainboard/pcengines/alix1c/stage1.c	2008-02-05 19:22:36.000000000 -0700
@@ -49,3 +49,9 @@
 	w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
 
 }
+
+void mainboard_pre_payload(void)
+{
+	geode_pre_payload();
+	banner(BIOS_DEBUG, "mainboard_pre_payload: done");
+}
Index: coreboot-v3/arch/x86/stage1.c
===================================================================
--- coreboot-v3.orig/arch/x86/stage1.c	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/arch/x86/stage1.c	2008-02-05 19:06:23.000000000 -0700
@@ -37,6 +37,7 @@
 void die(const char *msg);
 void hardware_stage1(void);
 void disable_car(void);
+void mainboard_pre_payload(void);
 
 static void stop_ap(void)
 {
@@ -177,11 +178,13 @@
 		legacy(&archive, "normal/payload", (void *)UNCOMPRESS_AREA, mem);
 
 	entry = load_file_segments(&archive, "normal/payload");
-	if (entry != (void*)-1)
+	if (entry != (void*)-1) {
+		/* Final coreboot call before handing off to the payload. */
+		mainboard_pre_payload();
 		run_address(entry);
-	else
+	} else {
 		die("FATAL: No usable payload found.\n");
-
+	}
 	die ("FATAL: Last stage returned to coreboot.\n");
 }
 
Index: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3.orig/arch/x86/Makefile	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/arch/x86/Makefile	2008-02-05 19:06:23.000000000 -0700
@@ -157,7 +157,7 @@
 	$(Q)$(OBJCOPY) --prefix-symbols=stage0_ $(obj)/stage0.o $(obj)/stage0-prefixed.o
 
 	$(Q)printf "  TEST    $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)test `wc -c < $(obj)/stage0.init` -gt 16128 && \
+	$(Q)test `wc -c < $(obj)/stage0.init` -gt 20224 && \
 		printf "Error. Bootblock got too big.\n" || true
 	$(Q)printf "  NM      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(NM) $(obj)/stage0.o | sort -u > $(obj)/stage0.init.map
Index: coreboot-v3/arch/x86/ldscript.ld
===================================================================
--- coreboot-v3.orig/arch/x86/ldscript.ld	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/arch/x86/ldscript.ld	2008-02-05 19:06:23.000000000 -0700
@@ -28,7 +28,7 @@
 TARGET(binary)
 SECTIONS
 {
-	. = 0xffffc000 + 256; /* leave space for vpd */
+	. = 0xffffb000 + 256; /* leave space for vpd */
 
 	.stage0_1 . : {
 		_stage0_1 = .;
Index: coreboot-v3/util/lar/lar.h
===================================================================
--- coreboot-v3.orig/util/lar/lar.h	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/util/lar/lar.h	2008-02-05 19:06:23.000000000 -0700
@@ -52,7 +52,7 @@
 
 #define MAGIC "LARCHIVE"
 #define MAX_PATHLEN 1024
-#define BOOTBLOCK_SIZE 16384
+#define BOOTBLOCK_SIZE 20480
 
 #define BOOTBLOCK_NAME "bootblock"
 #define BOOTBLOCK_NAME_LEN 16
Index: coreboot-v3/include/arch/x86/amd_geodelx.h
===================================================================
--- coreboot-v3.orig/include/arch/x86/amd_geodelx.h	2008-02-05 19:05:52.000000000 -0700
+++ coreboot-v3/include/arch/x86/amd_geodelx.h	2008-02-05 19:06:23.000000000 -0700
@@ -1269,6 +1269,7 @@
 void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1);
 void system_preinit(void);
 void msr_init(void);
+void geode_pre_payload(void);
 #endif
 
 #endif
