Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Index: src/cpu/intel/microcode/microcode.c
===================================================================
--- src/cpu/intel/microcode/microcode.c	(revision 3111)
+++ src/cpu/intel/microcode/microcode.c	(working copy)
@@ -33,7 +33,6 @@
 	 */
 	msr_t msr;
 	__asm__ volatile (
-		"wrmsr\n\t"
 		"xorl %%eax, %%eax\n\t"
 		"xorl %%edx, %%edx\n\t"
 		"movl $0x8b, %%ecx\n\t"
@@ -60,7 +59,7 @@
 	char *c;
 	msr_t msr;
 	
-	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	/* cpuid sets msr 0x8B if a microcode update has been loaded. */
 	msr.lo = 0;
 	msr.hi = 0;
 	wrmsr(0x8B, msr);