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<P><FONT SIZE=2 FACE="Arial">Hi, all,</FONT>
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<P><FONT SIZE=2 FACE="Arial">I am a little confused by PIC, APIC, XAPIC and XIOAPIC.</FONT>
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<P><FONT SIZE=2 FACE="Arial">In LB stage, only PIC mode is applied, isn't it? However, I remember some people of LB community told me there was no ISR except the debug ISR during LB. So does this mean it totally unnecessary to setup PIC via C00h/C001h IO port in LB?</FONT></P>
<P><FONT SIZE=2 FACE="Arial">APIC is setup only after OS runs and gets the interrupt routing from MPTable or ACPI table, is it correct? Then, what difference between APIC and XAPIC? Some documents say APIC has MMIO space registers at FEC00000h while XAPIC has PCI configuration space registers. But some documents seems to refer the same controller by APIC and XAPIC.</FONT></P>
<P><FONT SIZE=2 FACE="Arial">And XAPIC and XIOAPIC are the same things, aren’t they?</FONT>
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<P><FONT SIZE=2 FACE="Arial">Please help me out, I am completely confused by these terms.</FONT>
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<P><SPAN LANG="en-us"><FONT FACE="Arial">Best Regards</FONT></SPAN><SPAN LANG="zh-cn"></SPAN>
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<P><SPAN LANG="zh-cn"><FONT FACE="宋体">丰立波</FONT></SPAN><SPAN LANG="en-us"><FONT FACE="Arial"> Feng Libo @ AMD Ext</FONT></SPAN><SPAN LANG="zh-cn"><FONT FACE="Arial">:</FONT></SPAN><SPAN LANG="en-us"><FONT FACE="Arial"> 20906</FONT></SPAN>
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