This fix moves the power button management to stage 2. Power button is 
now default disabled, which is the safest setting. Power button is 
controlled by the power_button in the cs5536 dts. "1" means enable.

This patch also adds (we hope temporarily!) a function in stage1 to 
setup COM2 as COM1. We're working around this but for now it's needed. 
This function is from v2. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Index: southbridge/amd/cs5536/stage1.c
===================================================================
--- southbridge/amd/cs5536/stage1.c	(revision 632)
+++ southbridge/amd/cs5536/stage1.c	(working copy)
@@ -113,23 +113,6 @@
 }
 
 /**
- * Power button setup.
- *
- * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
- * controls all voltage rails except Vstandby & Vmem. We need to enable
- * OUT_AUX1 and OUTPUT_ENABLE in this order.
- *
- * If GPIO24 is not enabled then soft-off will not work.
- */
-static void cs5536_setup_power_button(void)
-{
-	/* TODO: Should be a #define? */
-	outl(0x40020000, PMS_IO_BASE + 0x40);
-	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
-	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
-}
-
-/**
  * Set the various GPIOs.
  *
  * An unknown question at this point is how general this is to all mainboards.
@@ -239,6 +222,40 @@
 	wrmsr(MDD_UART1_CONF, msr);
 }
 
+void cs5536_setup_onchipuart2(void)
+{
+	struct msr msr;
+
+	/* GPIO4 - UART2_TX */
+	/* Set: Output Enable  (0x4) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
+	/* Set: OUTAUX1 Select (0x10) */
+	outl(GPIOL_4_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT);
+	/* GPIO4 - UART2_RX */
+	/* Set: Input Enable   (0x20) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	/* Set: INAUX1 Select  (0x34) */
+	outl(GPIOL_3_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/* Set: GPIO 3 + 3 Pull Up  (0x18) */
+	outl(GPIOL_3_SET | GPIOL_4_SET, GPIO_IO_BASE + GPIOL_PULLUP_ENABLE);
+
+	/* set address to 3F8 */
+	msr = rdmsr(MDD_LEG_IO);
+	msr.lo |= 0x7 << 20;
+	wrmsr(MDD_LEG_IO, msr);
+
+	/* Bit 1 = DEVEN (device enable)
+	 * Bit 4 = EN_BANKS (allow access to the upper banks
+	 */
+	msr.lo = (1 << 4) | (1 << 1);
+	msr.hi = 0;
+
+	/* enable COM2 */
+	wrmsr(MDD_UART2_CONF, msr);
+}
+
+
 /**
  * Board setup.
  *
@@ -279,5 +296,4 @@
 	cs5536_setup_iobase();
 	cs5536_setup_smbus_gpio();
 	/* cs5536_enable_smbus(); -- Leave this out for now. */
-	cs5536_setup_power_button();
 }
Index: southbridge/amd/cs5536/cs5536.c
===================================================================
--- southbridge/amd/cs5536/cs5536.c	(revision 632)
+++ southbridge/amd/cs5536/cs5536.c	(working copy)
@@ -89,6 +89,26 @@
 };
 
 /**
+ * Power button setup.
+ *
+ * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which
+ * controls all voltage rails except Vstandby & Vmem. We need to enable
+ * OUT_AUX1 and OUTPUT_ENABLE in this order.
+ *
+ * @param sb The southbridge config structure. 
+ * If GPIO24 is not enabled then soft-off will not work.
+ */
+static void cs5536_setup_power_button(struct southbridge_amd_cs5536_dts_config *sb )
+{
+	if (!sb->power_button)
+		return;
+	/* TODO: Should be a #define? */
+	outl(0x40020000, PMS_IO_BASE + 0x40);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
+	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
+}
+
+/**
  * Program ACPI LBAR and initialize ACPI registers.
  */
 static void pm_chipset_init(void)
@@ -617,6 +637,8 @@
 	if (sb->enable_ide)
 		ide_init(dev);
 
+	cs5536_setup_power_button(sb);
+
 	printk(BIOS_SPEW, "cs5536: %s() Exit\n", __FUNCTION__);
 }
 
Index: southbridge/amd/cs5536/dts
===================================================================
--- southbridge/amd/cs5536/dts	(revision 632)
+++ southbridge/amd/cs5536/dts	(working copy)
@@ -56,4 +56,12 @@
 	com2_enable = "0";
 	com2_address = "0x2f8";
 	com2_irq = "3";
+
+	/* enable/disable power button. On systems with no power switch, 
+	 * one usually does not want the button enabled. Example: 
+	 * Alix1C, dbe62, dbe61. If you enable this, and the power is 
+	 * hard-wired, the board will turn off after 4 seconds, which is 
+	 * probably not what you want. 
+	 */
+	power_button = "0";
 };
Index: southbridge/amd/cs5536/cs5536.h
===================================================================
--- southbridge/amd/cs5536/cs5536.h	(revision 632)
+++ southbridge/amd/cs5536/cs5536.h	(working copy)
@@ -444,6 +444,7 @@
 /* Function prototypes */
 void cs5536_disable_internal_uart(void);
 void cs5536_setup_onchipuart(void);
+void cs5536_setup_onchipuart2(void);
 void cs5536_stage1(void);
 
 #endif /* SOUTHBRIDGE_AMD_CS5536_CS5536_H */
Index: mainboard/artecgroup/dbe62/stage1.c
===================================================================
--- mainboard/artecgroup/dbe62/stage1.c	(revision 632)
+++ mainboard/artecgroup/dbe62/stage1.c	(working copy)
@@ -58,7 +58,7 @@
 	 * NOTE: Must do this AFTER the early_setup! It is counting on some
 	 * early MSR setup for the CS5536.
 	 */
-	cs5536_setup_onchipuart();
+	cs5536_setup_onchipuart2();
 }
 
 void mainboard_pre_payload(void)
Index: mainboard/artecgroup/dbe62/dts
===================================================================
--- mainboard/artecgroup/dbe62/dts	(revision 632)
+++ mainboard/artecgroup/dbe62/dts	(working copy)
@@ -43,6 +43,12 @@
 			/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. 
 			 * See virtual PIC spec. */
 			enable_gpio_int_route = "0x0D0C0700";
+			/* we use com2 since that is on the dongle */
+			com2_enable = "1";
+			/* Set com2 address to be COM1 */
+			com2_address = "0x3f8";
+			/* Set com2 IRQ to be what is usually COM1 */
+			com2_irq = "4";
 		};
 	};
 };
