diff -Nru coreboot-v2-3132/src/mainboard/advantech/pcm-5820/Options.lb coreboot-v2-3132-remove/src/mainboard/advantech/pcm-5820/Options.lb
--- coreboot-v2-3132/src/mainboard/advantech/pcm-5820/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/advantech/pcm-5820/Options.lb	2008-03-14 15:43:24.000000000 +0500
@@ -63,6 +63,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -75,6 +76,7 @@
 default ROM_SIZE = 256 * 1024
 default HAVE_PIRQ_TABLE = 1
 default IRQ_SLOT_COUNT = 0		# Override this in targets/*/Config.lb.
+default PIRQ_ROUTE = 1
 default HAVE_FALLBACK_BOOT = 1
 default HAVE_MP_TABLE = 0
 default HAVE_HARD_RESET = 0
diff -Nru coreboot-v2-3132/src/mainboard/amd/db800/irq_tables.c coreboot-v2-3132-remove/src/mainboard/amd/db800/irq_tables.c
--- coreboot-v2-3132/src/mainboard/amd/db800/irq_tables.c	2008-01-18 15:35:56.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/amd/db800/irq_tables.c	2008-03-14 15:28:12.000000000 +0500
@@ -65,42 +65,6 @@
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-	int i, j, k, num_entries;
-	unsigned char pirq[4];
-	uint16_t chipset_irq_map;
-	uint32_t pciAddr, pirtable_end;
-	struct irq_routing_table *pirq_tbl;
-
-	pirtable_end = copy_pirq_routing_table(addr);
-
-	/* Set up chipset IRQ steering. */
-	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
-	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
-		     chipset_irq_map);
-	outl(pciAddr & ~3, 0xCF8);
-	outl(chipset_irq_map, 0xCFC);
-
-	pirq_tbl = (struct irq_routing_table *)(addr);
-	num_entries = (pirq_tbl->size - 32) / 16;
-
-	/* Set PCI IRQs. */
-	for (i = 0; i < num_entries; i++) {
-		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
-			     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-		for (j = 0; j < 4; j++) {
-			printk_debug("INT: %c bitmap: %x ", 'A' + j,
-				     pirq_tbl->slots[i].irq[j].bitmap);
-			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ;	/* Finds lsb in bitmap to IRQ#. */
-			pirq[j] = k;
-			printk_debug("PIRQ: %d\n", k);
-		}
-
-		/* Bus, device, slots IRQs for {A,B,C,D}. */
-		pci_assign_irqs(pirq_tbl->slots[i].bus,
-				pirq_tbl->slots[i].devfn >> 3, pirq);
-	}
-
 	/* Put the PIR table in memory and checksum. */
-	return pirtable_end;
+	return 	copy_pirq_routing_table(addr);
 }
diff -Nru coreboot-v2-3132/src/mainboard/amd/db800/Options.lb coreboot-v2-3132-remove/src/mainboard/amd/db800/Options.lb
--- coreboot-v2-3132/src/mainboard/amd/db800/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/amd/db800/Options.lb	2008-03-14 15:38:15.000000000 +0500
@@ -48,6 +48,7 @@
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -84,6 +85,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=4
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/amd/norwich/irq_tables.c coreboot-v2-3132-remove/src/mainboard/amd/norwich/irq_tables.c
--- coreboot-v2-3132/src/mainboard/amd/norwich/irq_tables.c	2008-01-18 15:35:56.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/amd/norwich/irq_tables.c	2008-03-14 15:28:12.000000000 +0500
@@ -67,42 +67,6 @@
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-	int i, j, k, num_entries;
-	unsigned char pirq[4];
-	uint16_t chipset_irq_map;
-	uint32_t pciAddr, pirtable_end;
-	struct irq_routing_table *pirq_tbl;
-
-	pirtable_end = copy_pirq_routing_table(addr);
-
-	/* Set up chipset IRQ steering. */
-	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
-	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
-		     chipset_irq_map);
-	outl(pciAddr & ~3, 0xCF8);
-	outl(chipset_irq_map, 0xCFC);
-
-	pirq_tbl = (struct irq_routing_table *)(addr);
-	num_entries = (pirq_tbl->size - 32) / 16;
-
-	/* Set PCI IRQs. */
-	for (i = 0; i < num_entries; i++) {
-		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
-			     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-		for (j = 0; j < 4; j++) {
-			printk_debug("INT: %c bitmap: %x ", 'A' + j,
-				     pirq_tbl->slots[i].irq[j].bitmap);
-			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ;	/* Finds lsb in bitmap to IRQ#. */
-			pirq[j] = k;
-			printk_debug("PIRQ: %d\n", k);
-		}
-
-		/* Bus, device, slots IRQs for {A,B,C,D}. */
-		pci_assign_irqs(pirq_tbl->slots[i].bus,
-				pirq_tbl->slots[i].devfn >> 3, pirq);
-	}
-
 	/* Put the PIR table in memory and checksum. */
-	return pirtable_end;
+	return 	copy_pirq_routing_table(addr);
 }
diff -Nru coreboot-v2-3132/src/mainboard/amd/norwich/Options.lb coreboot-v2-3132-remove/src/mainboard/amd/norwich/Options.lb
--- coreboot-v2-3132/src/mainboard/amd/norwich/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/amd/norwich/Options.lb	2008-03-14 15:38:23.000000000 +0500
@@ -48,6 +48,7 @@
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -84,6 +85,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/artecgroup/dbe61/irq_tables.c coreboot-v2-3132-remove/src/mainboard/artecgroup/dbe61/irq_tables.c
--- coreboot-v2-3132/src/mainboard/artecgroup/dbe61/irq_tables.c	2008-01-18 15:35:56.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/artecgroup/dbe61/irq_tables.c	2008-03-14 15:28:12.000000000 +0500
@@ -64,42 +64,6 @@
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-	int i, j, k, num_entries;
-	unsigned char pirq[4];
-	uint16_t chipset_irq_map;
-	uint32_t pciAddr, pirtable_end;
-	struct irq_routing_table *pirq_tbl;
-
-	pirtable_end = copy_pirq_routing_table(addr);
-
-	/* Set up chipset IRQ steering. */
-	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
-	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
-		     chipset_irq_map);
-	outl(pciAddr & ~3, 0xCF8);
-	outl(chipset_irq_map, 0xCFC);
-
-	pirq_tbl = (struct irq_routing_table *)(addr);
-	num_entries = (pirq_tbl->size - 32) / 16;
-
-	/* Set PCI IRQs. */
-	for (i = 0; i < num_entries; i++) {
-		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
-			     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-		for (j = 0; j < 4; j++) {
-			printk_debug("INT: %c bitmap: %x ", 'A' + j,
-				     pirq_tbl->slots[i].irq[j].bitmap);
-			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ;	/* Finds lsb in bitmap to IRQ#. */
-			pirq[j] = k;
-			printk_debug("PIRQ: %d\n", k);
-		}
-
-		/* Bus, device, slots IRQs for {A,B,C,D}. */
-		pci_assign_irqs(pirq_tbl->slots[i].bus,
-				pirq_tbl->slots[i].devfn >> 3, pirq);
-	}
-
 	/* Put the PIR table in memory and checksum. */
-	return pirtable_end;
-}
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+	return 	copy_pirq_routing_table(addr);
+}
diff -Nru coreboot-v2-3132/src/mainboard/artecgroup/dbe61/Options.lb coreboot-v2-3132-remove/src/mainboard/artecgroup/dbe61/Options.lb
--- coreboot-v2-3132/src/mainboard/artecgroup/dbe61/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/artecgroup/dbe61/Options.lb	2008-03-14 15:38:42.000000000 +0500
@@ -48,6 +48,7 @@
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -84,7 +85,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=3
-
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/asi/mb_5blmp/Options.lb coreboot-v2-3132-remove/src/mainboard/asi/mb_5blmp/Options.lb
--- coreboot-v2-3132/src/mainboard/asi/mb_5blmp/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/asi/mb_5blmp/Options.lb	2008-03-14 15:44:04.000000000 +0500
@@ -42,7 +42,7 @@
 # uses CONFIG_CONSOLE_VGA
 # uses CONFIG_PCI_ROM_RUN
 uses CONFIG_VIDEO_MB
-
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE = 256 * 1024
@@ -71,6 +71,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=5        # TODO?
+default PIRQ_ROUTE=1
 
 ##
 ## Build code to export a CMOS option table
diff -Nru coreboot-v2-3132/src/mainboard/axus/tc320/Options.lb coreboot-v2-3132-remove/src/mainboard/axus/tc320/Options.lb
--- coreboot-v2-3132/src/mainboard/axus/tc320/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/axus/tc320/Options.lb	2008-03-14 15:44:50.000000000 +0500
@@ -63,6 +63,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default HAVE_PIRQ_TABLE = 1
 default IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
 default HAVE_OPTION_TABLE = 0
 default ROM_IMAGE_SIZE = 64 * 1024
 default FALLBACK_SIZE = 128 * 1024
diff -Nru coreboot-v2-3132/src/mainboard/bcom/winnet100/Options.lb coreboot-v2-3132-remove/src/mainboard/bcom/winnet100/Options.lb
--- coreboot-v2-3132/src/mainboard/bcom/winnet100/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/bcom/winnet100/Options.lb	2008-03-14 15:45:30.000000000 +0500
@@ -63,6 +63,7 @@
 uses CONFIG_SPLASH_GRAPHIC
 uses CONFIG_GX1_VIDEO
 uses CONFIG_GX1_VIDEOMODE
+uses PIRQ_ROUTE
 
 ## Enable VGA with a splash screen (only 640x480 to run on most monitors).
 ## We want to support up to 1024x768@16 so we need 2MiB video memory.
@@ -82,6 +83,7 @@
 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
 default HAVE_PIRQ_TABLE = 1
 default IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
+default PIRQ_ROUTE = 1
 default HAVE_OPTION_TABLE = 0
 default ROM_IMAGE_SIZE = 64 * 1024
 default FALLBACK_SIZE = 128 * 1024
diff -Nru coreboot-v2-3132/src/mainboard/digitallogic/msm800sev/irq_tables.c coreboot-v2-3132-remove/src/mainboard/digitallogic/msm800sev/irq_tables.c
--- coreboot-v2-3132/src/mainboard/digitallogic/msm800sev/irq_tables.c	2008-01-18 15:35:56.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/digitallogic/msm800sev/irq_tables.c	2008-03-14 15:28:12.000000000 +0500
@@ -70,38 +70,9 @@
 };
 
 
-unsigned long write_pirq_routing_table(unsigned long addr){
-       int i, j, k, num_entries;
-       unsigned int pirq[4];
-       uint16_t chipset_irq_map;
-       uint32_t pciAddr, pirtable_end;
-       struct irq_routing_table *pirq_tbl;
-
-       pirtable_end = copy_pirq_routing_table(addr);
-
-       /* Set up chipset IRQ steering */
-       pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-       chipset_irq_map = (11 << 12 | 10 << 8 | 11 << 4 | 10);
-       printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr, chipset_irq_map);
-       outl(pciAddr & ~3, 0xCF8);
-       outl(chipset_irq_map, 0xCFC);
-
-       pirq_tbl = (struct irq_routing_table *)(addr);
-       num_entries = (pirq_tbl->size - 32)/16;
-
-       /* Set PCI IRQs */
-       for (i=0; i < num_entries; i++){
-               printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i, pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-               for (j = 0; j < 4; j++){
-               printk_debug("INT: %c bitmap: %x ", 'A'+j, pirq_tbl->slots[i].irq[j].bitmap);
-                       for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++); /* finds lsb in bitmap to IRQ# */
-                       pirq[j] = k;
-                       printk_debug("PIRQ: %d\n", k);
-               }
-               pci_assign_irqs(pirq_tbl->slots[i].bus, pirq_tbl->slots[i].devfn, pirq);        /* bus, device, slots IRQs for {A,B,C,D} */
-       }
-
-       /* put the PIR table in memory and checksum */
-       return pirtable_end;
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	/* Put the PIR table in memory and checksum. */
+	return 	copy_pirq_routing_table(addr);
 }
 
diff -Nru coreboot-v2-3132/src/mainboard/digitallogic/msm800sev/Options.lb coreboot-v2-3132-remove/src/mainboard/digitallogic/msm800sev/Options.lb
--- coreboot-v2-3132/src/mainboard/digitallogic/msm800sev/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/digitallogic/msm800sev/Options.lb	2008-03-14 15:39:25.000000000 +0500
@@ -48,6 +48,7 @@
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -84,6 +85,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=6
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/eaglelion/5bcm/Options.lb coreboot-v2-3132-remove/src/mainboard/eaglelion/5bcm/Options.lb
--- coreboot-v2-3132/src/mainboard/eaglelion/5bcm/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/eaglelion/5bcm/Options.lb	2008-03-14 15:46:00.000000000 +0500
@@ -42,6 +42,7 @@
 uses CONFIG_UDELAY_TSC
 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
 uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -75,6 +76,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/iei/juki-511p/Options.lb coreboot-v2-3132-remove/src/mainboard/iei/juki-511p/Options.lb
--- coreboot-v2-3132/src/mainboard/iei/juki-511p/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/iei/juki-511p/Options.lb	2008-03-14 15:46:48.000000000 +0500
@@ -43,6 +43,7 @@
 uses TTYS0_BASE
 uses TTYS0_LCS
 uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -72,6 +73,7 @@
 ##
 default HAVE_PIRQ_TABLE=0
 default IRQ_SLOT_COUNT=2
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/iei/nova4899r/Options.lb coreboot-v2-3132-remove/src/mainboard/iei/nova4899r/Options.lb
--- coreboot-v2-3132/src/mainboard/iei/nova4899r/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/iei/nova4899r/Options.lb	2008-03-14 15:46:27.000000000 +0500
@@ -45,6 +45,7 @@
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_VIDEO_MB
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 256*1024
@@ -82,6 +83,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=7
+default PIRQ_ROUTE=1
 #object irq_tables.o
 
 ##
diff -Nru coreboot-v2-3132/src/mainboard/pcengines/alix1c/irq_tables.c coreboot-v2-3132-remove/src/mainboard/pcengines/alix1c/irq_tables.c
--- coreboot-v2-3132/src/mainboard/pcengines/alix1c/irq_tables.c	2008-01-18 15:35:56.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/pcengines/alix1c/irq_tables.c	2008-03-14 15:40:35.000000000 +0500
@@ -106,46 +106,6 @@
 
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-	int i, j, k, num_entries;
-	unsigned char pirq[4];
-	uint16_t chipset_irq_map;
-	uint32_t pciAddr, pirtable_end;
-	struct irq_routing_table *pirq_tbl;
-
-	pirtable_end = copy_pirq_routing_table(addr);
-
-	/* Set up chipset IRQ steering. */
-	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
-	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
-	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
-		     chipset_irq_map);
-	outl(pciAddr & ~3, 0xCF8);
-	outl(chipset_irq_map, 0xCFC);
-
-	pirq_tbl = (struct irq_routing_table *) (addr);
-	num_entries = (pirq_tbl->size - 32) / 16;
-
-	/* Set PCI IRQs. */
-	for (i = 0; i < num_entries; i++) {
-		printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
-			     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
-		for (j = 0; j < 4; j++) {
-			printk_debug("INT: %c bitmap: %x ", 'A' + j,
-				     pirq_tbl->slots[i].irq[j].bitmap);
-			/* Finds lsb in bitmap to IRQ#. */
-			for (k = 0; 
-			     (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) 
-				     && (pirq_tbl->slots[i].irq[j].bitmap != 0);
-			     k++);
-			pirq[j] = k;
-			printk_debug("PIRQ: %d\n", k);
-		}
-
-		/* Bus, device, slots IRQs for {A,B,C,D}. */
-		pci_assign_irqs(pirq_tbl->slots[i].bus,
-				pirq_tbl->slots[i].devfn >> 3, pirq);
-	}
-
 	/* Put the PIR table in memory and checksum. */
-	return pirtable_end;
+	return 	copy_pirq_routing_table(addr);
 }
diff -Nru coreboot-v2-3132/src/mainboard/pcengines/alix1c/Options.lb coreboot-v2-3132-remove/src/mainboard/pcengines/alix1c/Options.lb
--- coreboot-v2-3132/src/mainboard/pcengines/alix1c/Options.lb	2008-01-18 20:08:58.000000000 +0500
+++ coreboot-v2-3132-remove/src/mainboard/pcengines/alix1c/Options.lb	2008-03-14 15:39:01.000000000 +0500
@@ -68,6 +68,7 @@
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
+uses PIRQ_ROUTE
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 default ROM_SIZE  = 512*1024
@@ -104,7 +105,7 @@
 ##
 default HAVE_PIRQ_TABLE=1
 default IRQ_SLOT_COUNT=5
-
+default PIRQ_ROUTE=1
 ##
 ## Build code to export a CMOS option table
 ##
