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<br>i have a board working with this chip and i have the docs<br>it's a quite old tree and i needed some patches to get it working i will<br>put it online as soon as i find the backup<br>afaik the docs are public ...<br><br>Reinder<br><br>> On Sat, Mar 22, 2008 at 11:43 PM, Jacek Chruscik <mercury@wirebros.com <br>> <mailto:mercury@wirebros.com>> wrote:<br>> <br>> Hi,<br>> <br>> Does anybody know how to deal with this southbridge: VIA VT82c686<br>> I'm trying to port coreboot v.2 for FIC FR33E motherboard, but this<br>> southbridge has the superio built in.<br>> I don't have any datasheet for this chip.<br>> coreboot-v2 has no option for such superio, and all I need to do is to<br>> initialize serial port.<br>> As a base I used via-epia code. The north is vt8601.<br>> <br>> So far I generated PIRQ table, modified auto.c to recognize correct<br>> southbridge, modified config.lb <http://config.lb> to initialize<br>> devices.<br>> <br>> There is serial init function in vt82c686 source:<br>> <br>> static void vt82c686_enable_serial(device_t dev, unsigned iobase)<br>> .....<br>> <br>> but it requires 2 parameters, which I don't have (called as early<br>> serial init from auto.c):<br>> <br>> <br>> dev is the ISA/LPC device in the southbridge, with device ID 0x0686. <br>> iobase is the serial io base, usually 0x3f8 for the first port, and <br>> 0x2f8 for the second one (although I doubt the second one will work, <br>> without some modification).<br>> <br>> -Corey<br>> <br><br><br><br /><hr />Express yourself instantly with MSN Messenger! <a href='http://clk.atdmt.com/AVE/go/onm00200471ave/direct/01/' target='_new'>MSN Messenger</a></body>
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