---------- Forwarded message ----------<br><div class="gmail_quote">From: <b class="gmail_sendername">Jake Peavy</b> <<a href="mailto:djstunks@gmail.com">djstunks@gmail.com</a>><br>Date: Wed, Mar 26, 2008 at 9:19 PM<br>
Subject: Re: [coreboot] MIPS Yamon replacement?<br>To: Carl-Daniel Hailfinger <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net">c-d.hailfinger.devel.2006@gmx.net</a>><br><br>Forgot the list... <br><br><div class="Ih2E3d">
On 3/26/08, <b class="gmail_sendername">Carl-Daniel Hailfinger</b> <<a href="mailto:c-d.hailfinger.devel.2006@gmx.net" target="_blank">c-d.hailfinger.devel.2006@gmx.net</a>> wrote:</div><div><span class="gmail_quote"></span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="Ih2E3d">
On 26.03.2008 21:05, Jake Peavy wrote:<br></div><div><div></div><div class="Wj3C7c">> Has anyone looked at porting Coreboot onto MIPS architecture? Can it be<br> > used as a Yamon replacement?<br> ><br> <br> <br>
Nobody has looked into it yet, but we welcome all contributions to<br>
Coreboot, especially for non-x86 architectures. Please note, though,<br> that the x86 arch (main support area for Coreboot) traditionally has<br> extremely crappy firmware/BIOS compared to any other architecture. I<br> have to admit that I just started to read up on Yamon and it roughly<br>
seems to do what we would achieve with a combination of Coreboot and a<br> payload like OpenFirmware.<br> <br> Coreboot is designed to make lowlevel init fast and easy with clean and<br> well-structured code, supporting diverse payloads. Target settings<br>
(northbridge, southbridge, SuperI/O) are compiled in except for the<br> usual bus probing stuff. A Coreboot MIPS target could do it all<br> differently, though. Unfortunately <a href="http://linux-mip.org" target="_blank">linux-mip.org</a> is down and I could not<br>
find out whether Yamon really tries to support all available hardware<br> with one binary. That would be impossible in the x86 world due to<br> inability to probe certain stuff and due to size constraints.<br> <br> If you decide to look into Coreboot MIPS support, please don't study<br>
coreboot v2. The coreboot v3 architecture is a lot cleaner because we<br> learned a lot with previous generations, the code is nicer and we even<br> have a design document which is reasonably accurate. Of course, if the<br>
MIPS angle shows considerable problems with the current Coreboot v3<br> design, we'd be happy to hear about it to improve the design.<br> <br> By the way, it would be nice to know how execution starts on MIPS (top<br>
or bottom of address space). I have a patch which adds handling for<br> bottom-booting architectures to v3, but so far we have seen no use case.<br> </div></div></blockquote></div><br>Hi Carl,<br><br>I'd be interested in trying to help with this effort. It would be certainly be a learning experience for me.<br>
<br>If Coreboot has been ported to PPC it might be very similar. Both PPC and MIPS architectures are RISC based, but maybe that's where the similarities end.<br><br>Based on <a href="http://www.mips.com/media/files/MD00103-2B-4KE-SUM-02.04.pdf" target="_blank">http://www.mips.com/media/files/MD00103-2B-4KE-SUM-02.04.pdf</a> section 6.1.5, MIPS execution begins at 0x1FC00000. At least on the MIPS32 core I have ;-)<br clear="all">
<br>You mentioned payload, is this typically the S1 (MBR) code in x86 arch?<br><font color="#888888"><br>-- <br>-jp<br><br><br>If you think a weakness can be turned into a strength, I hate to tell you this, but that's another weakness.<br>
<br><a href="http://deepthoughtsbyjackhandy.com" target="_blank">deepthoughtsbyjackhandy.com</a><br><br></font></div>