On Mon, Mar 31, 2008 at 11:50 AM, Ed Swierk <<a href="mailto:eswierk@arastra.com">eswierk@arastra.com</a>> wrote:<br><div class="gmail_quote"><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
The early init code of several Intel southbridge chipsets calls<br>
pci_locate_device() to locate the SMBus controller and LPC bridge<br>
devices on the PCI bus. Since these devices are always located at a<br>
fixed PCI bus:device:function, the code can be simplified by<br>
hardcoding the devices.<br>
<br>
Signed-off-by: Ed Swierk <<a href="mailto:eswierk@arastra.com">eswierk@arastra.com</a>><br>
<br>--<br>
coreboot mailing list<br>
<a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br>
<a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br></blockquote></div><br>Acked-by: Corey Osgood <<a href="mailto:corey.osgood@gmail.com">corey.osgood@gmail.com</a>><br>
<br><blockquote style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;" class="gmail_quote">Index: coreboot-v2-3189/src/southbridge/intel/esb6300/esb6300_early_smbus.c<br>===================================================================<br>
--- coreboot-v2-3189.orig/src/southbridge/intel/esb6300/esb6300_early_smbus.c<br>+++ coreboot-v2-3189/src/southbridge/intel/esb6300/esb6300_early_smbus.c<br>@@ -4,12 +4,8 @@<br> <br> static void enable_smbus(void)<br> {<br>
-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x25a4), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBUS controller not found\r\n");<br>-    }<br>-    uint8_t enable;<br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>
+<br>     print_spew("SMBus controller enabled\r\n");<br>     pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>     pci_write_config8(dev, 0x40, 1);<br>@@ -19,11 +15,6 @@ static void enable_smbus(void)<br>     <br>
     /* Disable interrupt generation */<br>     outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br>-<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("ISA bridge not found\r\n");<br>
-    }<br> }<br> <br> static int smbus_read_byte(unsigned device, unsigned address)<br>Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_lpc.c<br>===================================================================<br>
--- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100_early_lpc.c<br>+++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_lpc.c<br>@@ -20,12 +20,7 @@<br> <br> static void i3100_enable_superio(void)<br> {<br>
-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,<br>-                       PCI_DEVICE_ID_INTEL_3100_LPC), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("LPC bridge not found\r\n");<br>
-    }<br>+    device_t dev = PCI_DEV(0, 0x1f, 0);<br> <br>     /* Enable decoding of I/O locations for SuperIO devices */<br>     pci_write_config16(dev, 0x82, 0x340f);<br>@@ -33,12 +28,7 @@ static void i3100_enable_superio(void)<br>
 <br> static void i3100_halt_tco_timer(void)<br> {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,<br>-                       PCI_DEVICE_ID_INTEL_3100_LPC), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>
-        die("LPC bridge not found\r\n");<br>-    }<br>+    device_t dev = PCI_DEV(0, 0x1f, 0);<br> <br>     /* Temporarily enable the ACPI I/O range at 0x4000 */<br>     pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));<br>
Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_smbus.c<br>===================================================================<br>--- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100_early_smbus.c<br>
+++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100_early_smbus.c<br>@@ -24,12 +24,8 @@<br> <br> static void enable_smbus(void)<br> {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,<br>
-                       PCI_DEVICE_ID_INTEL_3100_SMB), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBus controller not found\r\n");<br>-    }<br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>+<br>     print_spew("SMBus controller enabled\r\n");<br>
     pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>     pci_write_config8(dev, 0x40, 1);<br>Index: coreboot-v2-3189/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c<br>===================================================================<br>
--- coreboot-v2-3189.orig/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c<br>+++ coreboot-v2-3189/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c<br>@@ -3,12 +3,8 @@<br> <br> static void enable_smbus(void)<br>
 {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_SMB), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBUS controller not found\r\n");<br>
-    }<br>-    <br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>+<br>     print_debug("SMBus controller enabled\r\n");<br>     /* set smbus iobase */<br>     pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);<br>
Index: coreboot-v2-3189/src/southbridge/intel/i82801db/i82801db_early_smbus.c<br>===================================================================<br>--- coreboot-v2-3189.orig/src/southbridge/intel/i82801db/i82801db_early_smbus.c<br>
+++ coreboot-v2-3189/src/southbridge/intel/i82801db/i82801db_early_smbus.c<br>@@ -22,13 +22,10 @@<br> <br> static void enable_smbus(void)<br> {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);<br>
-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBUS controller not found\r\n");<br>-    }<br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>+<br>     print_spew("SMBus controller enabled\r\n");<br>-    <br>
+<br>     pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>     /* Set smbus enable */<br>     pci_write_config8(dev, 0x40, 1);<br>@@ -36,19 +33,12 @@ static void enable_smbus(void)<br>     pci_write_config8(dev, 0x4, 1);<br>
     /* SMBALERT_DIS */<br>     pci_write_config8(dev, 0x11, 4);<br>-    <br>+<br>     /* Disable interrupt generation */<br>     outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br> <br>     /* clear any lingering errors, so the transaction will run */<br>
     outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);<br>-<br>-#if 0    // It's unlikely that half the southbridge suddenly vanishes?<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>
-        die("ISA bridge not found\r\n");<br>-    }<br>-#endif<br> }<br> <br> static int smbus_read_byte(unsigned device, unsigned address)<br>Index: coreboot-v2-3189/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c<br>
===================================================================<br>--- coreboot-v2-3189.orig/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c<br>+++ coreboot-v2-3189/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c<br>
@@ -21,12 +21,8 @@<br> <br> static void enable_smbus(void)<br> {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x24c3), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBUS controller not found\r\n");<br>
-    }<br>-    <br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>+<br>     print_debug("SMBus controller enabled\r\n");<br>     /* set smbus iobase */<br>     pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>Index: coreboot-v2-3189/src/southbridge/intel/i82801er/i82801er_early_smbus.c<br>
===================================================================<br>--- coreboot-v2-3189.orig/src/southbridge/intel/i82801er/i82801er_early_smbus.c<br>+++ coreboot-v2-3189/src/southbridge/intel/i82801er/i82801er_early_smbus.c<br>
@@ -4,13 +4,10 @@<br> <br> static void enable_smbus(void)<br> {<br>-    device_t dev;<br>-    dev = pci_locate_device(PCI_ID(0x8086, 0x24d3), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("SMBUS controller not found\r\n");<br>
-    }<br>+    device_t dev = PCI_DEV(0, 0x1f, 3);<br>+<br>     print_spew("SMBus controller enabled\r\n");<br>-    <br>+<br>     pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>     /* Set smbus enable */<br>
     pci_write_config8(dev, 0x40, 1);<br>@@ -18,19 +15,12 @@ static void enable_smbus(void)<br>     pci_write_config8(dev, 0x4, 1);<br>     /* SMBALERT_DIS */<br>     pci_write_config8(dev, 0x11, 4);<br>-    <br>+<br>     /* Disable interrupt generation */<br>
     outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br> <br>     /* clear any lingering errors, so the transaction will run */<br>     outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);<br>-<br>-#if 0    // It's unlikely that half the southbridge suddenly vanishes?<br>
-    dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);<br>-    if (dev == PCI_DEV_INVALID) {<br>-        die("ISA bridge not found\r\n");<br>-    }<br>-#endif<br> }<br> <br> static int smbus_read_byte(unsigned device, unsigned address)<br>
</blockquote>