Set manual settings for dbe62; the auto settings are giving slightly wrong values

Add call to dumplxmsr in dbe62 initram main()

Add dumplxmsrs function to geodelx raminit support code

Correct spelling of CAS

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Index: mainboard/artecgroup/dbe62/initram.c
===================================================================
--- mainboard/artecgroup/dbe62/initram.c	(revision 637)
+++ mainboard/artecgroup/dbe62/initram.c	(working copy)
@@ -33,9 +33,9 @@
 #include <northbridge/amd/geodelx/raminit.h>
 #include <spd.h>
 
-#define MANUALCONF 0		/* Do automatic strapped PLL config */
-#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
-#define PLLMSRLO 0x02000030
+#define MANUALCONF 1		/* Do automatic strapped PLL config */
+#define PLLMSRHI 0x000003d9	/* manual settings for the PLL */
+#define PLLMSRLO 0x07de0080	/* from factory bios */
 #define DIMM0 ((u8) 0xA0)
 #define DIMM1 ((u8) 0xA2)
 
@@ -124,6 +124,8 @@
   */
 int main(void)
 {
+	void dumplxmsrs(int level);
+
 	u8 smb_devices[] =  {
 		DIMM0, DIMM1
 	};
@@ -151,6 +153,7 @@
 	sdram_enable(DIMM0, DIMM1);
 	printk(BIOS_DEBUG, "done sdram enable\n");
 
+	dumplxmsrs(BIOS_DEBUG);
 	/* Check low memory */
 	ram_check(0x00000000, 640*1024);
 
Index: northbridge/amd/geodelx/raminit.c
===================================================================
--- northbridge/amd/geodelx/raminit.c	(revision 637)
+++ northbridge/amd/geodelx/raminit.c	(working copy)
@@ -35,6 +35,42 @@
 
 u8 spd_read_byte(u16 device, u8 address);
 
+
+/** 
+ * Dump key MSR values for ram init. You can call this function and then use it to 
+ * compare to a fuctory bios setting.
+ * @param level printk level
+ */
+
+void dumplxmsrs(int level)
+{
+	static unsigned long msrs[] = {
+        	MC_CF07_DATA, 
+        	MC_CF8F_DATA, 
+        	MC_CF1017_DATA, 
+        	GLCP_DELAY_CONTROLS, 
+        	MC_CFCLK_DBUG, 
+        	MC_CF_PMCTR,
+		GLCP_SYS_RSTPLL
+	};
+	static char *msrnames[] = {
+        	"MC_CF07_DATA", 
+        	"MC_CF8F_DATA", 
+        	"MC_CF1017_DATA", 
+        	"GLCP_DELAY_CONTROLS", 
+        	"MC_CFCLK_DBUG", 
+        	"MC_CF_PMCTR",
+		"PLL reg"
+	};
+	int i;
+
+	for(i = 0; i < sizeof(msrs)/sizeof(msrs[0]); i++){
+		struct msr msr;
+		msr = rdmsr(msrs[i]);
+		printk(level, "(%lx): %x.%x\n",  msrs[i], msr.hi, msr.lo);
+	}
+
+}
 /**
  * Halt and Catch Fire. Print an error, then loop, sending NULLs on serial port, 
  * to ensure the message is visible. 
@@ -389,7 +425,7 @@
 		hlt();
 	}
 
-	printk(BIOS_DEBUG, "Set cas latency to %x\n", spd_byte);
+	printk(BIOS_DEBUG, "Set CAS latency to %x\n", spd_byte);
 	msr = rdmsr(MC_CF8F_DATA);
 	msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
 	msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;