On Sat, Apr 5, 2008 at 8:24 PM, <<a href="mailto:joe@smittys.pointclark.net">joe@smittys.pointclark.net</a>> wrote:<br><div class="gmail_quote"><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
This patch halts the tco timer early in the boot process on all ICH series southbridges. It also keeps the boot processes from rebooting through out the coreboot process.<br>
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Signed-off-by: Joseph Smith <<a href="mailto:joe@smittys.pointclark.net" target="_blank">joe@smittys.pointclark.net</a>><br>
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Thanks - Joe</blockquote><div><br><blockquote style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;" class="gmail_quote">Index: src/southbridge/intel/i82801xx/i82801xx_early_lpc.c<br>
===================================================================<br>--- src/southbridge/intel/i82801xx/i82801xx_early_lpc.c (revision 0)<br>+++ src/southbridge/intel/i82801xx/i82801xx_early_lpc.c (revision 0)<br>
@@ -0,0 +1,44 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008 Joseph Smith <<a href="mailto:joe@smittys.pointclark.net">joe@smittys.pointclark.net</a>><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>
+ * it under the terms of the GNU General Public License version 2 as<br>+ * published by the Free Software Foundation.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ *<br>+ * You should have received a copy of the GNU General Public License<br>+ * along with this program; if not, write to the Free Software<br>
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<br>+ *<br>+ */<br>+<br>+#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */<br>+#define TCOBASE 0x60 /* TCO Base Address Register */<br>
+#define TCO1_CNT 0x08 /* TCO1 Control Register */</blockquote><div><br>These should go into i82801xx.h, along with the defines in i82801xx_lpc.h. Do that, and this patch is<br>Acked-by: Corey Osgood <<a href="mailto:corey.osgood@gmail.com">corey.osgood@gmail.com</a>><br>
</div><div> </div><blockquote style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;" class="gmail_quote">+<br>+static void i82801xx_halt_tco_timer(void)<br>+{<br>+ device_t dev;<br>
+ uint16_t halt_tco_timer;<br>+<br>+ /* Set the LPC device statically. */<br>+ dev = PCI_DEV(0x0, 0x1f, 0x0);<br>+<br>+ /* Temporarily set ACPI base address (I/O space). */<br>+ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));<br>
</blockquote><blockquote style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;" class="gmail_quote">+<br>+ /* Temporarily enable ACPI I/O. */<br>+ pci_write_config8(dev, ACPI_CNTL, 0x10);<br>
+<br>+ /* Halt the TCO timer, preventing SMI and automatic reboot */<br>+ outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);<br>+<br>+ /* Disable ACPI I/O. */<br>+ pci_write_config8(dev, ACPI_CNTL, 0x00);<br>
+}<br>Index: src/mainboard/rca/rm4100/auto.c<br>===================================================================<br>--- src/mainboard/rca/rm4100/auto.c (revision 3217)<br>+++ src/mainboard/rca/rm4100/auto.c (working copy)<br>
@@ -42,6 +42,7 @@<br> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)<br> <br> #include "southbridge/intel/i82801xx/i82801xx_early_smbus.c"<br>+#include "southbridge/intel/i82801xx/i82801xx_early_lpc.c"<br>
<br> /**<br> * The onboard 128MB PC133 memory does not have a SPD EEPROM so the<br>@@ -69,24 +70,6 @@<br> #include "sdram/generic_sdram.c"<br> <br> /**<br>- * We have to disable the TCO Timer system reboot feature<br>
- * or we get several reboots through out the boot processes.<br>- */<br>-static void disable_tco_timer(void)<br>-{<br>- device_t dev;<br>- u8 reg8;<br>-<br>- /* Set the LPC device statically. */<br>- dev = PCI_DEV(0x0, 0x1f, 0x0);<br>
-<br>- /* Disable the TCO Timer system reboot feature. */<br>- reg8 = pci_read_config8(dev, 0xd4);<br>- reg8 |= (1 << 1);<br>- pci_write_config8(dev, 0xd4, reg8);<br>-}<br>-<br>-/**<br> * The AC'97 Audio Controller I/O space registers are read only by default<br>
* so we need to enable them by setting register 0x41 to 0x01.<br> */<br>@@ -131,6 +114,6 @@<br> /* ram_check(0, 640 * 1024); */<br> /* ram_check(130048 * 1024, 131072 * 1024); */<br> <br>- disable_tco_timer();<br>
+ i82801xx_halt_tco_timer();<br> ac97_io_enable();<br> } <br></blockquote></div></div><br>