Hi...<br> But in the data sheet they have mentioned like the SST49LF00xB detects whether it is being <br><br>accessed via a FWH or LPC protocol by detecting the START field contents; a 1101b or 1110b <br><br>indi-cates a Firmware Memory cycle and a 0000b indicates an LPC memory cycle.<br>
<br>but when i checked the content in the empty SST chip it shows like this <br><br><pre>[<a href="http://www.coreboot.org/mailman/listinfo/coreboot">root at localhost</a> ~]# hexdump sst_after_erase.bin<br>0000000 ffff ffff ffff ffff ffff ffff ffff ffff<br>
*<br>0080000</pre>from this i came to know that SST chip is working in LPC mode as <br><br>compared to data sheet ...is it right? i am totally confusing....<br><br>please inform me how to find whether chip is in FWH or LPC mode.<br>
<br>thanks in advance<br>Malatesh <br><br><br><br><br><br><div><span class="gmail_quote">On 05/04/2008, <b class="gmail_sendername">malatesh kamatad</b> <<a href="mailto:malateshkamat@gmail.com">malateshkamat@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Hello,<br> But the content after writing by using below command shows result like this....<br><br>[root@localhost ~]# /usr/local/sbin/flashrom -r | hexdump <br><br>0000000 6143 696c 7262 7461 6e69 2067 6564 616c<br>0000010 2079 6f6c 706f 2e2e 202e 4b4f 0a2e 6f4e<br>
0000020 6320 726f 6265 6f6f 2074 6174 6c62 2065<br>0000030 6f66 6e75 2e64 460a 756f 646e 6320 6968<br>0000040 7370 7465 2220 4956 2041 5456 3238 3733<br>0000050 2c22 6520 616e 6c62 6e69 2067 6c66 7361<br>0000060 2068 7277 7469 2e65 2e2e 4f20 2e4b 530a<br>
0000070 5453 3934 464c 3030 4134 422f 6620 756f<br>0000080 646e 6120 2074 6870 7379 6369 6c61 6120<br>0000090 6464 6572 7373 3020 6678 6666 3038 3030<br>00000a0 2e30 460a 616c 6873 7020 7261 2074 7369<br>00000b0 5320 5453 3934 464c 3030 4134 422f 2820<br>
00000c0 3135 2032 424b 2e29 450a 7272 726f 203a<br>00000d0 6f4e 6620 6c69 6e65 6d61 2065 7073 6365<br>00000e0 6669 6569 2e64 000a <br>00000e7<br><br>************************************<br> But using only hexdump i got result like this ...<br>
<br>[root@localhost ~]# hexdump sst_after_write05.bin <br><span class="q">0000000 ffff ffff ffff ffff ffff ffff ffff ffff<br>*<br>0080000<br><br></span><div><span class="e" id="q_1191d5e5a8bfc5d9_2">Thanks.<br>Malatesh<br>
<br><div><span class="gmail_quote">On 04/04/2008, <b class="gmail_sendername">malatesh kamatad</b> <<a href="mailto:malateshkamat@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">malateshkamat@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Ya .. after checking that file i got result like this ...it shows that there is a content in that file <br><br>[root@localhost ~]# hexdump sst_after_erase.bin <br>0000000 ffff ffff ffff ffff ffff ffff ffff ffff<br>*<br>0080000<br>
<br> I think erasing is not happened properly..<div><span><br><br>Thanks..<br>malatesh<br><br><div><span class="gmail_quote">On 04/04/2008, <b class="gmail_sendername">Corey Osgood</b> <<a href="mailto:corey.osgood@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">corey.osgood@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Ok, so if you open up the sst_after_erase.bin with a hex editor, is there anything in it? Does that match the data from the diff, or is it a binary ORing of the data from the diff? Do you have any other flash chips you can try on the board?<div>
<span><br>
<br>On Fri, Apr 4, 2008 at 8:41 AM, malatesh kamatad <<a href="mailto:malateshkamat@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">malateshkamat@gmail.com</a>> wrote:<br><div class="gmail_quote">
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Ya i got result like this after comparing <br><br> [root@localhost ~]# diff -us original.bin sst_after_write.bin <br>Binary files original.bin and sst_after_write.bin differ<br><br> but its showing that there is a difference in between to files ....<br>
<br> i think write is not happening proper ....<br><br>Thanks .<br><font color="#888888">malatesh</font><div><div></div><div><br><br><div><span class="gmail_quote">On 04/04/2008, <b class="gmail_sendername">Corey Osgood</b> <<a href="mailto:corey.osgood@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">corey.osgood@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
what's the output of diff -us original.bin sst_after_write.bin? Can you download the bios from the manufacturer and see if flashing that works?<br><br>-Corey<div><span><br><br>On Fri, Apr 4, 2008 at 7:03 AM, malatesh kamatad <<a href="mailto:malateshkamat@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">malateshkamat@gmail.com</a>> wrote:<br>
</span></div><div class="gmail_quote"><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><div><span> I worked with the step by step this is the output......<br>
<br>[root@localhost ~]# flashrom -r original.bin<div>
<br>Calibrating delay loop... OK.<br>No coreboot table found.<br>Found chipset "VIA VT8237", enabling flash write... OK.<br></div>
Pm49FL004 found at physical address 0xfff80000.<br>Flash part is Pm49FL004 (512 KB).<br>Reading Flash...done<br><div><br>[root@localhost ~]# flashrom -E<br>Calibrating delay loop... OK.<br>No coreboot table found.<br>
Found chipset "VIA VT8237", enabling flash write... OK.<br>
SST49LF004A/B found at physical address 0xfff80000.<br>Flash part is SST49LF004A/B (512 KB).<br>Erasing flash chip<br><br></div>[root@localhost ~]# flashrom -r sst_after_erase.bin<div><br>Calibrating delay loop... OK.<br>
No coreboot table found.<br>
Found chipset "VIA VT8237", enabling flash write... OK.<br>SST49LF004A/B found at physical address 0xfff80000.<br>Flash part is SST49LF004A/B (512 KB).<br>Reading Flash...done<br><br></div>[root@localhost ~]# flashrom -w original.bin<div>
<br>
Calibrating delay loop... OK.<br>No coreboot table found.<br>Found chipset "VIA VT8237", enabling flash write... OK.<br>SST49LF004A/B found at physical address 0xfff80000.<br>Flash part is SST49LF004A/B (512 KB).<br>
Flash image seems to be a legacy BIOS. Disabling checks.<br>Programming page: 0007 at address: 0x00070000<br><br></div>[root@localhost ~]# flashrom -r sst_after_write.bin<div><br>Calibrating delay loop... OK.<br>
No coreboot table found.<br>
Found chipset "VIA VT8237", enabling flash write... OK.<br>SST49LF004A/B found at physical address 0xfff80000.<br>Flash part is SST49LF004A/B (512 KB).<br>Reading Flash...done<br><br></div>Thanks,<br><font color="#888888">Malatesh.</font><div>
<div></div><div><br><div>
<span class="gmail_quote">On 04/04/2008, <b class="gmail_sendername">malatesh kamatad</b> <<a href="mailto:malateshkamat@gmail.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">malateshkamat@gmail.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Hi..<br> <br> We are having two BIOS i.e, PM49FL004( motherboard's BIOS) and empty flashrom <br><br> SST49LF004B ..<br> <br> We are trying to flash the content of PM49FL004 to SST49LF004B flashrom<br>
<br> according to your suggestion we have done ..we are getting output as bellow..<span><br> <br>
<p style="margin-bottom: 0in;">[root@localhost ~]# flashrom -E</p>
<p style="margin-bottom: 0in;">Calibrating delay loop... OK.</p>
<p style="margin-bottom: 0in;">No coreboot table found.</p>
<p style="margin-bottom: 0in;">Found chipset "VIA VT8237",
enabling flash write... OK.</p>
<p style="margin-bottom: 0in;">SST49LF004A/B found at physical address
0xfff80000.</p>
<p style="margin-bottom: 0in;">Flash part is SST49LF004A/B (512 KB).</p>
<p style="margin-bottom: 0in;">Erasing flash chip</p>
</span><span><p style="margin-bottom: 0in;">Erasing page: 0007 at address:
0x00070000</p>
</span><p style="margin-bottom: 0in;">[root@localhost ~]# flashrom -r
malateh.bin</p><span>
<p style="margin-bottom: 0in;">Calibrating delay loop... OK.</p>
<p style="margin-bottom: 0in;">No coreboot table found.</p>
<p style="margin-bottom: 0in;">Found chipset "VIA VT8237",
enabling flash write... OK.</p>
<p style="margin-bottom: 0in;">SST49LF004A/B found at physical address
0xfff80000.</p>
<p style="margin-bottom: 0in;">Flash part is SST49LF004A/B (512 KB).</p>
</span><p style="margin-bottom: 0in;">Reading Flash...done</p>
<p style="margin-bottom: 0in;">[root@localhost ~]# flashrom -w
malateh.bin</p><span>
<p style="margin-bottom: 0in;">Calibrating delay loop... OK.</p>
<p style="margin-bottom: 0in;">No coreboot table found.</p>
<p style="margin-bottom: 0in;">Found chipset "VIA VT8237",
enabling flash write... OK.</p>
<p style="margin-bottom: 0in;">SST49LF004A/B found at physical address
0xfff80000.</p>
<p style="margin-bottom: 0in;">Flash part is SST49LF004A/B (512 KB).</p>
<p style="margin-bottom: 0in;">Flash image seems to be a legacy BIOS.
Disabling checks.</p>
<p style="margin-bottom: 0in;">Programming page: 0007 at address:
0x00070000</p>
</span><p style="margin-bottom: 0in;">[root@localhost ~]# flashrom -v
malateh.bin</p><span>
<p style="margin-bottom: 0in;">Calibrating delay loop... OK.</p>
<p style="margin-bottom: 0in;">No coreboot table found.</p>
<p style="margin-bottom: 0in;">Found chipset "VIA VT8237",
enabling flash write... OK.</p>
<p style="margin-bottom: 0in;">SST49LF004A/B found at physical address
0xfff80000.</p>
<p style="margin-bottom: 0in;">Flash part is SST49LF004A/B (512 KB).</p>
<p style="margin-bottom: 0in;">Flash image seems to be a legacy BIOS.
Disabling checks.</p>
</span><p style="margin-bottom: 0in;">Verifying flash... VERIFIED.
</p>
<br><br> After that we tried to boot the system by SST49lf004B but system is not rebooting....<br><br>So we want to flash the content of the Pm49fl004 to SST49lf004 so that our system can boot <br><br>using SST49lf004....<br>
<br>thanks,<br><span>Malatesh..</span><div><span><br> <br><br><div><span class="gmail_quote">On 04/04/2008, <b class="gmail_sendername">bari</b> <<a href="mailto:bari@onelabs.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">bari@onelabs.com</a>> wrote:</span><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Try Peters suggestion of reading the flash after an erase and see what is there.<br>
<br>
If it is erased, read back after you have tried to write and compare.<br>
<br>
See what is or is not happening.<br>
<br>
-Bari<br>
<br>
malatesh kamatad wrote:<br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><span>
Hi...<br>
I am working on ASRock motherboard .....in FWH mode...<br>
<br>
with regards.<br>
Malatesh<br>
<br></span><span>
On 03/04/2008, *bari* <<a href="mailto:bari@onelabs.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">bari@onelabs.com</a> <mailto:<a href="mailto:bari@onelabs.com" target="_blank" onclick="return top.js.OpenExtLink(window,event,this)">bari@onelabs.com</a>>> wrote:<br>
<br>
malatesh kamatad wrote:<br>
<br>
<br>
Hi all..<br>
I have worked with PM49fl00x.diff patch ,its worked fine<br>
and i got the output as below<br>
<br>
The PM49fl00x can work in LPC and FWH modes. Do you know which<br>
mode is being used?<br>
What mainboard did you test this in?<br>
<br>
Now i am working on SST49LF004B 33-4C-NHE<br>
0710022-CA with the<br>
motherboard K8Upgrade-VM800<br>
The flashrom detect flash device on this<br>
board, But the erasing and writting operation is not happening<br>
properly<br>
hier flashrom output : <br>
Is this the board by ASRock?<br>
<br>
-Bari<br>
<br>
<br>
<br>
</span></blockquote>
<br>
</blockquote></div><br>
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