diff -Naur ms9282/Config.lb ms7250/Config.lb
--- ms9282/Config.lb	2008-01-26 16:57:03.000000000 +0000
+++ ms7250/Config.lb	2007-09-26 13:49:54.000000000 +0000
@@ -1,5 +1,5 @@
 ##
-## This file is part of the coreboot project.
+## This file is part of the LinuxBIOS project.
 ##
 ## Copyright (C) 2006 AMD
 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -24,7 +24,7 @@
 
 ##
 ## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
 ##
 if USE_FALLBACK_IMAGE
        default ROM_SECTION_SIZE   = FALLBACK_SIZE
@@ -36,19 +36,19 @@
 
 ##
 ## Compute the start location and size size of
-## The coreboot bootloader.
+## The linuxBIOS bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 default CONFIG_ROM_PAYLOAD     = 1
 
 ##
-## Compute where this copy of coreboot will start in the boot rom
+## Compute where this copy of linuxBIOS will start in the boot rom
 ##
 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
-## Compute a range of ROM that can cached to speed up coreboot,
+## Compute a range of ROM that can cached to speed up linuxBIOS,
 ## execution speed.
 ##
 ## XIP_ROM_SIZE must be a power of 2.
@@ -81,14 +81,14 @@
 
 makerule ./auto.o
         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
 end
 
 else
 
 makerule ./auto.inc
         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 end
@@ -122,7 +122,7 @@
 end
 
 ##
-## Build our 16 bit and 32 bit coreboot entry code
+## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
 if USE_FALLBACK_IMAGE
         mainboardinit cpu/x86/16bit/entry16.inc
@@ -142,7 +142,7 @@
 end
 
 ##
-## Build our reset vector (This is where coreboot is entered)
+## Build our reset vector (This is where linuxBIOS is entered)
 ##
 if USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
@@ -180,7 +180,7 @@
 end
 
 ###
-### This is the early phase of coreboot startup
+### This is the early phase of linuxBIOS startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -227,22 +227,21 @@
 end
 
 
-# sample config for msi/ms9282
+# sample config for msi/ms7250
 chip northbridge/amd/amdk8/root_complex
         device apic_cluster 0 on
-                chip cpu/amd/socket_F
+                chip cpu/amd/socket_AM2
                         device apic 0 on end
                 end
         end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/nvidia/mcp55
-                                       device pci 0.0 on end   # HT
-                                       device pci 1.0 on # LPC
-                                               chip superio/winbond/w83627ehg
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC was 1.0 test
+						chip superio/winbond/w83627ehg
                                                        device pnp 2e.0 on #  Floppy
                                                                io 0x60 = 0x3f0
                                                                irq 0x70 = 6
@@ -276,106 +275,86 @@
                                                        end
                                                        device pnp 2e.8 off end #  WDTO_PLED
                                                        device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
-                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.a on  end #  ACPI
                                                        device pnp 2e.b on #  HW Monitor
                                                                io 0x60 = 0x290
                                                                irq 0x70 = 5
                                                        end
                                                end
-                                       end
-                                        device pci 1.1 on # SM 0
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 70 on  #0 pca9554 1
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                                       device i2c 70 on  #0 pca9554 2
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                               chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                       end
-                                               end
-                                       end
-                                       device pci 1.1 on # SM 1
-                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                       device i2c 72 on     #pca9554 channle1
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on     #pca9545 channel 2
-                                                               chip drivers/i2c/adm1027   #HWM ADT7463
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                                       device i2c 72 on end  #pca9545 channel 3
-                                                       device i2c 72 on      #pca9545 channel 4
-                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
-                                                                       device i2c 2e on end
-                                                               end
-                                                       end
-                                               end
-                                       end
-
-                                       device pci 2.0 on end # USB 1.1
-                                       device pci 2.1 on end # USB 2
-                                       device pci 4.0 on  end # IDE
-                                               device pci 5.0 on  end # SATA 0
-                                       device pci 5.1 on  end # SATA 1
-                                       device pci 5.2 on  end # SATA 2
-                                       device pci 6.0 on  #P2P
+					end
+			                device pci 1.1 on # SM 0 was 1.1 test!
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+					device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+					
+                			device pci 6.0 on end # PCI
+					
+					device pci 6.0 on  #P2P
                                                chip drivers/pci/onboard
                                                        device pci 4.0 on end
                                                        register "rom_address" = "0xfff80000"
                                                end
-                                       end # P2P
-                                       device pci 7.0 on end # reserve
-                                       device pci 8.0 on end # MAC0
-                                       device pci 9.0 on end # MAC1
-                                       device pci a.0 on
+					end  
+					    
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			#device pci a.0 on end # PCI E 5
+					
+					 device pci a.0 on
                                                device pci 0.0 on
                                                        chip drivers/pci/onboard
                                                                device pci 4.0 on end  #pci_E lan1
@@ -383,36 +362,46 @@
                                                        end
                                                end
                                        end # 0x376
-                                               device pci b.0 on  end # PCI E 0x374
-                                       device pci c.0 on  end
-                                       device pci d.0 on   #SAS
+					
+					
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			#device pci d.0 on end # PCI E 2
+					
+					 device pci d.0 on   #SAS
                                                chip drivers/pci/onboard
                                                        device pci 0.0 on end
                                                end
                                        end # PCI E 1 0x378
-                                       device pci e.0 on end # PCI E 0 0x375
-                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
-                                       register "ide0_enable" = "1"
-                                       register "ide1_enable" = "1"
-                                       register "sata0_enable" = "1"
-                                       register "sata1_enable" = "1"
-                               end
-                       end #  device pci 18.0
-                       device pci 18.0 on end # Link 1
-                       device pci 18.0 on end
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end
-#                device pnp 0.1 off end
-#                device pnp 0.2 off end
-#                device pnp 0.3 off end
-#                device pnp 0.4 off end
-#              device pnp 0.5 on end
-#        end
-end # root_complex
+					
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex
diff -Naur ms9282/Options.lb ms7250/Options.lb
--- ms9282/Options.lb	2008-01-18 15:08:58.000000000 +0000
+++ ms7250/Options.lb	2007-08-07 11:47:35.000000000 +0000
@@ -1,5 +1,5 @@
 ##
-## This file is part of the coreboot project.
+## This file is part of the LinuxBIOS project.
 ##
 ## Copyright (C) 2006 AMD
 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
@@ -57,7 +57,7 @@
 uses MAINBOARD_VENDOR
 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
+uses LINUXBIOS_EXTRA_VERSION
 uses _RAMBASE
 uses CONFIG_GDB_STUB
 uses CROSS_COMPILE
@@ -99,7 +99,6 @@
 # stepan 2007-04-12
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
 
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes
@@ -125,7 +124,7 @@
 default HAVE_FALLBACK_BOOT=1
 
 ##
-## Build code to reset the motherboard from coreboot
+## Build code to reset the motherboard from linuxBIOS
 ##
 default HAVE_HARD_RESET=1
 
@@ -133,7 +132,7 @@
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default IRQ_SLOT_COUNT=23
 
 ##
 ## Build code to export an x86 MP table
@@ -147,7 +146,7 @@
 default HAVE_OPTION_TABLE=1
 
 ##
-## Move the default coreboot cmos range off of AMD RTC registers
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
 ##
 default LB_CKS_RANGE_START=49
 default LB_CKS_RANGE_END=122
@@ -158,8 +157,10 @@
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_MAX_CPUS=2
+## was 4
+default CONFIG_MAX_PHYSICAL_CPUS=1
+## was 2/1
 default CONFIG_LOGICAL_CPUS=1
 
 #CHIP_NAME ?
@@ -181,7 +182,8 @@
 #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
 
 ##bx_b005+ make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
+default SB_HT_CHAIN_ON_BUS0=2
+##was1
 
 ##only offset for SB chain?, default is yes(1)
 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
@@ -194,14 +196,16 @@
 ## enable CACHE_AS_RAM specifics
 ##
 default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcc000
-default DCACHE_RAM_SIZE=0x4000
+default DCACHE_RAM_BASE=0xc8000
+## was 0xcc000
+default DCACHE_RAM_SIZE=0x08000
+## was 0x4000
 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
 default CONFIG_USE_INIT=0
 
-default ENABLE_APIC_EXT_ID=1
+default ENABLE_APIC_EXT_ID=0
 default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=0
+default LIFT_BSP_APIC_ID=1
 
 
 ##
@@ -212,16 +216,16 @@
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="ms9282"
+default MAINBOARD_PART_NUMBER="ms7250"
 default MAINBOARD_VENDOR="MSI"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
 
 ###
-### coreboot layout values
+### LinuxBIOS layout values
 ###
 
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
 default ROM_IMAGE_SIZE = 65536
 
 ##
@@ -232,7 +236,8 @@
 ##
 ## Use a small 16K heap
 ##
-default HEAP_SIZE=0x4000
+default HEAP_SIZE=0x8000
+## was 0x4000
 
 ##
 ## Only use the option table in a normal image
@@ -240,9 +245,10 @@
 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 
 ##
-## Coreboot C code runs at this location in RAM
+## LinuxBIOS C code runs at this location in RAM
 ##
-default _RAMBASE=0x00004000
+default _RAMBASE=0x00100000
+### was 0x00004000
 
 ##
 ## Load the payload from the ROM
@@ -289,7 +295,7 @@
 default TTYS0_LCS=0x3
 
 ##
-### Select the coreboot loglevel
+### Select the linuxBIOS loglevel
 ##
 ## EMERG      1   system is unusable
 ## ALERT      2   action must be taken immediately
diff -Naur ms9282/apc_auto.c ms7250/apc_auto.c
--- ms9282/apc_auto.c	1970-01-01 00:00:00.000000000 +0000
+++ ms7250/apc_auto.c	2007-02-17 14:28:11.000000000 +0000
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 AMD
+ * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1 
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "arch/i386/lib/console.c"
+
+#if 0 
+static void post_code(uint8_t value) {
+#if 1
+        int i;
+        for(i=0;i<0x80000;i++) {
+                outb(value, 0x80);
+        }
+#endif
+}
+#endif
+
+#include <cpu/amd/model_fxx_rev.h>
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+
+#include "lib/delay.c"
+
+//#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
+#include "northbridge/amd/amdk8/amdk8_f.h"
+
+#include "cpu/x86/mtrr.h"
+#include "cpu/amd/mtrr.h"
+#include "cpu/x86/tsc.h"
+
+#include "northbridge/amd/amdk8/amdk8_f_pci.c"
+#include "northbridge/amd/amdk8/raminit_f_dqs.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+void hardwaremain(int ret_addr)
+{
+	struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+        struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+
+	struct node_core_id id;
+
+	id = get_node_core_id_x();
+
+	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+
+	train_ram(id.nodeid, sysinfo, sysinfox);
+
+	/*
+		go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
+	*/
+
+        __asm__ volatile (
+                "movl  %0, %%edi\n\t"
+                "jmp     *%%edi\n\t"
+                :: "a"(ret_addr)
+        );
+
+
+
+}
+struct eregs {
+        uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
+        uint32_t vector;
+        uint32_t error_code;
+        uint32_t eip;
+        uint32_t cs;
+        uint32_t eflags;
+};
+
+void x86_exception(struct eregs *info)
+{
+        do {
+                hlt();
+        } while(1);
+}
+
+
diff -Naur ms9282/cache_as_ram_auto.c ms7250/cache_as_ram_auto.c
--- ms9282/cache_as_ram_auto.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/cache_as_ram_auto.c	2007-07-10 15:49:38.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -26,56 +23,80 @@
 #define __ROMCC__
 
 #define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
 
-#define SET_NB_CFG_54 1
+#define K8_ALLOCATE_IO_RANGE 1
+//#define K8_SCAN_PCI_BUS 1
+
 
-//used by raminit
 #define QRANK_DIMM_SUPPORT 1
 
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
 //used by init_cpus and fidvid
 #define K8_SET_FIDVID 1
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#define DEBUG_SMBUS 1
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
 
+#define DBGP_DEFAULT 7
+ 
 #include <stdint.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
+#if CONFIG_USBDEBUG_DIRECT
+#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
+#include "pc80/usbdebug_direct_serial.c"
+#endif
+#include "ram/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>
+
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 
-#if CONFIG_USE_INIT == 0
-       #include "lib/memcpy.c"
 #endif
 
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#if USE_FAILOVER_IMAGE==0
+
 #include "cpu/x86/bist.h"
 
+#if CONFIG_USE_INIT == 0
+        #include "lib/memcpy.c"
+#endif
+
+#include "northbridge/amd/amdk8/debug.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
 
-#include <device/pci_ids.h>
+
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+
 static void memreset_setup(void)
 {
 }
@@ -86,49 +107,48 @@
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITCH2 0x72
-        unsigned device=(ctrl->channel0[0])>>8;
-        smbus_send_byte(SMBUS_SWITCH1, device);
-       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+	print_debug("activate_spd_rom: nothing needs to be done \r\n");
 }
 
-#if 0
-static inline void change_i2c_mux(unsigned device)
-{
-#define SMBUS_SWITCH1 0x70
-#define SMBUS_SWITHC2 0x72
-        smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
-       smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-}
-#endif
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
-       return smbus_read_byte(device, address);
+	return smbus_read_byte(device, address);
 }
 
-//#define K8_4RANK_DIMM_SUPPORT 1
+
+
+
+
+
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/raminit_f.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
+
 #include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit_f.c"
+
 #include "sdram/generic_sdram.c"
 
- /* msi does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c" 
+
 #include "cpu/amd/dualcore/dualcore.c"
 
 #define MCP55_NUM 1
-#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
-//set GPIO to input mode
+#define MCP55_USE_NIC 1
+#define MCP55_USE_AZA 1
+
+#define MCP55_PCI_E_X_0 0
+
 #define MCP55_MB_SETUP \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
+        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
+#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
 #include "cpu/amd/car/copy_and_run.c"
@@ -136,9 +156,12 @@
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
+
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#if USE_FALLBACK_IMAGE == 1
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -151,16 +174,19 @@
         uint32_t dword;
         uint8_t byte;
 
-        byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20;
+        byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
+        byte |= 0x20; 
         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
-
+        
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<0);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
-
+        
+        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
+        dword |= (1<<16);
+        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 }
+
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
         unsigned last_boot_normal_x = last_boot_normal();
@@ -198,99 +224,180 @@
  normal_image:
         __asm__ volatile ("jmp __normal_image"
                 : /* outputs */
-                : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
                 );
 
  fallback_image:
-       ;
+#if HAVE_FAILOVER_BOOT==1
+        __asm__ volatile ("jmp __fallback_image"
+                : /* outputs */
+                : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+                )
+#endif
+	;
 }
 #endif
-
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
-#if USE_FALLBACK_IMAGE == 1
-        failover_process(bist, cpu_init_detectedx);
+#if HAVE_FAILOVER_BOOT==1 
+    #if USE_FAILOVER_IMAGE==1
+	failover_process(bist, cpu_init_detectedx);	
+    #else
+	real_main(bist, cpu_init_detectedx);
+    #endif
+#else
+    #if USE_FALLBACK_IMAGE == 1
+	failover_process(bist, cpu_init_detectedx);	
+    #endif
+	real_main(bist, cpu_init_detectedx);
 #endif
-        real_main(bist, cpu_init_detectedx);
-
 }
 
-//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
-#define RC0 (2<<8)
-#define RC1 (1<<8)
+#if USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-       static const uint16_t spd_addr [] = {
-                       RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-                       RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+	static const uint16_t spd_addr [] = {
+			(0xa<<3)|0, (0xa<<3)|1, 0, 0,
+			(0xa<<3)|2, (0xa<<3)|3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-                       RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-                       RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
+			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
 #endif
-       };
-
-       unsigned bsp_apicid = 0;
-        int needs_reset;
-       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-       char *p ;
+	};
+	
+	
+
+        struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+        int needs_reset = 0;
+        unsigned bsp_apicid = 0;
+	
+	uint32_t dword;
 
         if (bist == 0) {
-               //init_cpus(cpu_init_detectedx);
-               bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+		
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+		
         }
 
-       w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+	w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
+	
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+	
+	if (bist == 0) {
+		print_debug("bist==0 cpus inited \r\n");
+		}
+		
+	#if CONFIG_MAX_PHYSICAL_CPUS > 1
+	print_debug("CONFIG_MAX_PHYSICAL_CPUS > 1 \r\n");
+	#endif
+
+
+#if CONFIG_USBDEBUG_DIRECT
+	mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
+	early_usbdebug_direct_init();
+	//console_init();
+#endif
+        //console_init();
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 
-       /* Halt if there was a built in self test failure */
-       report_bist_failure(bist);
-
-        setup_ms9282_resource_map();
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 
-       setup_coherent_ht_domain();
+        
+#if MEM_TRAIN_SEQ == 1
+        set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+	print_debug("set_sysinfo_in_ram(0)");
+#endif
+        setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();
-
+	print_debug("setup_coherent_ht_domain()");
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
+        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+         * So here need to make sure last core0 is started, esp for two way system,
+         * (there may be apic id conflicts in that case)
+         */
         start_other_cores();
-        //wait_all_other_cores_started(bsp_apicid);
+        wait_all_other_cores_started(bsp_apicid);
+	print_debug("start_other_cores()");
 #endif
+
+        /* it will set up chains and store link pair for optimization later */
         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-       needs_reset = optimize_link_coherent_ht();
+#if K8_SET_FIDVID == 1
 
-       needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 
-        needs_reset |= mcp55_early_setup_x();
+        }
+
+        enable_fid_change();
+
+        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+        init_fidvid_bsp(bsp_apicid);
+
+        // show final fid and vid
+        {
+                msr_t msr;
+                msr=rdmsr(0xc0010042);
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 
-               if (needs_reset) {
-                       print_info("ht reset -\r\n");
-                       soft_reset();
-               }
-
-        //It's the time to set ctrl now;
-        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-       enable_smbus();
-
-#if 0
-        int i;
-        for(i=4;i<8;i++) {
-                change_i2c_mux(i);
-                dump_smbus_registers();
         }
 #endif
 
-       memreset_setup();
+        needs_reset |= optimize_link_coherent_ht();
+        needs_reset |= optimize_link_incoherent_ht(sysinfo);
+        needs_reset |= mcp55_early_setup_x();
+
+        // fidvid change will issue one LDTSTOP and the HT change will be effective too
+        if (needs_reset) {
+                print_info("ht reset -\r\n");
+            	soft_reset();
+        }
+        allow_all_aps_stop(bsp_apicid);
+print_debug("allow_all_aps_stop");
+        //It's the time to set ctrl in sysinfo now;
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+print_debug("fill_mem_ctrl");
+        enable_smbus(); 
+print_debug("enable_smbus()");
+        memreset_setup();
+print_debug("memreset_setup()");
+        //do we need apci timer, tsc...., only debug need it for better output
+        /* all ap stopped? */
+	
+        //init_timer(); // Need to use TMICT to synconize FID/VID was disabled!
+//print_debug("init_timer()");
+
+        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+print_debug("sdram_initialize \r\n ");
+/*print_debug("sysinfo \r\n ");
+dump_mem(0x000cf000, 0x000cf730);*/
+write32(0x00100000,0x12345678);
+write32(0xfffe0000,0x12345678 /*value*/);
+dump_mem(0xfffe0000, 0xfffe0000+0x100);
+dump_mem(0x00100000, 0x00100000+0x100);
+
+dword=read32(0x00100000);
+print_debug_hex32(dword);
 
-       sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
-       post_cache_as_ram();
+
+        post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+	print_debug("post_cache_as_ram()");
 
 }
+
+
+#endif
diff -Naur ms9282/chip.h ms7250/chip.h
--- ms9282/chip.h	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/chip.h	2007-06-28 11:15:52.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 MSI
  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
@@ -19,9 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-extern struct chip_operations mainboard_msi_ms9282_ops;
+extern struct chip_operations mainboard_msi_ms7250_ops;
 
-struct mainboard_msi_ms9282_config {
+struct mainboard_msi_ms7250_config {
        int fixup_scsi;
        int fixup_vga;
 };
diff -Naur ms9282/failover.c ms7250/failover.c
--- ms9282/failover.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/failover.c	2007-06-29 13:23:13.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
@@ -61,7 +61,17 @@
 
 static unsigned long main(unsigned long bist)
 {
-        /* Make cerain my local apic is useable */
+        int i=0;
+	/* Make cerain my local apic is useable */
+	#if 0
+	print_debug("entering main");
+	for(i=0;i<10000;i++)
+	{
+	intel_chip_post_macro(0x01);
+	}
+	#endif
+	
+	
         enable_lapic();
 
         /* Is this a cpu only reset? */
diff -Naur ms9282/get_bus_conf.c ms7250/get_bus_conf.c
--- ms9282/get_bus_conf.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/get_bus_conf.c	2007-08-08 12:14:08.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -33,70 +30,48 @@
 
 #include <cpu/amd/amdk8_sysconf.h>
 
-#include "mb_sysconf.h"
 
 // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
+//busnum is default
+        unsigned char bus_isa;
+        unsigned char bus_mcp55[8]; //1
+        unsigned apicid_mcp55;
+
 
-unsigned pci1234x[] =
+unsigned pci1234x[] = 
 {        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
-        //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-        0x0000ff0,
+	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
         0x0000ff0,
-        0x0000ff0,
-//        0x0000ff0,
+//        0x0000ff0, //   ff0
+//        0x0000ff0, //   ff0
+//        0x0000ff0, //   ff0
 //        0x0000ff0,
 //        0x0000ff0,
 //        0x0000ff0,
 //        0x0000ff0
 };
-unsigned hcdnx[] =
+unsigned hcdnx[] = 
 { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
-       0x20202020,
-       0x20202020,
-        0x20202020,
+	0x20202020,
+//	0x20202020,
+ //       0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 //        0x20202020,
 };
-
+unsigned bus_type[256]; 
 
 extern void get_sblk_pci1234(void);
 
 static unsigned get_bus_conf_done = 0;
 
-static unsigned get_hcid(unsigned i)
-{
-        unsigned id = 0;
-
-        unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
-        unsigned devn = sysconf.hcdn[i] & 0xff;
-
-        device_t dev;
-
-        dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
-        switch (dev->device) {
-        case 0x0369: //IO55
-                id = 4;
-                break;
-        }
-
-        // we may need more way to find out hcid: subsystem id? GPIO read ?
-
-        // we need use id for 1. bus num, 2. mptable, 3. acpi table
-
-        return id;
-}
-
 void get_bus_conf(void)
 {
 
-       unsigned apicid_base;
-       struct mb_sysconf_t *m;
+	unsigned apicid_base;
+	unsigned sbdn;
 
         device_t dev;
         int i, j;
@@ -105,11 +80,6 @@
 
         get_bus_conf_done = 1;
 
-       sysconf.mb = &mb_sysconf;
-
-       m = sysconf.mb;
-       memset(m, 0, sizeof(struct mb_sysconf_t));
-
         sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
         for(i=0;i<sysconf.hc_possible_num; i++) {
                 sysconf.pci1234[i] = pci1234x[i];
@@ -118,51 +88,59 @@
 
         get_sblk_pci1234();
 
-       sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+	sbdn = sysconf.sbdn;
 
-       m->bus_type[0] = 1; //pci
+	for(i=0; i<8; i++) {
+		bus_mcp55[i] = 0;
+	}
+	
+	for(i=0;i<256; i++) {
+		bus_type[i] = 0;
+	}
+
+	bus_type[0] = 1; //pci
+	
+	bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 
-       m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_type[bus_mcp55[0]] = 1;
 
                 /* MCP55 */
-                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
                 if (dev) {
-                        m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+                        bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+                        bus_mcp55[2]++;
+			for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
                 }
                 else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
-                }
+                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
 
-               for(i=2; i<8;i++) {
-                       dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
-                       if (dev) {
-                               m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                       }
-                       else {
-                               printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
-                       }
-               }
-
-       for(i=0; i< sysconf.hc_possible_num; i++) {
-               if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-                unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
-               for (j = busn; j <= busn_max; j++)
-                       m->bus_type[j] = 1;
-               if(m->bus_isa <= busn_max)
-                       m->bus_isa = busn_max + 1;
-               printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
-       }
+                        bus_mcp55[1] = 2;
+                        bus_mcp55[2] = 3;
+                }
 
+		for(i=2; i<8;i++) {
+	                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
+        	        if (dev) {
+                	        bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+        	                bus_isa++;
+				for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
+	                }
+        	        else {
+                	        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
+	                        bus_isa = bus_mcp55[i-1]+1;
+        	        }
+		}
 
 
-/*I/O APICs:   APIC ID Version State           Address*/
+/*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
-       apicid_base = get_apicid_base(1);
-#else
-       apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+	apicid_base = get_apicid_base(1);
+#else 
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
 #endif
-       m->apicid_mcp55 = apicid_base+0;
+	apicid_mcp55 = apicid_base+0;
 
 }
diff -Naur ms9282/irq_tables.c ms7250/irq_tables.c
--- ms9282/irq_tables.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/irq_tables.c	2008-03-18 16:18:52.000000000 +0000
@@ -1,45 +1,46 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+/* This file was generated by getpir.c, do not modify!
+ * (but if you do, please run checkpir on it to verify)
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * Contains the IRQ Routing Table dumped directly from your
+ * memory, which BIOS sets up.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
  */
 
-/* This file was generated by getpir.c, do not modify!
-   (but if you do, please run checkpir on it to verify)
-   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
-   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
+#ifdef GETPIR
+#include "pirq_routing.h"
+#else
+#include <arch/pirq_routing.h>
+#endif
 #include <console/console.h>
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/pirq_routing.h>
+//#include <arch/pirq_routing.h>
 
 #include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
+
+
+
+/* Platform IRQs */
+#define PIRQA 10
+#define PIRQB 11
+#define PIRQC 10
+#define PIRQD 11
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+
+
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
 
 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
-               uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
-               uint8_t slot, uint8_t rfu)
+  uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+  uint8_t slot, uint8_t rfu)
 {
         pirq_info->bus = bus;
         pirq_info->devfn = devfn;
@@ -55,22 +56,65 @@
         pirq_info->rfu = rfu;
 }
 
-unsigned long write_pirq_routing_table(unsigned long addr)
+#if 0
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,  /* u32 signature */
+	PIRQ_VERSION,    /* u16 version   */
+	32+16*23,	 /* There can be total 23 devices on the bus */
+	0x00,		 /* Where the interrupt router lies (bus) */
+	(0x01<<3)|0x0,   /* Where the interrupt router lies (dev) */
+	0,		 /* IRQs devoted exclusively to PCI usage */
+	0x10de,		 /* Vendor */
+	0x364,		 /* Device */
+	0,		 /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x46,		 /* u8 checksum. This has to be set to some
+			    value that would give 0 after the sum of all
+			    bytes for this structure (including checksum) */
+	{
+		/* bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
+		{0x00,(0x01<<3)|0x0, {{0x02, 0x4ca0}, {0x05, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x02<<3)|0x0, {{0x08, 0x4ca0}, {0x03, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x08<<3)|0x0, {{0x0a, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x09<<3)|0x0, {{0x09, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x05<<3)|0x0, {{0x07, 0x4ca0}, {0x06, 0x4ca0}, {0x0f, 0x4ca0}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x06<<3)|0x0, {{0x00, 0x0000}, {0x0b, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+		{0x00,(0x0f<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x0, 0x0},
+		{0x07,(0x00<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x20, 0x0},
+		{0x00,(0x0e<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x0, 0x0},
+		{0x06,(0x00<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x21, 0x0},
+		{0x00,(0x0d<<3)|0x0, {{0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x04ca0}}, 0x0, 0x0},
+		{0x05,(0x00<<3)|0x0, {{0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x04ca0}}, 0x22, 0x0},
+		{0x00,(0x0c<<3)|0x0, {{0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x04ca0}}, 0x0, 0x0},
+		{0x04,(0x00<<3)|0x0, {{0x84, 0x4ca0}, {0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x04ca0}}, 0x23, 0x0},
+		{0x00,(0x0b<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x0, 0x0},
+		{0x03,(0x00<<3)|0x0, {{0x85, 0x4ca0}, {0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x04ca0}}, 0x24, 0x0},
+		{0x00,(0x0a<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x0, 0x0},
+		{0x02,(0x00<<3)|0x0, {{0x86, 0x4ca0}, {0x87, 0x4ca0}, {0x84, 0x4ca0}, {0x85, 0x04ca0}}, 0x25, 0x0},
+		{0x01,(0x00<<3)|0x0, {{0x80, 0x4ca0}, {0x81, 0x4ca0}, {0x82, 0x4ca0}, {0x83, 0x04ca0}}, 0x1, 0x0},
+		{0x01,(0x01<<3)|0x0, {{0x81, 0x4ca0}, {0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x04ca0}}, 0x2, 0x0},
+		{0x01,(0x02<<3)|0x0, {{0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x4ca0}, {0x81, 0x04ca0}}, 0x3, 0x0},
+		{0x01,(0x05<<3)|0x0, {{0x82, 0x4ca0}, {0x83, 0x4ca0}, {0x80, 0x4ca0}, {0x81, 0x04ca0}}, 0x4, 0x0},
+		{0x01,(0x04<<3)|0x0, {{0x83, 0x4ca0}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+	}
+};
+#endif
+
+
+unsigned long routing_table(unsigned long addr)
 {
 
-       struct irq_routing_table *pirq;
-       struct irq_info *pirq_info;
-       unsigned slot_num;
-       uint8_t *v;
-       struct mb_sysconf_t *m;
-       unsigned sbdn;
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+ unsigned sbdn;
 
         uint8_t sum=0;
         int i;
 
         get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-       sbdn = sysconf.sbdn;
-       m = sysconf.mb;
+ sbdn = sysconf.sbdn;
 
         /* Align the table to be 16 byte aligned. */
         addr += 15;
@@ -79,52 +123,408 @@
         /* This table must be betweeen 0xf0000 & 0x100000 */
         printk_info("Writing IRQ routing tables to 0x%x...", addr);
 
-       pirq = (void *)(addr);
-       v = (uint8_t *)(addr);
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+ 
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version  = PIRQ_VERSION;
+ 
+ pirq->rtr_bus = bus_mcp55[0];
+ pirq->rtr_devfn = ((sbdn+1)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+ 
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x0360; //0x0370 0x0364;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+
+#if 0
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x0800, 0x5, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x0080, 0x6, 0x0400, 0x0f, 0x0800, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# if 1 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x0020, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+# endif 
+
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x00, 0x0000, 0x0b, 0xdef8, 0x00, 0x0000, 0x00, 0x0000, 0, 0);
+# endif 
+ 
+ pirq_info++; slot_num++;
+ // write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x07, ((sbdn+0x00)<<3)|0, 0x85, 0x0400, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x20, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x06, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x05, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x04, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x03, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x02, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0, 0x83/*81*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, /*0x2*/ 0x2, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x04)<<3)|0, 0x83, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+
+#endif
+
+
+
+#if 1 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x4ca0, 0x5, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x4ca0, 0x6, 0x4ca0, 0x0f, 0x4ca0, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info,0x07 /*bus_mcp55[7]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x20, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x06 /*bus_mcp55[6]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x05 /*bus_mcp55[5]*/, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x04 /*bus_mcp55[0]*/, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x03/*bus_mcp55[3]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x02/*bus_mcp55[2]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[1]*/, ((sbdn+0x00)<<3)|0, 0x80, 0x4ca0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x04ca0, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x01)<<3)|0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x04ca0, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x04)<<3)|0, 0x83, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+#endif 
+ 
+ 
+ 
+ pirq->size = 32 + 16 * slot_num;
+
+        for (i = 0; i < pirq->size; i++)
+                sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+        if (sum != pirq->checksum) {
+                pirq->checksum = sum;
+        }
 
-       pirq->signature = PIRQ_SIGNATURE;
-       pirq->version  = PIRQ_VERSION;
+ printk_info("done.\n");
+
+ return (unsigned long) pirq_info;
+
+}
 
-       pirq->rtr_bus = m->bus_mcp55[0];
-       pirq->rtr_devfn = ((sbdn+6)<<3)|0;
 
-       pirq->exclusive_irqs = 0;
 
-       pirq->rtr_vendor = 0x10de;
-       pirq->rtr_device = 0x0370;
 
-       pirq->miniport_data = 0;
 
-       memset(pirq->rfu, 0, sizeof(pirq->rfu));
 
-       pirq_info = (void *) ( &pirq->checksum + 1);
-       slot_num = 0;
-//pci bridge
-       write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-       pirq_info++; slot_num++;
+unsigned long routing_table2(unsigned long addr)
+{
 
-        for(i=1; i< sysconf.hc_possible_num; i++) {
-                if(!(sysconf.pci1234[i] & 0x1) ) continue;
-                unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-                unsigned devn = sysconf.hcdn[i] & 0xff;
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+ unsigned sbdn;
 
-                write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-                pirq_info++; slot_num++;
-       }
+        uint8_t sum=0;
+        int i;
 
-       pirq->size = 32 + 16 * slot_num;
+        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ sbdn = sysconf.sbdn;
+
+        /* Align the table to be 16 byte aligned. */
+        addr += 15;
+        addr &= ~15;
+
+        /* This table must be betweeen 0xf0000 & 0x100000 */
+        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+ 
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version  = PIRQ_VERSION;
+ 
+ pirq->rtr_bus = bus_mcp55[0];
+ pirq->rtr_devfn = ((sbdn+6/*+3*/)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+ 
+ pirq->rtr_vendor = 0x10de;
+ pirq->rtr_device = 0x0370; //0x0370; 0x0364
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+ 
+# if 1 /*from 7260*/
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x01, 0xdef8, 0x2,0xdef8 /*0x0020*/, 0x03, 0xdef8, 0x04, 0xdef8, 0x0, 0x0);
+ 
+ pirq_info++; slot_num++;
+# endif
+
+#if 1
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x0800, 0x5, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x0400, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x0080, 0x6, 0x0400, 0x0f, 0x0800, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b,0x0100 /*0x0020*/, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+# endif 
+
+# if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x00, 0x0000, 0x0b, 0xdef8, 0x00, 0x0000, 0x00, 0x0000, 0, 0);
+# endif 
+ 
+# if 0 /*from 7260*/
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x01, 0xdef8, 0x2,0xdef8 /*0x0020*/, 0x03, 0xdef8, 0x04, 0xdef8, 0x0, 0x0);
+ pirq_info++; slot_num++;
+# endif 
+
+ //pirq_info++; slot_num++;
+ 
+ // write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x07, ((sbdn+0x00)<<3)|0, 0x85, 0x0400, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x20, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x06, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x05, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x04, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x03, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x02, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+// pirq_info++; slot_num++;
+
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x00)<<3)|0, 0x80/*80*/, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x1, 0x0);
+ pirq_info++; slot_num++;
+
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x01)<<3)|0, 0x81/*81*/,/*0x0800*/ 0x0800, 0x00,/*0x0*/ 0x0000, 0x00,/*0x0*/ 0x0000, 0x00, 0x00000, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01, ((sbdn+0x02)<<3)|0, 0x82,/*0x4ca0*/  0x4c80, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+// pirq_info++; slot_num++;
+// write_pirq_info(pirq_info, 0x01, ((sbdn+0x04)<<3)|0, 0x83, 0x0800, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ //pirq_info++; slot_num++;
+
+#endif
+
+
+
+#if 0 
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x01)<<3)|0, 0x2, 0x4ca0, 0x5, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x02)<<3)|0, 0x8, 0x4ca0, 0x3, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x08)<<3)|0, 0x0a, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x09)<<3)|0, 0x09, 0x4ca0, 0x0, 0x0000, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x05)<<3)|0, 0x07, 0x4ca0, 0x6, 0x4ca0, 0x0f, 0x4ca0, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x06)<<3)|0, 0x00, 0x0000, 0x0b, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0f)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info,0x07 /*bus_mcp55[7]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x20, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0e)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x06 /*bus_mcp55[6]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x21, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0d)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x05 /*bus_mcp55[5]*/, ((sbdn+0x00)<<3)|0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x04ca0, 0x22, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0c)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x04 /*bus_mcp55[0]*/, ((sbdn+0x00)<<3)|0, 0x84, 0x4ca0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x04ca0, 0x23, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0b)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x03/*bus_mcp55[3]*/, ((sbdn+0x00)<<3)|0, 0x85, 0x4ca0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x04ca0, 0x24, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+0x0a)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x0, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x02/*bus_mcp55[2]*/, ((sbdn+0x00)<<3)|0, 0x86, 0x4ca0, 0x87, 0x4ca0, 0x84, 0x4ca0, 0x85, 0x04ca0, 0x25, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[1]*/, ((sbdn+0x00)<<3)|0, 0x80, 0x4ca0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x04ca0, 0x1, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x01)<<3)|0, 0x81, 0x4ca0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x04ca0, 0x2, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x02)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x3, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x05)<<3)|0, 0x82, 0x4ca0, 0x83, 0x4ca0, 0x80, 0x4ca0, 0x81, 0x04ca0, 0x4, 0x0);
+ pirq_info++; slot_num++;
+ write_pirq_info(pirq_info, 0x01/*bus_mcp55[0]*/, ((sbdn+0x04)<<3)|0, 0x83, 0x4ca0, 0x00, 0x0000, 0x00, 0x0000, 0x00, 0x00000, 0x0, 0x0);
+ pirq_info++; slot_num++;
+#endif 
+ 
+ 
+ 
+ pirq->size = 32 + 16 * slot_num;
 
         for (i = 0; i < pirq->size; i++)
                 sum += v[i];
 
-       sum = pirq->checksum - sum;
+ sum = pirq->checksum - sum;
 
         if (sum != pirq->checksum) {
                 pirq->checksum = sum;
         }
 
-       printk_info("done.\n");
+ printk_info("done.\n");
 
-       return  (unsigned long) pirq_info;
+ return (unsigned long) pirq_info;
+
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	int i, j, k, num_entries;
+	unsigned char pirq[4];
+	uint16_t chipset_irq_map;
+	uint32_t pciAddr, pirtable_end;
+	struct irq_routing_table *pirq_tbl;
+	unsigned functNum;
+	unsigned result;
+	device_t pdev;
+
+	//pirtable_end = copy_pirq_routing_table(addr);
+	pirtable_end = routing_table2(addr);
+
+	/* Set up chipset IRQ steering. */
+#if 0	
+/*just something I do not understand*/	
+	pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+	chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
+	printk_debug("%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
+		     chipset_irq_map);
+	outl(pciAddr & ~3, 0xCF8);
+	outl(chipset_irq_map, 0xCFC);	
+#endif
+	pirq_tbl = (struct irq_routing_table *)(addr);
+	num_entries = (pirq_tbl->size - 32) / 16;
+
+	/* Set PCI IRQs. */
+	for (i = 0; i < num_entries; i++) {
+		//printk_debug("PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
+		//	     pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
+		for (j = 0; j < 4; j++) {
+			//printk_debug("INT: %c bitmap: %x ", 'A' + j,
+			//	     pirq_tbl->slots[i].irq[j].bitmap);
+			for (k = 0; (!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1)) && (pirq_tbl->slots[i].irq[j].bitmap != 0); k++) ;
+	/* Finds lsb in bitmap to IRQ#. */
+			pirq[j] = k;
+			//printk_debug("PIRQ: %d\n", k);
+		}
+
+		/* Bus, device, slots IRQs for {A,B,C,D}. */
+		pci_assign_irqs(pirq_tbl->slots[i].bus,
+				pirq_tbl->slots[i].devfn >> 3, pirq);
+	}
+	
+	for (functNum = 0; functNum < 8; functNum++) {
+		pdev = dev_find_slot(0x01, (0x01 << 3) + functNum);
+
+		if (pdev) {
+	
+	/*It was for realtek*/
+	//pdev = dev_find_slot(0x1, (0x1 << 3) + 0x0);
+	
+	//pci_write_config8(pdev, 0x55, 0x00);
+	/*
+	pci_write_config32(pdev, 0x55, 0xFFFFFFFF);
+	pci_write_config32(pdev, 0x55, 0x0);
+	printk_debug("0x55 Device found  \n");
+	result=pci_read_config8(pdev, 0x55);
+	print_debug_hex8(result);	*/
+	                     }
+	}
+	
+	//pirtable_end = routing_table(addr);
 
+	/* Put the PIR table in memory and checksum. */
+	return pirtable_end;
 }
diff -Naur ms9282/mainboard.c ms7250/mainboard.c
--- ms9282/mainboard.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mainboard.c	2007-02-19 19:11:20.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 MSI
  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
diff -Naur ms9282/mb_sysconf.h ms7250/mb_sysconf.h
--- ms9282/mb_sysconf.h	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mb_sysconf.h	2007-02-09 00:26:10.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2006 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
diff -Naur ms9282/mptable.c ms7250/mptable.c
--- ms9282/mptable.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/mptable.c	2007-08-08 16:29:29.000000000 +0000
@@ -1,12 +1,9 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
- * Copyright (C) 2006 AMD
+ * Copyright (C) 2007 AMD
  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
  *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -29,19 +26,22 @@
 #include <stdint.h>
 
 #include <cpu/amd/amdk8_sysconf.h>
+extern unsigned char bus_isa;
+extern unsigned char bus_mcp55[8]; //1
+
+extern unsigned apicid_mcp55;
 
-#include "mb_sysconf.h"
+extern unsigned bus_type[256]; 
 
 void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "MSI    ";
-        static const char productid[12] = "MS9282       ";
+        static const char productid[12] = "MS7250       ";
         struct mp_config_table *mc;
-       struct mb_sysconf_t *m;
-       unsigned sbdn;
+	unsigned sbdn;
 
-       int i,j;
+	int i,j;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
         memset(mc, 0, sizeof(*mc));
@@ -60,112 +60,145 @@
         mc->mpe_checksum = 0;
         mc->reserved = 0;
 
-        smp_write_processors(mc);
+       smp_write_processors(mc);
+       
+      // smp_write_processor(mc,0x00, 0x10,0x3, 0x0f32, 0x178bfbff);
+      // smp_write_processor(mc,0x01, 0x10,0x1, 0x0f32, 0x178bfbff);
 
-       get_bus_conf();
-       sbdn = sysconf.sbdn;
-       m = sysconf.mb;
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
 
-/*Bus:         Bus ID  Type*/
+/*Bus:		Bus ID	Type*/
        /* define bus and isa numbers */
         for(j= 0; j < 256 ; j++) {
-               if(m->bus_type[j])
-                        smp_write_bus(mc, j, "PCI   ");
+		if(bus_type[j])
+			 smp_write_bus(mc, j, "PCI   ");
+			 
+			 
         }
-        smp_write_bus(mc, m->bus_isa, "ISA   ");
+        smp_write_bus(mc, bus_isa, "ISA   ");
 
-/*I/O APICs:   APIC ID Version State           Address*/
+/*I/O APICs:	APIC ID	Version	State		Address*/
         {
                 device_t dev;
-               struct resource *res;
-               uint32_t dword;
+		struct resource *res;
+		uint32_t dword;
 
-                dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+                dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
                 if (dev) {
-                       res = find_resource(dev, PCI_BASE_ADDRESS_1);
-                       if (res) {
-                               smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
-                       }
+			print_debug("Device found \r\n");
+			res = find_resource(dev, PCI_BASE_ADDRESS_1);
+			
+			
+			print_debug("PCI: ");
+			print_debug_hex32(dev);
+			
+			
+			if (res) {
+				smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
+				print_debug_hex32(res->base);
+				print_debug("\r\n");
+			}
 
-                       dword = 0x43c6c643;
-                       pci_write_config32(dev, 0x7c, dword);
+			dword = 0x43c6c643;
+	        	pci_write_config32(dev, 0x7c, dword);
 
-                       dword = 0x81001a00;
-                       pci_write_config32(dev, 0x80, dword);
+		        dword = 0x81001a00;
+		        pci_write_config32(dev, 0x80, dword);
 
-                       dword = 0xd00002d2;
-                       pci_write_config32(dev, 0x84, dword);
+	        	dword = 0xd0001202;
+		        pci_write_config32(dev, 0x84, dword);
 
                 }
-
-
-       }
-
-                  /*I/O Ints:  Type    Polarity    Trigger                     Bus ID   IRQ    APIC ID PIN# */
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
-       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
-
-//SMBUS
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
-
-//USB1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
-
-//USB2.0
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
-
-//SATA2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
-
-//SATA3
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
-
-//NIC1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
-//NIC2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
-
-       for(j=7; j>=2; j--) {
-               if(!m->bus_mcp55[j]) continue;
-               for(i=0;i<4;i++) {
-                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
-               }
-       }
-
-       for(j=0; j<1; j++)
-               for(i=0;i<4;i++) {
-                       smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
-               }
-
-/*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
-       smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
-       smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
-       /* There is no extension information... */
-
-       /* Compute the checksums */
-       mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-       mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-       printk_debug("Wrote the mp table end at: %p - %p\n",
-               mc, smp_next_mpe_entry(mc));
-       return smp_next_mpe_entry(mc);
+	}
+  
+/*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+*/
+	//apicid_mcp55=0x0;
+	print_debug("bus_isa "); print_debug_hex32(bus_isa); print_debug("\r\n");
+	print_debug("bus_mcp55[0] "); print_debug_hex32(bus_mcp55[0]); print_debug("\r\n");
+	print_debug("bus_mcp55[1] "); print_debug_hex32(bus_mcp55[1]); print_debug("\r\n");
+	print_debug("apicid_mcp55 "); print_debug_hex32(apicid_mcp55); print_debug("\r\n");
+	//print_debug("(sbdn+8)<<2)"); print_debug_hex32((sbdn+8)<<2)); print_debug("\r\n");
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_mcp55, 0x1);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_mcp55, 0x2);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_mcp55, 0x3);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_mcp55, 0x4);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_mcp55, 0x6);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH,  bus_mcp55[1], 0x5, apicid_mcp55, 0x5);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_mcp55, 0x7);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_mcp55, 0x8);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_mcp55, 0x9);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_mcp55, 0xc);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_mcp55, 0xd);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_mcp55, 0xe);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_mcp55, 0xf);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|0/*1*/, apicid_mcp55, 0xb/*0xa*/);
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, /*0x15*/0x5); // 23 0X17
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, /*0x14*/0x07); // 20
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, /*0x17*/0x05); // 23
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, /*0x15*/0xb); // 21
+
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, /*0x16*/0xa); // 22
+	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, /*0x16*/0xa); // 22 new device
+	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07/*bus_mcp55[7]*/, ((sbdn+0)<<2)|0, apicid_mcp55, /*0x16*/0xa);//new device
+	
+	/*ethernet 0 */
+#if 0	
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x01/*bus_mcp55[1]*/, ((sbdn+1)<<2)|0, apicid_mcp55, 0xb); // 12
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_LOW, bus_mcp55[1], 0x0, ((sbdn+1)<<2)|0, 0x5); // 5
+	/*smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((sbdn+1)<<2)|1, apicid_mcp55, 0xc); // 5*/
+# endif	
+	
+#if 1/*Test version do not destribute interrupts */
+	for(j=7; j>=2; j--) {
+		if(!bus_mcp55[j]) continue;
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
+        	}
+	}
+
+	for(j=0; j<2; j++) 
+	        for(i=0;i<4;i++) {
+        	        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x00+j)<<2)|i, apicid_mcp55, 0x05 + (2+i+j)%4);
+	        }
+		
+#endif		
+		//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((sbdn+1)<<2)|0, apicid_mcp55, 0x); // 22
+	
+
+/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	
+	/* Compute the checksums */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+	
+	
+	
+	
+	
+	printk_debug("Wrote the mp table end at: %p - %p\n",
+		mc, smp_next_mpe_entry(mc));
+	return smp_next_mpe_entry(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-       void *v;
-       v = smp_write_floating_table(addr);
-       return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr);
+	return (unsigned long)smp_write_config_table(v);
 }
diff -Naur ms9282/resourcemap.c ms7250/resourcemap.c
--- ms9282/resourcemap.c	2008-01-18 10:35:56.000000000 +0000
+++ ms7250/resourcemap.c	2007-07-05 16:24:30.000000000 +0000
@@ -1,5 +1,5 @@
 /*
- * This file is part of the coreboot project.
+ * This file is part of the LinuxBIOS project.
  *
  * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
  *
