Remove inline from FAM10 CPU initialization functions.
This doesn't save any space for me but it is the right thing to allow GCC to optimize.

Signed-off-by: Marc Jones <marc.jones@amd.com>

Index: coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c
===================================================================
--- coreboot-v2.orig/src/cpu/amd/model_10xxx/fidvid.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c	2008-04-25 13:19:40.000000000 -0600
@@ -25,21 +25,21 @@
 // if we are tight of CAR stack, disable it
 #define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
 
-static inline void print_debug_fv(const char *str, u32 val)
+static void print_debug_fv(const char *str, u32 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
 		printk_debug("%s%x\n", str, val);
 #endif
 }
 
-static inline void print_debug_fv_8(const char *str, u8 val)
+static void print_debug_fv_8(const char *str, u8 val)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
 		printk_debug("%s%02x\n", str, val);
 #endif
 }
 
-static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
+static void print_debug_fv_64(const char *str, u32 val, u32 val2)
 {
 #if FAM10_SET_FIDVID_DEBUG == 1
 		printk_debug("%s%x%x\n", str, val, val2);
Index: coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
===================================================================
--- coreboot-v2.orig/src/cpu/amd/model_10xxx/init_cpus.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c	2008-04-25 13:19:40.000000000 -0600
@@ -30,24 +30,24 @@
 	#define FAM10_SET_FIDVID_CORE0_ONLY 0
 #endif
 
-static inline void print_initcpu8 (const char *strval, u8 val)
+static void print_initcpu8 (const char *strval, u8 val)
 {
 	printk_debug("%s%02x\n", strval, val);
 }
 
-static inline void print_initcpu8_nocr (const char *strval, u8 val)
+static void print_initcpu8_nocr (const char *strval, u8 val)
 {
 	printk_debug("%s%02x", strval, val);
 }
 
 
-static inline void print_initcpu16 (const char *strval, u16 val)
+static void print_initcpu16 (const char *strval, u16 val)
 {
 	printk_debug("%s%04x\n", strval, val);
 }
 
 
-static inline void print_initcpu(const char *strval, u32 val)
+static void print_initcpu(const char *strval, u32 val)
 {
 	printk_debug("%s%08x\n", strval, val);
 }
@@ -59,7 +59,7 @@
 void cpuSetAMDMSR(void);
 
 #if PCI_IO_CFG_EXT == 1
-static inline void set_EnableCf8ExtCfg(void)
+static void set_EnableCf8ExtCfg(void)
 {
 	// set the NB_CFG[46]=1;
 	msr_t msr;
@@ -69,7 +69,7 @@
 	wrmsr(NB_CFG_MSR, msr);
 }
 #else
-static inline void set_EnableCf8ExtCfg(void) { }
+static void set_EnableCf8ExtCfg(void) { }
 #endif
 
 
@@ -78,7 +78,7 @@
 /* because we will use gs to store hi, so need to make sure lo can start
    from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
 
-static inline void set_pci_mmio_conf_reg(void)
+static void set_pci_mmio_conf_reg(void)
 {
 #if MMCONF_SUPPORT
 	msr_t msr;
@@ -184,7 +184,7 @@
 }
 
 /* FIXME: Duplicate of what is in lapic.h? */
-static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
+static int lapic_remote_read(int apicid, int reg, u32 *pvalue)
 {
 	int timeout;
 	u32 status;
Index: coreboot-v2/src/cpu/amd/quadcore/quadcore.c
===================================================================
--- coreboot-v2.orig/src/cpu/amd/quadcore/quadcore.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/cpu/amd/quadcore/quadcore.c	2008-04-25 13:19:40.000000000 -0600
@@ -24,7 +24,7 @@
 
 #include "cpu/amd/quadcore/quadcore_id.c"
 
-static inline u32 get_core_num_in_bsp(u32 nodeid)
+static u32 get_core_num_in_bsp(u32 nodeid)
 {
 	u32 dword;
 	dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
@@ -34,7 +34,7 @@
 }
 
 #if SET_NB_CFG_54 == 1
-static inline u8 set_apicid_cpuid_lo(void)
+static u8 set_apicid_cpuid_lo(void)
 {
 	// set the NB_CFG[54]=1; why the OS will be happy with that ???
 	msr_t msr;
@@ -46,12 +46,12 @@
 }
 #else
 
-static inline void set_apicid_cpuid_lo(void) { }
+static void set_apicid_cpuid_lo(void) { }
 
 #endif
 
 
-static inline void real_start_other_core(u32 nodeid, u32 cores)
+static void real_start_other_core(u32 nodeid, u32 cores)
 {
 	u32 dword;
 
@@ -78,7 +78,7 @@
 }
 
 //it is running on core0 of node0
-static inline void start_other_cores(void)
+static void start_other_cores(void)
 {
 	u32 nodes;
 	u32 nodeid;
Index: coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c
===================================================================
--- coreboot-v2.orig/src/cpu/amd/quadcore/quadcore_id.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c	2008-04-25 13:19:40.000000000 -0600
@@ -32,7 +32,7 @@
 	return ( ( msr.hi >> (54-32)) & 1);
 }
 
-static inline u32 get_initial_apicid(void)
+static u32 get_initial_apicid(void)
 {
 	return ((cpuid_ebx(1) >> 24) & 0xff);
 }
@@ -67,12 +67,12 @@
 	return id;
 }
 
-static inline u32 get_core_num(void)
+static u32 get_core_num(void)
 {
 	return (cpuid_ecx(0x80000008) & 0xff);
 }
 
-static inline struct node_core_id get_node_core_id_x(void) {
+static struct node_core_id get_node_core_id_x(void) {
 
 	return get_node_core_id( read_nb_cfg_54() );
 }
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
===================================================================
--- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c	2008-04-25 13:19:40.000000000 -0600
@@ -102,7 +102,7 @@
 }
 
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
+static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
 	int ret,i;
@@ -119,7 +119,7 @@
 }
 
 
-static inline int spd_read_byte(u32 device, u32 address)
+static int spd_read_byte(u32 device, u32 address)
 {
 	int result;
 	result = smbus_read_byte(device, address);
Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
===================================================================
--- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d_gcc.h	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h	2008-04-25 13:20:46.000000000 -0600
@@ -60,7 +60,7 @@
 }
 
 
-static inline u32 bsr(u32 x)
+static u32 bsr(u32 x)
 {
 	u8 i;
 	u32 ret = 0;
@@ -77,7 +77,7 @@
 }
 
 
-static inline u32 bsf(u32 x)
+static u32 bsf(u32 x)
 {
 	u8 i;
 	u32 ret = 32;
Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c
===================================================================
--- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mctdqs_d.c	2008-04-25 13:12:53.000000000 -0600
+++ coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c	2008-04-25 13:19:40.000000000 -0600
@@ -65,7 +65,7 @@
 
 #define DQS_TRAIN_DEBUG 0
 
-static inline void print_debug_dqs(const char *str, u32 val, u8 level)
+static void print_debug_dqs(const char *str, u32 val, u8 level)
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
@@ -74,7 +74,7 @@
 #endif
 }
 
-static inline void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
+static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level)
 {
 #if DQS_TRAIN_DEBUG > 0
 	if (DQS_TRAIN_DEBUG >= level) {
