PWB was not getting set since it is 1<<14 and it was only doing a pci_write_config8.

Signed-off-by: Marc Jones <marc.jones@amd.com>

Index: coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c
===================================================================
--- coreboot-v2.orig/src/southbridge/amd/cs5536/cs5536_ide.c	2008-05-06 10:12:28.000000000 -0600
+++ coreboot-v2/src/southbridge/amd/cs5536/cs5536_ide.c	2008-05-06 10:12:49.000000000 -0600
@@ -43,7 +43,7 @@
 	// NOTE: Only 32-bit writes to the data buffer are allowed when PWB is set
 	ide_cfg = pci_read_config32(dev, IDE_CFG);
 	ide_cfg |= CHANEN | PWB;
-	pci_write_config8(dev, IDE_CFG, ide_cfg);
+	pci_write_config32(dev, IDE_CFG, ide_cfg);
 }
 
 static void ide_enable(struct device *dev)
