./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c:unsigned pm_base; ./southbridge/nvidia/mcp55/lpc.c: unsigned link; ./southbridge/nvidia/mcp55/lpc.c:static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ./southbridge/nvidia/mcp55/stage1_usbdebug.c:static void set_debug_port(unsigned port) ./southbridge/nvidia/mcp55/stage1_usbdebug.c:static void mcp55_enable_usbdebug_direct(unsigned port) ./southbridge/nvidia/mcp55/usb2.c: unsigned base; ./southbridge/nvidia/mcp55/usb2.c: unsigned old_debug; ./southbridge/nvidia/mcp55/mcp55.c:static struct device *find_lpc_dev( struct device *dev, unsigned devfn) ./southbridge/nvidia/mcp55/mcp55.c: unsigned index = 0; ./southbridge/nvidia/mcp55/mcp55.c: unsigned index2 = 0; ./southbridge/nvidia/mcp55/mcp55.c: unsigned deviceid; ./southbridge/nvidia/mcp55/mcp55.c: unsigned vendorid; ./southbridge/nvidia/mcp55/mcp55.c: unsigned devfn; ./southbridge/nvidia/mcp55/stage1.c: int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); ./southbridge/nvidia/mcp55/stage1.c: unsigned vendorid = 0x10de; ./southbridge/nvidia/mcp55/stage1.c: unsigned val = 0x01610109; ./southbridge/nvidia/mcp55/stage1.c:void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) ./southbridge/nvidia/mcp55/stage1.c: unsigned val; ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) ./southbridge/nvidia/mcp55/stage1.c: unsigned busn[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned devn[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned io_base[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 }; ./southbridge/nvidia/mcp55/stage1.c: unsigned busnx; ./southbridge/nvidia/mcp55/stage1.c: unsigned devnx; ./southbridge/nvidia/mcp55/stage1.c:void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) ./northbridge/amd/geodelx/vsmsetup.c: unsigned eax, ebx, ecx, edx; ./northbridge/amd/geodelx/vsmsetup.c: unsigned eax, ebx, ecx, edx; ./northbridge/amd/k8/northbridge.c:static u32 f1_read_config32(unsigned reg) ./northbridge/amd/k8/northbridge.c:static void f1_write_config32(unsigned reg, u32 value) ./northbridge/amd/k8/northbridge.c:static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, config_reg; ./northbridge/amd/k8/northbridge.c: unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain ./northbridge/amd/k8/northbridge.c: unsigned max_bus; ./northbridge/amd/k8/northbridge.c: unsigned min_bus; ./northbridge/amd/k8/northbridge.c: unsigned max_devfn; ./northbridge/amd/k8/northbridge.c: unsigned temp = 0; ./northbridge/amd/k8/northbridge.c: unsigned nodeid; ./northbridge/amd/k8/northbridge.c: unsigned link; ./northbridge/amd/k8/northbridge.c: unsigned sblink = 0; ./northbridge/amd/k8/northbridge.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/northbridge.c:static int reg_useable(unsigned reg, ./northbridge/amd/k8/northbridge.c: struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c:static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, reg; ./northbridge/amd/k8/northbridge.c:static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, reg; ./northbridge/amd/k8/northbridge.c:static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c:static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) ./northbridge/amd/k8/northbridge.c: unsigned reg, link; ./northbridge/amd/k8/northbridge.c:static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) ./northbridge/amd/k8/northbridge.c: unsigned link; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c: unsigned hole_startk; ./northbridge/amd/k8/northbridge.c: unsigned base_k, limit_k; ./northbridge/amd/k8/northbridge.c: unsigned reset_memhole = 1; ./northbridge/amd/k8/northbridge.c: unsigned basek, limitk, sizek; ./northbridge/amd/k8/northbridge.c: unsigned pre_sizek; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nb_cfg_54; ./northbridge/amd/k8/northbridge.c: unsigned siblings; ./northbridge/amd/k8/northbridge.c: unsigned jj; ./northbridge/amd/k8/incoherent_ht.c:static void ht_collapse_previous_enumeration(u8 bus, unsigned offset_unitid) ./northbridge/amd/k8/incoherent_ht.c: u32 bdf1, u8 pos1, unsigned offs1, ./northbridge/amd/k8/incoherent_ht.c: u32 bdf2, u8 pos2, unsigned offs2) ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid, struct sys_info *sysinfo); ./northbridge/amd/k8/incoherent_ht.c:int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned new_bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned max_bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid, struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned uoffs; ./northbridge/amd/k8/incoherent_ht.c: unsigned real_last_unitid; ./northbridge/amd/k8/incoherent_ht.c: unsigned offs; ./northbridge/amd/k8/incoherent_ht.c:void ht_setup_chain(u32 bdf, unsigned upos, struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/incoherent_ht.c: unsigned devn = 1; ./northbridge/amd/k8/incoherent_ht.c:int set_ht_link_buffer_count(u8 node, u8 linkn, u8 linkt, unsigned val) ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c:int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val) ./northbridge/amd/k8/incoherent_ht.c: unsigned devn; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/incoherent_ht.c:unsigned get_nodes(void); ./northbridge/amd/k8/incoherent_ht.c: unsigned next_io_base; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned link_pair_num = sysinfo->link_pair_num; ./northbridge/amd/k8/coherent_ht.c: unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp2(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp4(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp6(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp8(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned verify_mp_capabilities(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node, mask; ./northbridge/amd/k8/coherent_ht.c:void clear_dead_routes(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c:unsigned verify_dualcore(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node, totalcpus, tmp; ./northbridge/amd/k8/coherent_ht.c:void coherent_ht_finalize(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c: unsigned total_cpus; ./northbridge/amd/k8/coherent_ht.c:int apply_cpu_errata_fixes(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c:int optimize_link_read_pointers(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c: unsigned reg; ./northbridge/amd/k8/coherent_ht.c:inline unsigned get_nodes(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/get_sblk_pci1234.c:unsigned node_link_to_bus(unsigned node, unsigned link) ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned reg; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned dst_node; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned dst_link; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned bus_base; ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/raminit.c:static struct dimm_size spd_get_dimm_size(unsigned device) ./northbridge/amd/k8/raminit.c:static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) ./northbridge/amd/k8/raminit.c:static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) ./northbridge/amd/k8/raminit.c: static const unsigned cs_map_aa[] = { ./northbridge/amd/k8/raminit.c: unsigned node_id; ./northbridge/amd/k8/raminit.c: unsigned limit; ./northbridge/amd/k8/raminit.c: unsigned base; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c: unsigned limit_reg, base_reg; ./northbridge/amd/k8/raminit.c:static void set_top_mem(unsigned tom_k, unsigned hole_startk) ./northbridge/amd/k8/raminit.c: unsigned common_size; ./northbridge/amd/k8/raminit.c: unsigned common_cs_mode; ./northbridge/amd/k8/raminit.c: unsigned size; ./northbridge/amd/k8/raminit.c: unsigned cs_mode; ./northbridge/amd/k8/raminit.c: unsigned index, candidate; ./northbridge/amd/k8/raminit.c: unsigned size; ./northbridge/amd/k8/raminit.c: unsigned node_id; ./northbridge/amd/k8/raminit.c: unsigned end_k; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c:static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) ./northbridge/amd/k8/raminit.c: unsigned dimm_mask; ./northbridge/amd/k8/raminit.c: unsigned device; ./northbridge/amd/k8/raminit.c: unsigned device0, device1; ./northbridge/amd/k8/raminit.c: unsigned addr; ./northbridge/amd/k8/raminit.c:static const struct mem_param *get_mem_param(unsigned min_cycle_time) ./northbridge/amd/k8/raminit.c: unsigned min_cycle_time, min_latency, bios_cycle_time; ./northbridge/amd/k8/raminit.c: static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned tref, old_tref; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c: unsigned latency; ./northbridge/amd/k8/raminit.c: unsigned clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks; ./northbridge/amd/k8/raminit.c: unsigned rdpreamble; ./northbridge/amd/k8/raminit.c: unsigned async_lat; ./northbridge/amd/k8/raminit.c:static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) ./northbridge/amd/k8/raminit.c: unsigned base_k; ./northbridge/amd/k8/raminit.c: unsigned base_k, limit_k; ./northbridge/amd/k8/raminit.c: unsigned end_k; ./northbridge/amd/k8/raminit.c:void set_sysinfo_in_ram(unsigned val) ./superio/winbond/w83627hf/superio.c: unsigned hwm_reg_values[] = { ./device/hypertransport.c:static unsigned ht_read_freq_cap(struct device *dev, unsigned pos) ./device/hypertransport.c: unsigned freq_cap; ./device/pci_device.c: unsigned ctl; ./device/pci_device.c: unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) << 8); ./include/uart8250.h:unsigned char uart8250_rx_byte(unsigned base_port); ./include/uart8250.h:int uart8250_can_rx_byte(unsigned base_port); ./include/uart8250.h:void uart8250_tx_byte(unsigned base_port, unsigned char data); ./include/uart8250.h:void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); ./include/device/agp.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/hypertransport.h: unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); ./include/device/device.h: unsigned bridge_ctrl; /* Bridge control register */ ./include/device/device.h: unsigned reset_needed : 1; ./include/device/device.h: unsigned disable_relaxed_ordering : 1; ./include/device/pcix.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/pcix.h:const char *pcix_speed(unsigned sstatus); ./include/device/path.h: unsigned domain; ./include/device/path.h: unsigned bus; ./include/device/path.h: unsigned devfn; ./include/device/path.h: unsigned port; ./include/device/path.h: unsigned device; ./include/device/path.h: unsigned device; ./include/device/path.h: unsigned apic_id; ./include/device/path.h: unsigned node_id; ./include/device/path.h: unsigned core_id; ./include/device/path.h: unsigned cluster; ./include/device/path.h: unsigned id; ./include/device/path.h: unsigned id; ./include/device/path.h: unsigned iobase; ./include/device/pci_ops.h:u8 pci_read_config8(struct device * dev, unsigned where); ./include/device/pci_ops.h:u16 pci_read_config16(struct device * dev, unsigned where); ./include/device/pci_ops.h:u32 pci_read_config32(struct device * dev, unsigned where); ./include/device/pci_ops.h:void pci_write_config8(struct device * dev, unsigned where, u8 val); ./include/device/pci_ops.h:void pci_write_config16(struct device * dev, unsigned where, u16 val); ./include/device/pci_ops.h:void pci_write_config32(struct device * dev, unsigned where, u32 val); ./include/device/pci.h: void (*set_subsystem)(struct device * dev, unsigned vendor, unsigned device); ./include/device/pci.h:struct device * pci_probe_dev(struct device * dev, struct bus *bus, unsigned devfn); ./include/device/pci.h: unsigned min_devfn, unsigned max_devfn, unsigned int max)); ./include/device/pci.h:unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/pci.h:u8 pci_moving_config8(struct device *dev, unsigned reg); ./include/device/pci.h:u16 pci_moving_config16(struct device *dev, unsigned reg); ./include/device/pci.h:u32 pci_moving_config32(struct device *dev, unsigned reg); ./include/device/pci.h:unsigned pci_find_next_capability(struct device * dev, unsigned cap, unsigned last); ./include/device/pci.h:unsigned pci_find_capability(struct device * dev, unsigned cap); ./include/device/pci.h:void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device); ./include/device/pnp.h:void pnp_set_iobase(struct device * dev, unsigned index, unsigned iobase); ./include/device/pnp.h:void pnp_set_irq(struct device * dev, unsigned index, unsigned irq); ./include/device/pnp.h:void pnp_set_drq(struct device * dev, unsigned index, unsigned drq); ./include/device/pnp.h: unsigned mask, set; ./include/device/pnp.h: unsigned function; ./include/device/pnp.h: unsigned flags; ./include/device/pnp.h:struct resource *pnp_get_resource(struct device * dev, unsigned index); ./include/device/pnp.h: unsigned functions, struct pnp_info *info); ./include/device/resource.h:extern struct resource *probe_resource(struct device *dev, unsigned index); ./include/device/resource.h:extern struct resource *new_resource(struct device * dev, unsigned index); ./include/device/resource.h:extern struct resource *find_resource(struct device * dev, unsigned index); ./include/device/pcie.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/cardbus.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/arch/x86/amd/k8/raminit.h: unsigned node_id; ./include/arch/x86/amd/k8/sysconf.h: unsigned nodes; ./include/arch/x86/amd/k8/sysconf.h: unsigned hc_possible_num; ./include/arch/x86/amd/k8/sysconf.h: unsigned pci1234[HC_POSSIBLE_NUM]; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcdn[HC_POSSIBLE_NUM]; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type ./include/arch/x86/amd/k8/sysconf.h: unsigned sbdn; ./include/arch/x86/amd/k8/sysconf.h: unsigned sblk; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234 ./include/arch/x86/amd/k8/sysconf.h: unsigned lift_bsp_apicid; ./include/arch/x86/amd/k8/k8.h: unsigned node_id; ./include/arch/x86/amd/k8/k8.h: unsigned nodeid; ./include/arch/x86/amd/k8/k8.h: unsigned coreid; ./include/arch/x86/amd/k8/k8.h:unsigned get_apicid_base(unsigned ioapic_num); ./include/arch/x86/mtrr.h:void x86_setup_var_mtrrs(unsigned address_bits); ./include/arch/x86/mtrr.h:void x86_setup_mtrrs(unsigned address_bits); ./lib/nrv2b.c: (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) ./lib/nrv2b.c: unsigned bc = 0; ./lib/uart8250.c:static inline int uart8250_can_tx_byte(unsigned base_port) ./lib/uart8250.c:static inline void uart8250_wait_to_tx_byte(unsigned base_port) ./lib/uart8250.c:static inline void uart8250_wait_until_sent(unsigned base_port) ./lib/uart8250.c:void uart8250_tx_byte(unsigned base_port, unsigned char data) ./lib/uart8250.c:int uart8250_can_rx_byte(unsigned base_port) ./lib/uart8250.c:unsigned char uart8250_rx_byte(unsigned base_port) ./lib/uart8250.c:void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs) ./doc/design/newboot.lyx: The simplest function is called smbus_read_byte(unsigned device, unsigned ./arch/x86/resourcemap.c: unsigned where; ./arch/x86/serial.c: unsigned ttysx_div; ./arch/x86/serial.c: unsigned ttysx_index; ./arch/x86/archtables.c: unsigned mptable_size = new_low_table_end - low_table_end - SMP_FLOATING_TABLE_LEN; ./arch/x86/mc146818rtc.c: unsigned sum, old_sum; ./arch/x86/mc146818rtc.c: unsigned sum; ./arch/x86/mc146818rtc.c:unsigned read_option(unsigned start, unsigned size, unsigned def) ./arch/x86/mc146818rtc.c: unsigned byte; ./arch/x86/pci_ops_auto.c: unsigned bus;