<div dir="ltr"><br><br><div class="gmail_quote">On Tue, Oct 21, 2008 at 10:20 AM, Marc Jones <span dir="ltr"><<a href="mailto:Marc.Jones@amd.com">Marc.Jones@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
Myles Watson wrote:<div><div></div><div class="Wj3C7c"><br>
<blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
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On Mon, Oct 20, 2008 at 4:10 PM, Marc Jones <<a href="mailto:Marc.Jones@amd.com" target="_blank">Marc.Jones@amd.com</a> <mailto:<a href="mailto:Marc.Jones@amd.com" target="_blank">Marc.Jones@amd.com</a>>> wrote:<br>
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Myles Watson wrote:<br>
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0 6 0 AMD-8111 PCI<br>
74601022 02300147 06040007 00014000<br>
00000000 00000000 40010100 02001010<br>
FE00FD00 FFE0FFF0 00000000 00000000<br>
00000000 000000C0 00000000 042B00FF<br>
<br>
^<br>
ISA isn't set. That might be a problem.<br>
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I can't tell that v2 ever sets it. In the 8111 datasheet it looks like that bit makes it so that bits 8 & 9 of the address get ignored so that only 256B of every 1024 are accessible. I don't think that's what we want.<br>
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Looking for that I found an interesting couple of defines.<br>
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include/device/pci_def.h:#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */<br>
include/device/pci_def.h:#define PCI_CB_BRIDGE_CTL_ISA 0x04<br>
<br>
I can see that they're used in two different places (one for the hardware, one for the device struct), but it still seems confusing.<br>
</blockquote>
<br></div></div>I think that the problem is probably in the mmio map that Ron posted yesterday. <div><div class="Wj3C7c"></div></div></blockquote><div><br>This is my latest. The one Ron posted was from func 0 just after RAM init. This one is from func 1.<br>
After RAM init: <br>DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0<br>DRAM(48)0000000000-0000ffffff, ->(1), , , No interleave, 0<br>DRAM(50)0000000000-0000ffffff, ->(2), , , No interleave, 0<br>DRAM(58)0000000000-0000ffffff, ->(3), , , No interleave, 0<br>
DRAM(60)0000000000-0000ffffff, ->(4), , , No interleave, 0<br>DRAM(68)0000000000-0000ffffff, ->(5), , , No interleave, 0<br>DRAM(70)0000000000-0000ffffff, ->(6), , , No interleave, 0<br>DRAM(78)0000000000-0000ffffff, ->(7), , , No interleave, 0<br>
MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>MMIO(88)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>
MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>
MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0<br>MMIO(b8)00fc000000-00ffffffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0<br>PCIIO(c0)00000003-01fff000<br>PCIIO(c0)00000000-01fff000, ->(0,0), R, W,VGA 0 ISA 0<br>
PCIIO(c8)00000000-00000000<br>PCIIO(c8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0<br>PCIIO(d0)00000000-00000000<br>PCIIO(d0)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0<br>PCIIO(d8)00000000-00000000<br>PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0<br>
CONFIG(e0)0000003f-00000000 ->(0,0),R W CE 0<br>CONFIG(e4)00000000-00000000 ->(0,0), CE 0<br>CONFIG(e8)00000000-00000000 ->(0,0), CE 0<br>CONFIG(ec)00000000-00000000 ->(0,0), CE 0<br><br>After assign resources ( I took out the ones that were all 0)<br>
DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0<br>MMIO(a8)00000a0000-00000bffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0<br>MMIO(b0)00fd000000-00fe1fffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted 0<br>
PCIIO(c0)00001000-00002000, ->(0,0), R, W,VGA 1 ISA 0<br>CONFIG(e0)00000003-00000000 ->(0,0),R W CE 0<br><br>Thanks,<br>Myles<br></div></div><br></div>