Fixup device tree code. Add/change methods as needed. This should help serengeti.

Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>


Index: southbridge/amd/rs690/ht.c
===================================================================
--- southbridge/amd/rs690/ht.c	(revision 953)
+++ southbridge/amd/rs690/ht.c	(working copy)
@@ -85,9 +85,8 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
 			      .device = PCI_DEVICE_ID_ATI_RS690_HT}}},
 	.constructor		 = default_device_constructor,
-	.phase2_setup_scan_bus = rs690_enable,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable = rs690_enable,
+	.phase3_chip_setup_dev = rs690_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/rs690/pcie.c
===================================================================
--- southbridge/amd/rs690/pcie.c	(revision 953)
+++ southbridge/amd/rs690/pcie.c	(working copy)
@@ -400,7 +400,7 @@
 			      .device = PCI_DEVICE_ID_ATI_RS690_PCIE}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_scan_bridge,
-	.phase4_enable_disable = rs690_enable,
+	.phase3_chip_setup_dev = rs690_enable,
 	.phase4_read_resources	 = pci_bus_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_bus_enable_resources,
Index: southbridge/amd/rs690/gfx.c
===================================================================
--- southbridge/amd/rs690/gfx.c	(revision 953)
+++ southbridge/amd/rs690/gfx.c	(working copy)
@@ -79,13 +79,9 @@
 	struct southbridge_amd_rs690_gfx_config *cfg = dev->device_configuration;
 	deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
 	vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
-	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n",
+	printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%lx.\n",
 	     deviceid, vendorid, cfg->vga_rom_address);
 
-#if 0 /* I think these should be done in Config.lb. Please check it. */
-	dev->on_mainboard = 1;
-	dev->rom_address = cfg->vga_rom_address;	/* 0xfff00000; */
-#endif
 	pci_dev_init(dev);
 
 	/* clk ind */
@@ -569,9 +565,9 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
 			      .device = PCI_DEVICE_ID_ATI_RS690MT_INT_GFX}}},
 	.constructor		 = default_device_constructor,
-	.phase2_setup_scan_bus	= rs690_internal_gfx_enable,
+	.phase3_chip_setup_dev = rs690_enable,
+	.phase3_enable	= rs690_internal_gfx_enable,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable = rs690_enable,
 	.phase4_read_resources	 = rs690_gfx_read_resources,
 	.phase4_set_resources	 = rs690_gfx_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/rs690/gfx.dts
===================================================================
--- southbridge/amd/rs690/gfx.dts	(revision 953)
+++ southbridge/amd/rs690/gfx.dts	(working copy)
@@ -33,7 +33,7 @@
 */
 {
 	device_operations	= "rs690_gfx";
-	vga_rom_address	=	"0xfff00000";		/* The location that the VGA rom has been appened. */
+	vga_rom_address = "0xfff0000";
 	gfx_dev2_dev3 = "1";	/* for GFX Core initialization REFCLK_SEL */
 	gfx_dual_slot = "0";		/* Is it dual graphics slots */
 	gfx_lane_reversal = "0";	/* Single/Dual slot lan reversal */
Index: southbridge/amd/sb600/ide.c
===================================================================
--- southbridge/amd/sb600/ide.c	(revision 953)
+++ southbridge/amd/sb600/ide.c	(working copy)
@@ -70,7 +70,7 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
 			      .device = PCI_DEVICE_ID_ATI_SB600_IDE}}},
 	.constructor		 = default_device_constructor,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/sb600/ac97.c
===================================================================
--- southbridge/amd/sb600/ac97.c	(revision 953)
+++ southbridge/amd/sb600/ac97.c	(working copy)
@@ -38,7 +38,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_ACI}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
@@ -52,7 +52,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_MCI}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/sb600/pci.c
===================================================================
--- southbridge/amd/sb600/pci.c	(revision 953)
+++ southbridge/amd/sb600/pci.c	(working copy)
@@ -130,7 +130,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_PCI}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_scan_bridge,
-	.phase4_enable_disable           = sb600_enable,
+	.phase3_chip_setup_dev           = sb600_enable,
 	.phase4_read_resources	 = pci_bus_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_bus_enable_resources,
Index: southbridge/amd/sb600/lpc.c
===================================================================
--- southbridge/amd/sb600/lpc.c	(revision 953)
+++ southbridge/amd/sb600/lpc.c	(working copy)
@@ -213,7 +213,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_LPC}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan	= scan_static_bus,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = sb600_lpc_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = sb600_lpc_enable_resources,
Index: southbridge/amd/sb600/sm.c
===================================================================
--- southbridge/amd/sb600/sm.c	(revision 953)
+++ southbridge/amd/sb600/sm.c	(working copy)
@@ -395,7 +395,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_SM}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = sb600_sm_read_resources,
 	.phase4_set_resources	 = sb600_sm_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/sb600/sata.c
===================================================================
--- southbridge/amd/sb600/sata.c	(revision 953)
+++ southbridge/amd/sb600/sata.c	(working copy)
@@ -192,7 +192,7 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
 			      .device = PCI_DEVICE_ID_ATI_SB600_SATA}}},
 	.constructor		 = default_device_constructor,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/sb600/usb.c
===================================================================
--- southbridge/amd/sb600/usb.c	(revision 953)
+++ southbridge/amd/sb600/usb.c	(working copy)
@@ -205,7 +205,7 @@
 			      .device = PCI_DEVICE_ID_ATI_SB600_USB2}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = usb_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/sb600/hda.c
===================================================================
--- southbridge/amd/sb600/hda.c	(revision 953)
+++ southbridge/amd/sb600/hda.c	(working copy)
@@ -279,7 +279,7 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_ATI,
 			      .device = PCI_DEVICE_ID_ATI_SB600_HDA}}},
 	.constructor		 = default_device_constructor,
-	.phase4_enable_disable = sb600_enable,
+	.phase3_chip_setup_dev = sb600_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/ide.c
===================================================================
--- southbridge/amd/amd8111/ide.c	(revision 953)
+++ southbridge/amd/amd8111/ide.c	(working copy)
@@ -78,7 +78,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_IDE}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/ac97.c
===================================================================
--- southbridge/amd/amd8111/ac97.c	(revision 953)
+++ southbridge/amd/amd8111/ac97.c	(working copy)
@@ -44,7 +44,7 @@
 			      .device = 0x746D}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
@@ -58,7 +58,7 @@
 			      .device = 0x746E}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/nic.c
===================================================================
--- southbridge/amd/amd8111/nic.c	(revision 953)
+++ southbridge/amd/amd8111/nic.c	(working copy)
@@ -99,7 +99,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_NIC}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = 0,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/usb2.c
===================================================================
--- southbridge/amd/amd8111/usb2.c	(revision 953)
+++ southbridge/amd/amd8111/usb2.c	(working copy)
@@ -49,7 +49,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_USB}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable = amd8111_usb2_enable,
+	.phase3_chip_setup_dev = amd8111_usb2_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/pci.c
===================================================================
--- southbridge/amd/amd8111/pci.c	(revision 953)
+++ southbridge/amd/amd8111/pci.c	(working copy)
@@ -75,7 +75,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_PCI}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_scan_bridge,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_bus_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_bus_enable_resources,
Index: southbridge/amd/amd8111/acpi.c
===================================================================
--- southbridge/amd/amd8111/acpi.c	(revision 953)
+++ southbridge/amd/amd8111/acpi.c	(working copy)
@@ -231,7 +231,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_ACPI}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = acpi_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = acpi_enable_resources,
Index: southbridge/amd/amd8111/lpc.c
===================================================================
--- southbridge/amd/amd8111/lpc.c	(revision 953)
+++ southbridge/amd/amd8111/lpc.c	(working copy)
@@ -213,7 +213,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_ISA}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = amd8111_lpc_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = amd8111_lpc_enable_resources,
Index: southbridge/amd/amd8111/smbus.c
===================================================================
--- southbridge/amd/amd8111/smbus.c	(revision 953)
+++ southbridge/amd/amd8111/smbus.c	(working copy)
@@ -53,7 +53,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_SMB}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/amd/amd8111/usb.c
===================================================================
--- southbridge/amd/amd8111/usb.c	(revision 953)
+++ southbridge/amd/amd8111/usb.c	(working copy)
@@ -50,7 +50,7 @@
 			      .device = PCI_DEVICE_ID_AMD_8111_USB}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = scan_static_bus,
-	.phase4_enable_disable           = amd8111_enable,
+	.phase3_chip_setup_dev           = amd8111_enable,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
 	.phase5_enable_resources = pci_dev_enable_resources,
Index: southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- southbridge/intel/i82371eb/i82371eb.c	(revision 953)
+++ southbridge/intel/i82371eb/i82371eb.c	(working copy)
@@ -90,7 +90,6 @@
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase4_enable_disable	 = 0,
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = i82371eb_isa_init,
 	.ops_pci		 = &pci_dev_ops_pci,
@@ -103,7 +102,6 @@
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase4_enable_disable	 = 0,
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = i82371eb_ide_init,
 	.ops_pci		 = &pci_dev_ops_pci,
@@ -116,7 +114,6 @@
 	.phase3_scan		 = 0,
 	.phase4_read_resources	 = pci_dev_read_resources,
 	.phase4_set_resources	 = pci_dev_set_resources,
-	.phase4_enable_disable	 = 0,
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init		 = i82371eb_acpi_init,
 	.ops_pci		 = &pci_dev_ops_pci,
Index: include/device/device.h
===================================================================
--- include/device/device.h	(revision 953)
+++ include/device/device.h	(working copy)
@@ -143,19 +143,19 @@
 	void (*phase1_set_device_operations)(struct device *dev);
 
 	/* phase 2 is for any magic you have to do before the busses are scanned */
-	void (*phase2_setup_scan_bus)(struct device * dev);
+	void (*phase2_fixup)(struct device * dev);
 
 	/* phase 3 is for scanning the bus, if needed. */
-	void (*phase3_enable_scan)(struct device *dev);
+	void (*phase3_chip_setup_dev)(struct device *dev);
+	/* some devices need to be enabled to scan. */
+	/* this function enables/disables according the value of 'enabled' in the device*/
+	void (*phase3_enable)(struct device * dev);
 	unsigned int (*phase3_scan)(struct device * bus, unsigned int max);
 
 	/* typically used by phase4 */
 	/* again, if we never use this anywhere else, we may change the names */
 	void (*phase4_read_resources)(struct device * dev);
 	void (*phase4_set_resources)(struct device * dev);
-	/* some devices need to be enabled to scan, then disabled again. */
-	/* this function enables/disables according the value of 'enabled' in the device*/
-	void (*phase4_enable_disable)(struct device * dev);
 
 	/* phase 5: enable devices */
 	void (*phase5_enable_resources)(struct device * dev);
Index: superio/winbond/w83627hf/superio.c
===================================================================
--- superio/winbond/w83627hf/superio.c	(revision 953)
+++ superio/winbond/w83627hf/superio.c	(working copy)
@@ -189,12 +189,12 @@
                 pnp_exit_ext_func_mode(dev);  
         }
 }
-static void phase2_setup_scan_bus(struct device *dev);
+static void phase3_chip_setup_dev(struct device *dev);
 struct device_operations w83627hf_ops = {
-	.phase2_setup_scan_bus = phase2_setup_scan_bus,
+	.phase3_chip_setup_dev = phase3_chip_setup_dev,
+	.phase3_enable   = w83627hf_pnp_enable_resources,
 	.phase4_read_resources   = pnp_read_resources,
 	.phase4_set_resources    = w83627hf_pnp_set_resources,
-	.phase4_enable_disable   = w83627hf_pnp_enable_resources,
 	.phase5_enable_resources = w83627hf_pnp_enable,
 	.phase6_init             = w83627hf_init,
 };
@@ -215,7 +215,7 @@
 };
 
 
-static void phase2_setup_scan_bus(struct device *dev)
+static void phase3_chip_setup_dev(struct device *dev)
 {
 	pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
 }
Index: superio/ite/it8712f/superio.c
===================================================================
--- superio/ite/it8712f/superio.c	(revision 953)
+++ superio/ite/it8712f/superio.c	(working copy)
@@ -105,10 +105,10 @@
 static void it8712f_setup_scan_bus(struct device *dev);
 
 struct device_operations it8712f_ops = {
-	.phase2_setup_scan_bus	 = it8712f_setup_scan_bus,
+	.phase3_chip_setup_dev	 = it8712f_setup_scan_bus,
+	.phase3_enable	 = it8712f_pnp_enable_resources,
 	.phase4_read_resources	 = pnp_read_resources,
 	.phase4_set_resources	 = it8712f_pnp_set_resources,
-	.phase4_enable_disable	 = it8712f_pnp_enable_resources,
 	.phase5_enable_resources = it8712f_pnp_enable,
 	.phase6_init		 = it8712f_init,
 };
Index: mainboard/amd/serengeti/dts
===================================================================
--- mainboard/amd/serengeti/dts	(revision 953)
+++ mainboard/amd/serengeti/dts	(working copy)
@@ -46,7 +46,6 @@
 					/config/("southbridge/amd/amd8111/usb2.dts");
 				};
 				pci@4,0{
-					rom_address = "0xfc000000";
 				};
 			};
 			pci@7,0 {
Index: mainboard/amd/dbm690t/mainboard.c
===================================================================
--- mainboard/amd/dbm690t/mainboard.c	(revision 953)
+++ mainboard/amd/dbm690t/mainboard.c	(working copy)
@@ -129,5 +129,5 @@
 		{.pci = {.vendor = PCI_VENDOR_ID_AMD,
 			      .device = 1}}},
 	.constructor		 = default_device_constructor,
-	.phase3_enable_scan = dbm690t_enable,
+	.phase3_chip_setup_dev = dbm690t_enable,
 };
Index: mainboard/emulation/qemu-x86/vga.c
===================================================================
--- mainboard/emulation/qemu-x86/vga.c	(revision 953)
+++ mainboard/emulation/qemu-x86/vga.c	(working copy)
@@ -40,6 +40,8 @@
 	 * but since QEMU has no Super I/O...
 	 */
 	init_pc_keyboard(0x60, 0x64, &conf);
+	/* now run the rom */
+	pci_dev_init(dev);
 }
 
 struct device_operations qemuvga_pci_ops_dev = {
@@ -50,9 +52,8 @@
 	.phase3_scan			= 0,
 	.phase4_read_resources		= pci_dev_read_resources,
 	.phase4_set_resources		= pci_dev_set_resources,
-	.phase4_enable_disable		= setup_onboard,
 	.phase5_enable_resources	= pci_dev_enable_resources,
-	.phase6_init			= pci_dev_init,
+	.phase6_init			= setup_onboard,
 	.ops_pci			= &pci_dev_ops_pci,
 };
 
Index: device/device.c
===================================================================
--- device/device.c	(revision 953)
+++ device/device.c	(working copy)
@@ -754,14 +754,14 @@
 	printk(BIOS_DEBUG, "Phase 2: Early setup...\n");
 	for (dev = all_devices; dev; dev = dev->next) {
 		printk(BIOS_SPEW,
-			"%s: dev %s: ops %p ops->phase2_setup_scan_bus %p\n",
+			"%s: dev %s: ops %p ops->phase2_fixup %p\n",
 			__FUNCTION__, dev->dtsname, dev->ops, 
-			dev->ops? dev->ops->phase2_setup_scan_bus : NULL);
-		if (dev->ops && dev->ops->phase2_setup_scan_bus) {
+			dev->ops? dev->ops->phase2_fixup : NULL);
+		if (dev->ops && dev->ops->phase2_fixup) {
 			printk(BIOS_SPEW,
-			       "Calling phase2 phase2_setup_scan_bus...\n");
-			dev->ops->phase2_setup_scan_bus(dev);
-			printk(BIOS_SPEW, "phase2_setup_scan_bus done\n");
+			       "Calling phase2 phase2_fixup...\n");
+			dev->ops->phase2_fixup(dev);
+			printk(BIOS_SPEW, "phase2_fixup done\n");
 		}
 	}
 
@@ -797,14 +797,12 @@
 		return max;
 	}
 
-	if (busdevice->ops->phase3_enable_scan)
-		busdevice->ops->phase3_enable_scan(busdevice);
-
 	do_phase3 = 1;
 	while (do_phase3) {
 		int link;
 		printk(BIOS_INFO, "%s: scanning %s(%s)\n", __FUNCTION__,
 		       busdevice->dtsname, dev_path(busdevice));
+#warning do we call phase3_enable here. 
 		new_max = busdevice->ops->phase3_scan(busdevice, max);
 		do_phase3 = 0;
 		for (link = 0; link < busdevice->links; link++) {
@@ -853,8 +851,8 @@
 	printk(BIOS_INFO, "Phase 3: Enumerating buses...\n");
 	root = &dev_root;
 
-	if (root->ops && root->ops->phase3_enable_scan) {
-		root->ops->phase3_enable_scan(root);
+	if (root->ops && root->ops->phase3_chip_setup_dev) {
+		root->ops->phase3_chip_setup_dev(root);
 	}
 	post_code(POST_STAGE2_PHASE3_MIDDLE);
 	if (!root->ops) {
Index: device/root_device.c
===================================================================
--- device/root_device.c	(revision 953)
+++ device/root_device.c	(working copy)
@@ -119,12 +119,12 @@
 		}
 		for (child = busdevice->link[link].children; child;
 		     child = child->sibling) {
-			if (child->ops && child->ops->phase3_enable_scan) {
-				child->ops->phase3_enable_scan(child);
+			if (child->ops && child->ops->phase3_chip_setup_dev) {
+				child->ops->phase3_chip_setup_dev(child);
 			}
 			/* Sigh. Have to enable to scan... */
-			if (child->ops && child->ops->phase5_enable_resources) {
-				child->ops->phase5_enable_resources(child);
+			if (child->ops && child->ops->phase3_enable) {
+				child->ops->phase3_enable(child);
 			}
 			if (child->path.type == DEVICE_PATH_I2C) {
 				printk(BIOS_DEBUG, "smbus: %s(%s)[%d]->",
@@ -217,11 +217,11 @@
  * mainboard directory. 
  */
 struct device_operations default_dev_ops_root = {
+	.phase3_scan             = root_dev_scan_bus,
 	.phase4_read_resources   = root_dev_read_resources,
 	.phase4_set_resources    = root_dev_set_resources,
 	.phase5_enable_resources = root_dev_enable_resources,
 	.phase6_init             = root_dev_init,
-	.phase3_scan             = root_dev_scan_bus,
 	.reset_bus               = root_dev_reset,
 };
 
Index: device/pci_rom.c
===================================================================
--- device/pci_rom.c	(revision 953)
+++ device/pci_rom.c	(working copy)
@@ -108,7 +108,8 @@
 	rom_data = (struct pci_data *)((unsigned char *)rom_header +
 				       le32_to_cpu(rom_header->data));
 
-	printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
+	printk(BIOS_SPEW, "PCI ROM Image, @%p, Vendor %04x, Device %04x,\n",
+		&rom_data->vendor,
 	       rom_data->vendor, rom_data->device);
 	if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) {
 		printk(BIOS_ERR,
Index: device/pci_device.c
===================================================================
--- device/pci_device.c	(revision 953)
+++ device/pci_device.c	(working copy)
@@ -739,7 +739,6 @@
 	.phase5_enable_resources = pci_dev_enable_resources,
 	.phase6_init             = pci_dev_init,
 	.phase3_scan             = 0,
-	.phase4_enable_disable   = 0,
 	.ops_pci                 = &pci_dev_ops_pci,
 };
 
@@ -749,12 +748,11 @@
 };
 
 struct device_operations default_pci_ops_bus = {
+	.phase3_scan             = pci_scan_bridge,
 	.phase4_read_resources   = pci_bus_read_resources,
 	.phase4_set_resources    = pci_dev_set_resources,
 	.phase5_enable_resources = pci_bus_enable_resources,
 	.phase6_init             = 0,
-	.phase3_scan             = pci_scan_bridge,
-	.phase4_enable_disable   = 0,
 	.reset_bus               = pci_bus_reset,
 	.ops_pci                 = &pci_bus_ops_pci,
 };
@@ -1006,8 +1004,8 @@
 		 * it may be absent and enable_dev() must cope.
 		 */
 		/* Run the magic enable sequence for the device. */
-		if (dev->ops && dev->ops->phase3_enable_scan) {
-			dev->ops->phase3_enable_scan(dev);
+		if (dev->ops && dev->ops->phase3_chip_setup_dev) {
+			dev->ops->phase3_chip_setup_dev(dev);
 		}
 		/* Now read the vendor and device ID. */
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -1062,8 +1060,8 @@
 	set_pci_ops(dev);
 
 	/* Now run the magic enable/disable sequence for the device. */
-	if (dev->ops && dev->ops->phase4_enable_disable) {
-		dev->ops->phase4_enable_disable(dev);
+	if (dev->ops && dev->ops->phase3_enable) {
+		dev->ops->phase3_enable(dev);
 	}
 
 	/* Display the device and error if we don't have some PCI operations
Index: northbridge/amd/geodelx/geodelx.c
===================================================================
--- northbridge/amd/geodelx/geodelx.c	(revision 953)
+++ northbridge/amd/geodelx/geodelx.c	(working copy)
@@ -227,7 +227,7 @@
 		{.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
 				     .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
 	.constructor			= default_device_constructor,
-	.phase2_setup_scan_bus		= geodelx_pci_domain_phase2,
+	.phase2_fixup		= geodelx_pci_domain_phase2,
 	.phase3_scan			= pci_domain_scan_bus,
 	.phase4_read_resources		= pci_domain_read_resources,
 	.phase4_set_resources		= geodelx_pci_domain_set_resources,
