PROBE works better with the 2nd fix (ich7 instead of ich_dc)
READ/WRITE looks to work fine
ERASE not tested

Some modifications I added in flashrom code to have this work :
1) ST M25P16 works better with ich7 on EP80579
2) Initialize tmp to avoid garbage in the variable.

----------------------------------------------------------------------------------
diff -c flashrom-V2-3695/chipset_enable.c flashrom/chipset_enable.c
*** flashrom-V2-3695/chipset_enable.c   Sun Oct 26 19:40:42 2008
--- flashrom/chipset_enable.c   Tue Oct 28 14:47:28 2008
***************
*** 765,771 ****
        {0x8086, 0x25a1, "Intel 6300ESB",       enable_flash_ich_4e},
        {0x8086, 0x2640, "Intel ICH6/ICH6R",    enable_flash_ich_dc},
        {0x8086, 0x2641, "Intel ICH6-M",        enable_flash_ich_dc},
!       {0x8086, 0x5031, "Intel EP80579",       enable_flash_ich_dc},
        {0x8086, 0x27b0, "Intel ICH7DH",        enable_flash_ich7},
        {0x8086, 0x27b8, "Intel ICH7/ICH7R",    enable_flash_ich7},
        {0x8086, 0x27b9, "Intel ICH7M",         enable_flash_ich7},
--- 765,771 ----
        {0x8086, 0x25a1, "Intel 6300ESB",       enable_flash_ich_4e},
        {0x8086, 0x2640, "Intel ICH6/ICH6R",    enable_flash_ich_dc},
        {0x8086, 0x2641, "Intel ICH6-M",        enable_flash_ich_dc},
!       {0x8086, 0x5031, "Intel EP80579",       enable_flash_ich7},
        {0x8086, 0x27b0, "Intel ICH7DH",        enable_flash_ich7},
        {0x8086, 0x27b8, "Intel ICH7/ICH7R",    enable_flash_ich7},
        {0x8086, 0x27b9, "Intel ICH7M",         enable_flash_ich7},
----------------------------------------------------------------------------------
diff -c flashrom-V2-3695/board_enable.c flashrom/board_enable.c
*** flashrom-V2-3695/board_enable.c     Sat Oct 18 23:14:13 2008
--- flashrom/board_enable.c     Mon Oct 27 19:02:12 2008
***************
*** 250,256 ****
   */
  static int board_asus_p5a(const char *name)
  {
!       uint8_t tmp;
        int i;
  
  #define ASUSP5A_LOOP 5000
--- 250,256 ----
   */
  static int board_asus_p5a(const char *name)
  {
!       uint8_t tmp = 0;
        int i;
  
  #define ASUSP5A_LOOP 5000
----------------------------------------------------------------------------------
[root@lion04 root]# flashrom --read flash_content.rom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Reading Flash...done
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 root]# flashrom --write 0ABPT907.ROM 
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Programming page: 
DONE BLOCK 0x0
DONE BLOCK 0x10000
DONE BLOCK 0x20000
DONE BLOCK 0x30000
DONE BLOCK 0x40000
DONE BLOCK 0x50000
DONE BLOCK 0x60000
DONE BLOCK 0x70000
DONE BLOCK 0x80000
DONE BLOCK 0x90000
DONE BLOCK 0xa0000
DONE BLOCK 0xb0000
DONE BLOCK 0xc0000
DONE BLOCK 0xd0000
DONE BLOCK 0xe0000
DONE BLOCK 0xf0000
DONE BLOCK 0x100000
DONE BLOCK 0x110000
DONE BLOCK 0x120000
DONE BLOCK 0x130000
DONE BLOCK 0x140000
DONE BLOCK 0x150000
DONE BLOCK 0x160000
DONE BLOCK 0x170000
DONE BLOCK 0x180000
DONE BLOCK 0x190000
DONE BLOCK 0x1a0000
DONE BLOCK 0x1b0000
DONE BLOCK 0x1c0000
DONE BLOCK 0x1d0000
DONE BLOCK 0x1e0000
DONE BLOCK 0x1f0000

[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --verify 0ABPT907.ROM 
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.          
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --verify flash_content.rom 
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... FAILED!  Expected=0x4e, Read=0xff
[root@lion04 root]#
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --erase
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Erasing flash chip.
[root@lion04 root]# 
----------------------------------------------------------------------------------
[root@lion04 BIOS_AMI]# flashrom --read zero.rom
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel EP80579", enabling flash write... OK.
Found chip "ST M25P16" (2048 KB) at physical address 0xffe00000.
===
This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE
Please email a report to flashrom@coreboot.org if any of the above operations
work correctly for you with this flash part. Please include the full output
from the program, including chipset found. Thank you for your help!
===
Reading Flash...done
[root@lion04 BIOS_AMI]# hexdump zero.rom 
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
[root@lion04 root]#