Partial support for cn700 stage2. Onboard VGA will almost definitely not work,
and the apic/cpu bus devices may be wrong. WIP.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>

Index: include/device/pci_ids.h
===================================================================
--- include/device/pci_ids.h	(revision 961)
+++ include/device/pci_ids.h	(working copy)
@@ -264,6 +264,14 @@
 #define PCI_DEVICE_ID_NVIDIA_MCP55_PMU          0x036B
 
 #define PCI_VENDOR_ID_VIA			0x1106
+#define PCI_DEVICE_ID_VIA_CN700_AGP		0x0314
+#define PCI_DEVICE_ID_VIA_CN700_ERR		0x1314
+#define PCI_DEVICE_ID_VIA_CN700_HOST		0x2314
+#define PCI_DEVICE_ID_VIA_CN700_MEMCTRL		0x3208
+#define PCI_DEVICE_ID_VIA_CN700_PM		0x4314
+#define PCI_DEVICE_ID_VIA_CN700_VLINK		0x7314
+#define PCI_DEVICE_ID_VIA_CN700_BRIDGE		0xB198
+#define PCI_DEVICE_ID_VIA_CN700_VGA		0x3344
 #define PCI_DEVICE_ID_VIA_VT8237_EHCI		0x3104
 #define PCI_DEVICE_ID_VIA_VT8237_LAN		0x3065
 #define PCI_DEVICE_ID_VIA_VT8237R_LPC		0x3227
Index: northbridge/via/cn700/agp.dts
===================================================================
Index: northbridge/via/cn700/memctrl.c
===================================================================
--- northbridge/via/cn700/memctrl.c	(revision 0)
+++ northbridge/via/cn700/memctrl.c	(revision 0)
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "cn700.h"
+
+static void memctrl_init(struct device *dev)
+{
+	struct device *vlink_dev;
+	u16 reg16;
+	u8 ranks, pagec, paged, pagee, pagef, shadowreg;
+
+	/* Set up the VGA framebuffer size. */
+	reg16 = (log2(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15);
+	pci_write_config16(dev, 0xa0, reg16);
+
+	/* Set up VGA timers. */
+	pci_write_config8(dev, 0xa2, 0x44);
+
+	for (ranks = 0x4b; ranks >= 0x48; ranks--) {
+		if (pci_read_config8(dev, ranks)) {
+			ranks -= 0x48;
+			break;
+		}
+	}
+	if (ranks == 0x47)
+		ranks = 0x00;
+	reg16 = 0xaae0;
+	reg16 |= ranks;
+	/* GMINT Misc. FrameBuffer rank */
+	pci_write_config16(dev, 0xb0, reg16);
+	/* AGPCINT Misc. */
+	pci_write_config8(dev, 0xb8, 0x08);
+
+	/* TODO: This doesn't belong here. At the very least make it a dts
+	 * option */
+
+	/* Shadow RAM */
+	pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30;
+	/* PAGE C, D, E are all read write enable */
+	pci_write_config8(dev, 0x80, pagec);
+	pci_write_config8(dev, 0x81, paged);
+	pci_write_config8(dev, 0x82, pagee);
+	/* PAGE F are read/writable */
+	shadowreg = pci_read_config8(dev, 0x83);
+	shadowreg |= pagef;
+	pci_write_config8(dev, 0x83, shadowreg);
+	/* vlink mirror */
+	vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+				    PCI_DEVICE_ID_VIA_CN700_VLINK, 0);
+	if (vlink_dev) {
+		pci_write_config8(vlink_dev, 0x61, pagec);
+		pci_write_config8(vlink_dev, 0x62, paged);
+		pci_write_config8(vlink_dev, 0x64, pagee);
+
+		shadowreg = pci_read_config8(vlink_dev, 0x63);
+		shadowreg |= pagef;
+		pci_write_config8(vlink_dev, 0x63, shadowreg);
+	}
+}
+
+static const struct device_operations memctrl_operations = {
+	.read_resources = cn700_noop,
+	.init           = memctrl_init,
+};
+
+static const struct pci_driver memctrl_driver __pci_driver = {
+	.ops    = &memctrl_operations,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
+};
Index: northbridge/via/cn700/pci.dts
===================================================================
Index: northbridge/via/cn700/stage2.c
===================================================================
--- northbridge/via/cn700/stage2.c	(revision 0)
+++ northbridge/via/cn700/stage2.c	(revision 0)
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <io.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+#include <statictree.h>
+#include <config.h>
+
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+	struct resource **best_p = gp;
+	struct resource *best;
+
+	best = *best_p;
+	if (!best || (best->base > new->base))
+		best = new;
+	*best_p = best;
+}
+
+static u32 find_pci_tolm(struct bus *bus)
+{
+	struct resource *min;
+	u32 tolm;
+
+	printk(BIOS_DEBUG, "Entering find_pci_tolm\n");
+
+	min = 0;
+	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM,
+			     tolm_test, &min);
+	tolm = 0xffffffffUL;
+	if (min && tolm > min->base)
+		tolm = min->base;
+
+	printk(BIOS_DEBUG, "Leaving find_pci_tolm\n");
+
+	return tolm;
+}
+
+static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40};
+
+static void pci_domain_set_resources(struct device *dev)
+{
+	struct device *mc_dev;
+	u32 pci_tolm;
+
+	printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n");
+
+	pci_tolm = find_pci_tolm(&dev->link[0]);
+	mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA,
+				 PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0);
+
+	if (mc_dev) {
+		u32 tomk, tolmk;
+		u8 rambits;
+		int i, idx;
+
+		/*
+		 * Once the register value is not zero, the RAM size is
+		 * this register's value multiply 64 * 1024 * 1024.
+		 */
+		for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
+			rambits = pci_read_config8(mc_dev, ramregs[i]);
+			if (rambits != 0)
+				break;
+		}
+
+		tomk = rambits * 64 * 1024;
+		printk(BIOS_SPEW, "tomk is 0x%x\n", tomk);
+		/* Compute the Top Of Low Memory (TOLM), in Kb. */
+		tolmk = pci_tolm >> 10;
+		if (tolmk >= tomk) {
+			/* The PCI hole does does not overlap the memory. */
+			tolmk = tomk;
+		}
+		/* Report the memory regions. */
+		idx = 10;
+		/* TODO: Hole needed? */
+		ram_resource(dev, idx++, 0, 640);	/* First 640k */
+		/* Leave a hole for VGA, 0xa0000 - 0xc0000 */
+		ram_resource(dev, idx++, 768,
+			     (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024));
+	}
+	phase4_assign_resources(&dev->link[0]);
+}
+
+static void cpu_bus_init(struct device *dev)
+{
+#warning "cpu_bus_init() empty, what should it do?"
+	printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
+	printk(BIOS_SPEW, ">> Exiting northbridge.c: %s\n", __FUNCTION__);
+}
+
+static void cpu_bus_noop(struct device *dev)
+{
+}
+
+/** Operations for when the northbridge is running a PCI domain. */
+struct device_operations cn700_north_domain = {
+	.id = {.type = DEVICE_ID_PCI_DOMAIN,
+		{.pci_domain = {.vendor = PCI_VENDOR_ID_VIA,
+				     .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= pci_domain_scan_bus,
+	.phase4_read_resources		= pci_domain_read_resources,
+	.phase4_set_resources		= pci_domain_set_resources,
+	.phase5_enable_resources	= enable_childrens_resources,
+	.phase6_init			= 0,
+};
+
+/** Operations for when the northbridge is running an APIC cluster. */
+struct device_operations cn700_north_apic = {
+	.id = {.type = DEVICE_ID_APIC_CLUSTER,
+		{.apic_cluster = {.vendor = PCI_VENDOR_ID_VIA,
+				       .device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= cpu_bus_noop,
+	.phase4_set_resources		= cpu_bus_noop,
+	.phase5_enable_resources	= cpu_bus_noop,
+	.phase6_init			= cpu_bus_init,
+};
Index: northbridge/via/cn700/agp.c
===================================================================
--- northbridge/via/cn700/agp.c	(revision 0)
+++ northbridge/via/cn700/agp.c	(revision 0)
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <console.h>
+#include <io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "cn700.h"
+
+/* This is the main AGP device, and only one used when configured for AGP 2.0 */
+static void agp_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Some of this may not be necessary (should be handled by the OS). */
+	printk(BIOS_DEBUG, "Enabling AGP.\n");
+
+	/* Allow R/W access to AGP registers. */
+	pci_write_config8(dev, 0x4d, 0x15);
+
+	/* Setup PCI latency timer. */
+	pci_write_config8(dev, 0xd, 0x8);
+
+	/*
+	 * Set to AGP 3.0 Mode, which should theoretically render the rest of
+	 * the registers set here pointless.
+	 */
+	pci_write_config8(dev, 0x84, 0xb);
+
+	/* AGP Request Queue Size */
+	pci_write_config8(dev, 0x4a, 0x1f);
+
+	/*
+	 * AGP Hardware Support (default 0xc4)
+	 * 7: AGP SBA Enable (1 to Enable)
+	 * 6: AGP Enable
+	 * 5: Reserved
+	 * 4: Fast Write Enable
+	 * 3: AGP8X Mode Enable
+	 * 2: AGP4X Mode Enable
+	 * 1: AGP2X Mode Enable
+	 * 0: AGP1X Mode Enable
+	 */
+	pci_write_config8(dev, 0x4b, 0xc4);
+
+	/* Enable AGP Backdoor */
+	pci_write_config8(dev, 0xb5, 0x03);
+
+	/* Set aperture to 32 MB. */
+	/* TODO: Use config option, explain how it works. */
+	pci_write_config32(dev, 0x94, 0x00010f38);
+	/* Set GART Table Base Address (31:12). */
+	pci_write_config32(dev, 0x98, (0x1558 << 12));
+	/* Set AGP Aperture Base. */
+	pci_write_config32(dev, 0x10, 0xf8000008);
+
+	/* Enable CPU/PMSTR GART Access. */
+	reg32 = pci_read_config8(dev, 0xbf);
+	reg32 |= 0x80;
+	pci_write_config8(dev, 0xbf, reg32);
+
+	/* Enable AGP Aperture. */
+	reg32 = pci_read_config32(dev, 0x94);
+	reg32 |= (3 << 7);
+	pci_write_config32(dev, 0x90, reg32);
+
+	/* AGP Control */
+	pci_write_config8(dev, 0xbc, 0x21);
+	pci_write_config8(dev, 0xbd, 0xd2);
+
+	/*
+	 * AGP Pad, driving strength, and delay control. All this should be
+	 * constant, seeing as the VGA controller is onboard.
+	 */
+	pci_write_config8(dev, 0x40, 0xc7);
+	pci_write_config8(dev, 0x41, 0xdb);
+	pci_write_config8(dev, 0x42, 0x10);
+	pci_write_config8(dev, 0x43, 0xdb);
+	pci_write_config8(dev, 0x44, 0x24);
+
+	/* AGPC CKG Control */
+	pci_write_config8(dev, 0xc0, 0x02);
+	pci_write_config8(dev, 0xc1, 0x02);
+}
+
+struct device_operations cn700_agp = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
+				.device = PCI_DEVICE_ID_VIA_CN700_AGP}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= 0,
+	.phase4_read_resources		= pci_dev_read_resources,
+	//.phase4_set_resources		= pci_dev_set_resources,
+	//.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= agp_init,
+};
Index: northbridge/via/cn700/stage2.h
===================================================================
--- northbridge/via/cn700/stage2.h	(revision 0)
+++ northbridge/via/cn700/stage2.h	(revision 0)
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_VIA_CN700_STAGE2_H
+#define NORTHBRIDGE_VIA_CN700_STAGE2_H
+
+extern unsigned int cn700_scan_root_bus(device_t root, unsigned int max);
+
+#endif
Index: northbridge/via/cn700/memctrl.dts
===================================================================
Index: northbridge/via/cn700/pci.c
===================================================================
--- northbridge/via/cn700/pci.c	(revision 0)
+++ northbridge/via/cn700/pci.c	(revision 0)
@@ -0,0 +1,61 @@
+#include <types.h>
+#include <console.h>
+#include <io.h>
+#include <lib.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/x86/cpu.h>
+#include <statictree.h>
+#include <config.h>
+#include "cn700.h"
+
+/*
+ * This is the AGP 3.0 and PCI bridge @B0 Device 1 Func 0. When using AGP 3.0, the
+ * config in this device takes presidence. We configure both just to be safe.
+ */
+static void pci_bridge_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "Setting up AGP bridge device\n");
+
+	pci_write_config16(dev, 0x4, 0x0007);
+
+	/* Secondary Bus Number */
+	pci_write_config8(dev, 0x19, 0x01);
+	/* Subordinate Bus Number */
+	pci_write_config8(dev, 0x1a, 0x01);
+	/* I/O Base */
+	pci_write_config8(dev, 0x1c, 0xd0);
+	/* I/O Limit */
+	pci_write_config8(dev, 0x1d, 0xd0);
+
+	/* Memory Base */
+	pci_write_config16(dev, 0x20, 0xfb00);
+	/* Memory Limit */
+	pci_write_config16(dev, 0x22, 0xfcf0);
+	/* Prefetchable Memory Base */
+	pci_write_config16(dev, 0x24, 0xf400);
+	/* Prefetchable Memory Limit */
+	pci_write_config16(dev, 0x26, 0xf7f0);
+	/* Enable VGA Compatible Memory/IO Range */
+	pci_write_config8(dev, 0x3e, 0x08);
+
+	/* Second PCI Bus Control (see datasheet) */
+	pci_write_config8(dev, 0x40, 0x83);
+	pci_write_config8(dev, 0x41, 0x43);
+	pci_write_config8(dev, 0x42, 0xe2);
+	pci_write_config8(dev, 0x43, 0x44);
+	pci_write_config8(dev, 0x44, 0x34);
+	pci_write_config8(dev, 0x45, 0x72);
+}
+
+struct device_operations cn700_pci_bridge = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
+				.device = PCI_DEVICE_ID_VIA_CN700_BRIDGE}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= pci_scan_bridge,
+	.phase4_read_resources		= pci_dev_read_resources,
+	//.phase4_set_resources		= pci_dev_set_resources,
+	//.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= pci_bridge_init,
+};
Index: northbridge/via/cn700/Makefile
===================================================================
--- northbridge/via/cn700/Makefile	(revision 961)
+++ northbridge/via/cn700/Makefile	(working copy)
@@ -20,6 +20,9 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_VIA_CN700),y)
 
-STAGE2_CHIPSET_SRC += 	
+STAGE2_CHIPSET_SRC += 	$(src)/northbridge/via/cn700/stage2.c \
+			$(src)/northbridge/via/cn700/agp.c \
+			$(src)/northbridge/via/cn700/pci.c \
+			$(src)/northbridge/via/cn700/vga.c
 
 endif
Index: northbridge/via/cn700/cn700.h
===================================================================
--- northbridge/via/cn700/cn700.h	(revision 961)
+++ northbridge/via/cn700/cn700.h	(working copy)
@@ -18,8 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#ifndef NORTHBRIDGE_VIA_CN700_CN700_H
+#define NORTHBRIDGE_VIA_CN700_CN700_H
+
 #include <types.h>
- 
+
 struct board_info {
 	u32 d0f2, d0f3, d0f4, d0f7, d1f0;
 	u16 spd_channel0[2];
@@ -59,3 +62,5 @@
 #define RAM_COMMAND_PRECHARGE	0x2
 #define RAM_COMMAND_MRS		0x3
 #define RAM_COMMAND_CBR		0x4
+
+#endif
Index: northbridge/via/cn700/stage2.dts
===================================================================
Index: northbridge/via/cn700/vga.c
===================================================================
--- northbridge/via/cn700/vga.c	(revision 0)
+++ northbridge/via/cn700/vga.c	(revision 0)
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console.h>
+#include <io.h>
+#include <types.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include <config.h>
+#include "cn700.h"
+
+void write_protect_vgabios(void)
+{
+	/* Don't bother for now. */
+#warning "CN700 VGA BIOS write protect needs to be completed"
+}
+
+static void vga_init(struct device *dev)
+{
+	u8 reg8;
+
+	printk(BIOS_DEBUG, "Initializing VGA\n");
+
+	/* Set memory rate to 200 MHz. */
+	outb(0x3d, CRTM_INDEX);
+	reg8 = inb(CRTM_DATA);
+	reg8 &= 0x0f;
+	reg8 |= (0x1 << 4);
+	outb(0x3d, CRTM_INDEX);
+	outb(reg8, CRTM_DATA);
+
+	/* Set framebuffer size. */
+	reg8 = (CONFIG_CN700_VIDEO_MB_32 / 4);
+	outb(0x39, SR_INDEX);
+	outb(reg8, SR_DATA);
+
+	pci_write_config8(dev, 0x04, 0x07);
+	pci_write_config8(dev, 0x0d, 0x20);
+	/* TODO: IIRC these need to be fixed for different VGA memory sizes */
+	pci_write_config32(dev, 0x10, 0xf4000008);
+	pci_write_config32(dev, 0x14, 0xfb000000);
+}
+
+static void vga_read_resources(struct device *dev)
+{
+	dev->rom_address = (0xffffffff - (u32)(1024 * CONFIG_COREBOOT_ROMSIZE_KB - 1)); 
+	dev->on_mainboard = 1;
+	pci_dev_read_resources(dev);
+}
+
+struct device_operations cn700_vga = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = PCI_VENDOR_ID_VIA,
+				.device = PCI_DEVICE_ID_VIA_CN700_VGA}}},
+	.constructor			= default_device_constructor,
+	.phase3_scan			= scan_static_bus,
+	.phase4_read_resources		= vga_read_resources,
+	.phase4_set_resources		= pci_dev_set_resources,
+	.phase5_enable_resources	= pci_dev_enable_resources,
+	.phase6_init			= vga_init,
+};
