Fixes to AMD MCT code, found by Marco Schmidt <mschmidt@dspace.de>

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Index: src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- src/northbridge/amd/amdmct/mct/mct_d.c	(revision 3796)
+++ src/northbridge/amd/amdmct/mct/mct_d.c	(working copy)
@@ -3400,6 +3400,8 @@
 	u8 max_dimms;
 
 	// FIXME: skip for Ax
+	
+	dev = pDCTstat->dev_dct;
 
 	/* Tri-state unused ODTs when motherboard termination is available */
 	max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- src/northbridge/amd/amdmct/wrappers/mcti_d.c	(revision 3796)
+++ src/northbridge/amd/amdmct/wrappers/mcti_d.c	(working copy)
@@ -197,13 +197,16 @@
 	case NV_CS_SpareCTL:
 		val = 0;	/* Disabled */
 		//val = 1;	/* Enabled */
+		break;
 	case NV_SyncOnUnEccEn:
 		val = 0;	/* Disabled */
 		//val = 1;	/* Enabled */
+		break;
 	case NV_Unganged:
 		/* channel interleave is better performance than ganged mode at this time */
 		val = 1;		/* Enabled */
 		//val = 0;	/* Disabled */
+		break;
 	case NV_ChannelIntlv:
 		val = 5;	/* Not currently checked in mctchi_d.c */
 	/* Bit 0 =     0 - Disable
@@ -213,7 +216,7 @@
 	 *             10b - Hash*, XOR of address bits [20:16, 6]
 	 *             11b - Hash*, XOR of address bits [20:16, 9]
 	 */
-
+		break;
 	}
 
 	return val;
