Clean up vt8237 and cn700 stage1 code, and make it easier to read. Will probably
break via/epia-cn target build.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>

Index: southbridge/via/vt8237/vt8237.h
===================================================================
--- southbridge/via/vt8237/vt8237.h	(revision 1066)
+++ southbridge/via/vt8237/vt8237.h	(working copy)
@@ -77,6 +77,7 @@
 } __attribute__ ((packed));
 
 void enable_smbus(u16);
+void vt8237_stage1(u16);
 u8 smbus_read_byte(u16, u8, u16);
 void vt8237_enable(struct device *);
 
Index: southbridge/via/vt8237/stage1.c
===================================================================
--- southbridge/via/vt8237/stage1.c	(revision 1066)
+++ southbridge/via/vt8237/stage1.c	(working copy)
@@ -189,6 +189,42 @@
 	inb(smbus_io_base + SMBHSTCTL);
 }
 
+void vt8237_stage1(u16 smbus_io_base)
+{
+	u32 dev;
+	u32 ide_dev;
+	
+	printk(BIOS_DEBUG, "Doing vt8237r/s stage1 init\n");
+
+	pci_conf1_find_device(0x1106, 0x3227, &dev);
+	pci_conf1_find_device(0x1106, 0x0571, &ide_dev);
+
+	/* Disable GP3 timer, or else the system reboots when it runs out */
+	pci_conf1_write_config8(dev, 0x98, 0x00);
+
+	pci_conf1_write_config8(dev, 0x58, 0x60);
+	pci_conf1_write_config8(dev, 0x59, 0x80);
+	pci_conf1_write_config8(dev, 0x5b, 0x08);
+
+	/* Make it respond to IO space */
+	pci_conf1_write_config8(ide_dev, 0x04, 0x07);
+
+	/* Compatibility mode addresses */
+	//pci_conf1_write_config32(ide_dev, 0x10, 0);
+	//pci_conf1_write_config32(ide_dev, 0x14, 0);
+	//pci_conf1_write_config32(ide_dev, 0x18, 0);
+	//pci_conf1_write_config32(ide_dev, 0x1b, 0);
+
+	/* Native mode base address */
+	//pci_conf1_write_config32(ide_dev, 0x20, BUS_MASTER_ADDR | 1);
+
+	pci_conf1_write_config8(ide_dev, 0x40, 0x4b);//was 0x3
+	pci_conf1_write_config8(ide_dev, 0x41, 0xf2);
+	pci_conf1_write_config8(ide_dev, 0x42, 0x09);
+
+	enable_smbus(smbus_io_base);
+}
+
 /* TODO:
  * Magic numbers -> #defines
  * fix?
Index: mainboard/jetway/j7f2/initram.c
===================================================================
--- mainboard/jetway/j7f2/initram.c	(revision 1066)
+++ mainboard/jetway/j7f2/initram.c	(working copy)
@@ -65,7 +65,7 @@
 void dump_smbus_registers(void)
 {
 	int device;
-	for(device = 1; device < (int)0x80; device++) {
+	for(device = (int)0x50; device < (int)0x82; device++) {
 		int j;
 		//if(spd_read_byte(device, 0) < 0 )
 		//	continue;
@@ -89,98 +89,13 @@
 
 static void enable_mainboard_devices(void) 
 {
-	u32 dev;
-
-	pci_conf1_find_device(0x1106, 0x3227, &dev);
-	/* Disable GP3 */
-	pci_conf1_write_config8(dev, 0x98, 0x00);
-
-	pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata
-	pci_conf1_write_config8(dev, 0x51, 0x1f);
-	pci_conf1_write_config8(dev, 0x58, 0x60);
-	pci_conf1_write_config8(dev, 0x59, 0x80);
-	pci_conf1_write_config8(dev, 0x5b, 0x08);
-
-	pci_conf1_find_device(0x1106, 0x0571, &dev);
-
-	/* Make it respond to IO space */
-	pci_conf1_write_config8(dev, 0x04, 0x07);
-
-	/* Compatibility mode addresses */
-	//pci_conf1_write_config32(dev, 0x10, 0);
-	//pci_conf1_write_config32(dev, 0x14, 0);
-	//pci_conf1_write_config32(dev, 0x18, 0);
-	//pci_conf1_write_config32(dev, 0x1b, 0);
-
-	/* Native mode base address */
-	//pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
-
-	pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3
-	pci_conf1_write_config8(dev, 0x41, 0xf2);
-	pci_conf1_write_config8(dev, 0x42, 0x09);
-	/* I'll be damned if I know what these do */
-	pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e
-	pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00
+	cn700_stage1();
+	vt8237_stage1(SMBUS_IO_BASE);
 }
 
-static void enable_shadow_ram(void) 
-{
-	u8 shadowreg;
-
-	printk(BIOS_DEBUG, "Enabling shadow ram\n");
-	/* Enable shadow ram as normal dram */
-	/* 0xc0000-0xcffff */
-	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
-	/* 0xd0000-0xdffff */
-	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
-	/* 0xe0000-0xeffff */
-	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
-
-	/* 0xf0000-0xfffff */
-	shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
-	shadowreg |= 0x30;
-	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
-
-	/* Do it again for the vlink controller */
-	shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
-	shadowreg |= 0x30;
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
-}
-
-static void enable_vlink(void)
-{
-	printk(BIOS_DEBUG, "Enabling Via V-Link\n");
-
-	/* Enable V-Link statically in 8x mode, using Jetway default values */
-//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
-	//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
-//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
-
-	/* This has to be done last, I think */
-	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
-}
-
 int main(void)
 {
+	/* TODO: Kill off this struct, like Uwe's doing in v2 */
 	struct board_info ctrl[] = {
 		{
 		.d0f2 = PCI_BDF(0, 0, 2),
@@ -194,20 +109,17 @@
 
 	printk(BIOS_DEBUG, "In initram.c main()\n");
 
-	enable_vlink();
-	enable_mainboard_devices();
-	enable_shadow_ram();
+	//enable_mainboard_devices();
 
-	c7_cpu_setup(PCI_BDF(0, 0, 2));
-
-	enable_smbus(SMBUS_IO_BASE);
+	//enable_smbus(SMBUS_IO_BASE);
 	//find_smbus_devices(0x00, 0xff);
+	dump_smbus_registers();
 	sdram_set_registers(ctrl);
 	sdram_set_spd_registers(ctrl);
 	ddr2_sdram_enable(ctrl);
 	
-	//ram_check(0, 640*1024);
-	//ram_check((8 * 1024 * 1024), (16 * 1024 * 1024));
+	ram_check(0, 640*1024);
+	ram_check((8 * 1024 * 1024), (16 * 1024 * 1024));
 
 	return 0;
 }
Index: mainboard/jetway/j7f2/stage1.c
===================================================================
--- mainboard/jetway/j7f2/stage1.c	(revision 1066)
+++ mainboard/jetway/j7f2/stage1.c	(working copy)
@@ -23,29 +23,28 @@
 #include <console.h>
 #include <io.h>
 #include <arch/x86/pci_ops.h>
+#include <arch/x86/legacy.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <superio/fintek/f71805f/f71805f.h>
 #include <northbridge/via/cn700/cn700.h>
+#include <southbridge/via/vt8237/vt8237.h>
 
+#define SMBUS_IO_BASE	0x0400
+
 void hardware_stage1(void)
 {
 	u32 dev;
 
 	post_code(POST_START_OF_MAIN);
 	f71805f_enable_serial(0x2e);
-	
-	/* Enable multifunction for northbridge. */
-	pci_conf1_write_config8(0x00, 0x4f, 0x01);
+	uart_init();
 
 	printk(BIOS_SPEW, "In hardware_stage1()\n");
-	/* Disabled GP3, to keep the system from rebooting automatically */
-	//pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev);
-	dev = PCI_BDF(0, 17, 0);
-	pci_conf1_write_config8(dev, 0x98, 0x00);
+	cn700_stage1();
+	vt8237_stage1(SMBUS_IO_BASE);
 }
 
 void mainboard_pre_payload(void)
 {
-	//banner(BIOS_DEBUG, "mainboard_pre_payload: done");
 }
Index: mainboard/jetway/j7f2/Makefile
===================================================================
--- mainboard/jetway/j7f2/Makefile	(revision 1066)
+++ mainboard/jetway/j7f2/Makefile	(working copy)
@@ -21,11 +21,12 @@
 ## TODO
 
 STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
+			$(src)/northbridge/via/cn700/stage1.c \
+			$(src)/southbridge/via/vt8237/stage1.c \
 			$(src)/arch/x86/stage1_mtrr.c
 
 INITRAM_SRC =   	$(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/via/cn700/initram.c \
-			$(src)/southbridge/via/vt8237/stage1.c \
 			$(src)/lib/ramtest.c \
 			$(src)/arch/x86/pci_ops_conf1.c
 
Index: northbridge/via/cn700/initram.c
===================================================================
--- northbridge/via/cn700/initram.c	(revision 1066)
+++ northbridge/via/cn700/initram.c	(working copy)
@@ -128,97 +128,6 @@
 }
 
 /**
- * Configure the bus between the cpu and the northbridge. This might be able to 
- * be moved to post-ram code in the future. For the most part, these registers
- * should not be messed around with. These are too complex to explain short of
- * copying the datasheets into the comments, but most of these values are from
- * the BIOS Porting Guide, so they should work on any board. If they don't,
- * try the values from your factory BIOS.
- *
- * TODO: Changing the DRAM frequency doesn't work (hard lockup)
- *
- * @param dev The northbridge's CPU Host Interface (D0F2)
- */
-void c7_cpu_setup(u32 dev)
-{
-	/* Host bus interface registers (D0F2 0x50-0x67) */
-	/* Request phase control */
-	pci_conf1_write_config8(dev, 0x50, 0x88);
-	/* CPU Interface Control */
-	pci_conf1_write_config8(dev, 0x51, 0x7a);
-	pci_conf1_write_config8(dev, 0x52, 0x6f);
-	/* Arbitration */
-	pci_conf1_write_config8(dev, 0x53, 0x88);
-	/* Miscellaneous Control */
-	pci_conf1_write_config8(dev, 0x54, 0x1e);
-	pci_conf1_write_config8(dev, 0x55, 0x16);
-	/* Write Policy */
-	pci_conf1_write_config8(dev, 0x56, 0x01);
-	/* Miscellaneous Control */
-	/* DRAM Operating Frequency (bits 7:5 Rx57)
-	 *      000 : 100MHz    001 : 133MHz
-	 *      010 : 166MHz    011 : 200MHz
-	 *      100 : 266MHz    101 : 333MHz
-	 *      110/111 : Reserved
-	 * bits 4:0: Reserved
-	 */
-	/* CPU Miscellaneous Control */
-	pci_conf1_write_config8(dev, 0x59, 0x44);
-	/* Write Policy */
-	pci_conf1_write_config8(dev, 0x5d, 0xb2);
-	/* Bandwidth Timer */
-	pci_conf1_write_config8(dev, 0x5e, 0x88);
-	/* CPU Miscellaneous Control */
-	pci_conf1_write_config8(dev, 0x5f, 0xc7);
-
-	/* Line DRDY# Timing Control */
-	pci_conf1_write_config8(dev, 0x60, 0xff);
-	pci_conf1_write_config8(dev, 0x61, 0xff);
-	pci_conf1_write_config8(dev, 0x62, 0x0f);
-	/* QW DRDY# Timing Control */
-	pci_conf1_write_config8(dev, 0x63, 0xff);
-	pci_conf1_write_config8(dev, 0x64, 0xff);
-	pci_conf1_write_config8(dev, 0x65, 0x0f);
-	/* Read Line Burst DRDY# Timing Control */
-	pci_conf1_write_config8(dev, 0x66, 0xff);
-	pci_conf1_write_config8(dev, 0x67, 0x30);
-
-	/* Host Bus I/O Circuit (see datasheet) */
-	/* Host Address Pullup/down Driving */
-	pci_conf1_write_config8(dev, 0x70, 0x11);
-	pci_conf1_write_config8(dev, 0x71, 0x11);
-	pci_conf1_write_config8(dev, 0x72, 0x11);
-	pci_conf1_write_config8(dev, 0x73, 0x11);
-	/* Miscellaneous Control */
-	pci_conf1_write_config8(dev, 0x74, 0x35);
-	/* AGTL+ I/O Circuit */
-	pci_conf1_write_config8(dev, 0x75, 0x28);
-	/* AGTL+ Compensation Status */
-	pci_conf1_write_config8(dev, 0x76, 0x74);
-	/* AGTL+ Auto Compensation Offest */
-	pci_conf1_write_config8(dev, 0x77, 0x00);
-	/* Host FSB CKG Control */
-	pci_conf1_write_config8(dev, 0x78, 0x0a);
-	/* Address/Address Clock Output Delay Control */
-	pci_conf1_write_config8(dev, 0x79, 0xaa);
-	/* Address Strobe Input Delay Control */
-	pci_conf1_write_config8(dev, 0x7a, 0x24);
-	/* Address CKG Rising/Falling Time Control */
-	pci_conf1_write_config8(dev, 0x7b, 0xaa);
-	/* Address CKG Clock Rising/Falling Time Control */
-	pci_conf1_write_config8(dev, 0x7c, 0x00);
-	/* Undefined (can't remember why I did this) */
-	pci_conf1_write_config8(dev, 0x7d, 0x6d);
-
-	pci_conf1_write_config8(dev, 0x7e, 0x00);
-	pci_conf1_write_config8(dev, 0x7f, 0x00);
-	pci_conf1_write_config8(dev, 0x80, 0x1b);
-	pci_conf1_write_config8(dev, 0x81, 0x0a);
-	pci_conf1_write_config8(dev, 0x82, 0x0a);
-	pci_conf1_write_config8(dev, 0x83, 0x0a);
-}
-
-/**
  * Set up various ram and other control registers statically. Some of these may 
  * not be needed, other should be done with spd info, but that's a project for
  * the future
@@ -353,10 +262,6 @@
 	pci_conf1_write_config8(dev->d0f3, 0x74, 0x04);
 	pci_conf1_write_config8(dev->d0f3, 0x75, 0x04);
 	pci_conf1_write_config8(dev->d0f3, 0x76, 0x00);
-	
-	/* Thanks to Urbez Santana Roma for this */
-	pci_conf1_write_config8(dev->d1f0, 0x19, 0x1);
-	pci_conf1_write_config8(dev->d1f0, 0x1a, 0x1);
 }
 
 /**
Index: northbridge/via/cn700/stage1.c
===================================================================
--- northbridge/via/cn700/stage1.c	(revision 0)
+++ northbridge/via/cn700/stage1.c	(revision 0)
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+//#include <lib.h>
+#include <console.h>
+#include <device/pci.h>
+//#include <io.h>
+#include <config.h>
+#include "cn700.h"
+
+static void enable_shadow_ram(void) 
+{
+	u8 shadowreg;
+
+	printk(BIOS_DEBUG, "Enabling shadow ram\n");
+	/* Enable shadow ram as normal dram */
+	/* 0xc0000-0xcffff */
+	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
+	/* 0xd0000-0xdffff */
+	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
+	/* 0xe0000-0xeffff */
+	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
+
+	/* 0xf0000-0xfffff */
+	shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
+	shadowreg |= 0x30;
+	pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
+
+	/* Do it again for the vlink controller */
+	shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
+	shadowreg |= 0x30;
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
+}
+
+static void enable_vlink(void)
+{
+	printk(BIOS_DEBUG, "Enabling Via V-Link\n");
+
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
+	//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
+
+	/* This has to be done last, I think */
+	pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
+}
+
+/**
+ * Configure the bus between the cpu and the northbridge. This might be able to 
+ * be moved to post-ram code in the future. For the most part, these registers
+ * should not be messed around with. These are too complex to explain short of
+ * copying the datasheets into the comments, but most of these values are from
+ * the BIOS Porting Guide, so they should work on any board. If they don't,
+ * try the values from your factory BIOS.
+ *
+ * TODO: Changing the DRAM frequency doesn't work (hard lockup)
+ *
+ * @param dev The northbridge's CPU Host Interface (D0F2)
+ */
+void c7_cpu_setup(void)
+{
+	u32 dev = PCI_BDF(0, 0, 2);
+
+	/* Host bus interface registers (D0F2 0x50-0x67) */
+	/* Request phase control */
+	pci_conf1_write_config8(dev, 0x50, 0x88);
+	/* CPU Interface Control */
+	pci_conf1_write_config8(dev, 0x51, 0x7a);
+	pci_conf1_write_config8(dev, 0x52, 0x6f);
+	/* Arbitration */
+	pci_conf1_write_config8(dev, 0x53, 0x88);
+	/* Miscellaneous Control */
+	pci_conf1_write_config8(dev, 0x54, 0x1e);
+	pci_conf1_write_config8(dev, 0x55, 0x16);
+	/* Write Policy */
+	pci_conf1_write_config8(dev, 0x56, 0x01);
+	/* Miscellaneous Control */
+	/* DRAM Operating Frequency (bits 7:5 Rx57)
+	 *      000 : 100MHz    001 : 133MHz
+	 *      010 : 166MHz    011 : 200MHz
+	 *      100 : 266MHz    101 : 333MHz
+	 *      110/111 : Reserved
+	 * bits 4:0: Reserved
+	 */
+	/* CPU Miscellaneous Control */
+	pci_conf1_write_config8(dev, 0x59, 0x44);
+	/* Write Policy */
+	pci_conf1_write_config8(dev, 0x5d, 0xb2);
+	/* Bandwidth Timer */
+	pci_conf1_write_config8(dev, 0x5e, 0x88);
+	/* CPU Miscellaneous Control */
+	pci_conf1_write_config8(dev, 0x5f, 0xc7);
+
+	/* Line DRDY# Timing Control */
+	pci_conf1_write_config8(dev, 0x60, 0xff);
+	pci_conf1_write_config8(dev, 0x61, 0xff);
+	pci_conf1_write_config8(dev, 0x62, 0x0f);
+	/* QW DRDY# Timing Control */
+	pci_conf1_write_config8(dev, 0x63, 0xff);
+	pci_conf1_write_config8(dev, 0x64, 0xff);
+	pci_conf1_write_config8(dev, 0x65, 0x0f);
+	/* Read Line Burst DRDY# Timing Control */
+	pci_conf1_write_config8(dev, 0x66, 0xff);
+	pci_conf1_write_config8(dev, 0x67, 0x30);
+
+	/* Host Bus I/O Circuit (see datasheet) */
+	/* Host Address Pullup/down Driving */
+	pci_conf1_write_config8(dev, 0x70, 0x11);
+	pci_conf1_write_config8(dev, 0x71, 0x11);
+	pci_conf1_write_config8(dev, 0x72, 0x11);
+	pci_conf1_write_config8(dev, 0x73, 0x11);
+	/* Miscellaneous Control */
+	pci_conf1_write_config8(dev, 0x74, 0x35);
+	/* AGTL+ I/O Circuit */
+	pci_conf1_write_config8(dev, 0x75, 0x28);
+	/* AGTL+ Compensation Status */
+	pci_conf1_write_config8(dev, 0x76, 0x74);
+	/* AGTL+ Auto Compensation Offest */
+	pci_conf1_write_config8(dev, 0x77, 0x00);
+	/* Host FSB CKG Control */
+	pci_conf1_write_config8(dev, 0x78, 0x0a);
+	/* Address/Address Clock Output Delay Control */
+	pci_conf1_write_config8(dev, 0x79, 0xaa);
+	/* Address Strobe Input Delay Control */
+	pci_conf1_write_config8(dev, 0x7a, 0x24);
+	/* Address CKG Rising/Falling Time Control */
+	pci_conf1_write_config8(dev, 0x7b, 0xaa);
+	/* Address CKG Clock Rising/Falling Time Control */
+	pci_conf1_write_config8(dev, 0x7c, 0x00);
+	/* Undefined (can't remember why I did this) */
+	pci_conf1_write_config8(dev, 0x7d, 0x6d);
+
+	pci_conf1_write_config8(dev, 0x7e, 0x00);
+	pci_conf1_write_config8(dev, 0x7f, 0x00);
+	pci_conf1_write_config8(dev, 0x80, 0x1b);
+	pci_conf1_write_config8(dev, 0x81, 0x0a);
+	pci_conf1_write_config8(dev, 0x82, 0x0a);
+	pci_conf1_write_config8(dev, 0x83, 0x0a);
+}
+
+void cn700_stage1(void)
+{
+	/* Enable multifunction for northbridge. */
+	pci_conf1_write_config8(0x00, 0x4f, 0x01);
+
+	/* Put Bus 1 in its proper place */
+	pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x19, 0x1);
+	pci_conf1_write_config8(PCI_BDF(0, 1, 0), 0x1a, 0x1);
+
+	enable_shadow_ram();
+	enable_vlink();
+	c7_cpu_setup();
+}
Index: northbridge/via/cn700/cn700.h
===================================================================
--- northbridge/via/cn700/cn700.h	(revision 1066)
+++ northbridge/via/cn700/cn700.h	(working copy)
@@ -28,7 +28,8 @@
 	u16 spd_channel0[2];
 };
 
-void c7_cpu_setup(u32);
+void c7_cpu_setup(void);
+void cn700_stage1(void);
 void sdram_set_registers(struct board_info *);
 void sdram_set_spd_registers(struct board_info *);
 void ddr2_sdram_enable(struct board_info *);
