<br><br><div class="gmail_quote">On Thu, Dec 18, 2008 at 9:07 AM, Corey Osgood <span dir="ltr"><<a href="mailto:corey.osgood@gmail.com">corey.osgood@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div><div></div><div class="Wj3C7c">On Thu, Dec 18, 2008 at 9:22 AM, Myles Watson <span dir="ltr"><<a href="mailto:mylesgw@gmail.com" target="_blank">mylesgw@gmail.com</a>></span> wrote:<br></div></div><div class="gmail_quote">
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<br><br><div class="gmail_quote"><div>On Wed, Dec 17, 2008 at 11:38 PM, Corey Osgood <span dir="ltr"><<a href="mailto:corey.osgood@gmail.com" target="_blank">corey.osgood@gmail.com</a>></span> wrote:<br>
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<div><div></div><div>On Wed, Dec 17, 2008 at 11:04 PM, Corey Osgood <span dir="ltr"><<a href="mailto:corey.osgood@gmail.com" target="_blank">corey.osgood@gmail.com</a>></span> wrote:<br></div></div><div class="gmail_quote">
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<div>On Wed, Dec 17, 2008 at 8:55 PM, Peter Stuge <span dir="ltr"><<a href="mailto:peter@stuge.se" target="_blank">peter@stuge.se</a>></span> wrote:<br></div><div class="gmail_quote"><div>
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<div>Corey Osgood wrote:<br>
> would there be any problem with calling functions to enable mtrrs<br>
> and the cache (if it's not already) from the end of disable_car()?<br>
<br>
</div>None whatsoever. Commit at will.<font color="#888888"></font></blockquote></div><div><br>It didn't help, disable_car() already does essentially the same thing; disable cache, enable mtrrs, re-enable cache. I'm comparing memtest between the stock bios and coreboot right now, the throughput for the stock bios is 6122MB/s for L1 cache and 574MB/s for memory. With v2, it's 3265 and 191, respectively (using ROMCC), with v3 it's 15 and 18. So something's not right somewhere. The other thing is that in v2 and v3, the CPU is only running at 800MHz in memtest, but with the stock BIOS it runs at 1.5GHz, that's probably the reason for the differing cache throughputs. Anyways, I'm diving into both v2 and v3 and trying to track down why this is running so slowly.</div>
</div></blockquote></div></div><div><br><insert happy dance here><br><br>From the currently-running memtest86 on coreboot-v3:<br></div></div>L1 Cache: 128K 3265 MB/s<br>Memory : 480M 240 MB/s</blockquote></div>
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<br>Congratulations! <br></div><div><div> </div><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;"><br>That's right, faster then v2 :) I've managed to coerce the northbridge into running the memory at 200MHz (DDR400) without locking up the system like it does in v2, and also to use 1GB of ram, which the fuctory BIOS only sees as 512MB, and v2 for some reason trips over. However, it's a mixed blessing, even though memtest86 now runs at an acceptable speed, coreboot is still running fairly slowly. I'm attaching a patch that brings over mtrr.c from v2 and hacks it to work with v3, but no sign-off because IMO it's not ready to be committed. I'll try booting a FILO payload and a kernel tomorrow, but right now it's time for some sleep.<br>
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</font></blockquote></div><div><br>I know it takes a while to try new things, but have you tried a different debug level. Switching Serengeti from BIOS_SPEW to BIOS_INFO cuts boot time by about 10x. I'm interested if that's true for you too.</div>
</div></blockquote></div></div><div><br>Still running with no errors, 9 hours later :) I dropped the debug level from SPEW to DEBUG and it helped greatly, it seems for some reason that v3 takes longer to print messages then v2 did. Also, disabling the console log buffer seems to have shaved a little time off, but I couldn't say for sure.</div>
</div></blockquote><div><br>It's possible that that's because printk is running out of the ROM. There have been some discussions on the list about that.<br><br>Thanks,<br>Myles<br> </div></div><br>