This patch fixes up qemu to work with the new resource allocation code.<br><br>Signed-off-by: Myles Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br><br>Thanks,<br>Myles<br><br>file-by-file changes:<br>
<br>dts:<br> There are no bus devices, remove it. Add the northbridge devices.<br> Fix susbsytem_vendor and subsystem_device.<br><br>southbridge/intel/i82371eb/ide:<br> Make the ide enabled by default.<br><br>northbridge/intel/i440bxemulation/i440bx.c:<br>
1. Split ops into domain and northbridge<br> A. Domain should have bus ops, scan_bus, etc.<br> B. Northbridge should have ops for its own registers.<br> In this case it only needs read and set resources.<br>
<br>functions:<br> i440bx_read_resources - set up the IO and VGA resources. VGA is fixed.<br> i440bx_ram_resources - this should be called after resource assignment.<br> i440bx_set_resources - call pci_set_resources then i440bx_ram_resources.<br>
i440bx_domain_read_resources - Set up system-wide resources, and<br> reserve space for the local APIC. I put the IOAPIC here too,<br> but it belongs somewhere in the southbridge.<br> i440bx_domain_set_resources - Mark the domain-specific resources as<br>
stored (In a real device you'd probably need to set some<br> registers here.) Call phase4_set_resources for children.<br><br>southbridge/intel/i82371eb/i82371eb.c:<br> 1. Add ISA read and set resources to reserve legacy IO space.<br>
- Note that since it's subtractively decoded, it doesn't need<br> to be stored anywhere. It needs to be marked stored so<br> pci_set_resource doesn't try to store it.<br> <br><br>