<table cellspacing="0" cellpadding="0" border="0" ><tr><td valign="top" style="font: inherit;">Marc,<br><br>I have narrowed the reset to the first<br>  msr = rdmsr(0xc0010042); <br>line in cache_as_ram.c.<br>I assume the second would do the same thing if it ever made it there.<br><br>Booting with the orig bios, linux reports<br>ts ttp tm stc 100mhzsteps<br>as the available power options. It is missing fid vid.<br><br>Based on the lack of cpuinfo bits and the documentation the says the processor will do exactly what it is doing, I propose the included patch.<br>I made the changes to pistachio and norwich also but they are untested.<br><br>With this patch I make it here:<br><br>coreboot-2.0.0 Wed Jan  7 17:09:38 PST 2009 starting...                        
 <br>bsp_apicid=0x0                                                                  <br>Enabling routing table for node 00 done.                                        <br>Enabling UP
 settings                                                            <br>Disabling read/write/fill probes for UP... done.                               
 <br>coherent_ht_finalize                                                            <br>done                                                                            <br>core0
 started:                                                                  <br>SBLink=00                                                                       <br>NC
 node|link=00                                                                 <br>rs690_early_setup()                                                             <br>get_cpu_rev
 EAX=0x60fc2.                                                        <br>CPU Rev is K8_G0.                                                               <br>NB Revision is
 A12.                                                             <br>k8_optimization()                                                              
 <br>rs690_por_init                                                                  <br>sb600_early_setup()                                                            
 <br>sb600_devices_por_init()                                                        <br>sb600_devices_por_init(): SMBus Device, BDF:0-20-0                              <br>SMBus controller enabled, sb revision is 0x13                                   <br>sb600_devices_por_init(): IDE Device,
 BDF:0-20-1                                <br>sb600_devices_por_init(): LPC Device, BDF:0-20-3                                <br>sb600_devices_por_init(): P2P Bridge, BDF:0-20-4                                <br>sb600_devices_por_init(): SATA Device, BDF:0-18-0                              
 <br>sb600_pmio_por_init()                                                                                                       <br>Changing FIDVID not supported
                                                         <br>entering optimize_link_incoherent_ht                                           
 <br>sysinfo->link_pair_num=0x1                                                      <br>entering ht_optimize_link                                                       <br>pos=0x8a, unfiltered
 freq_cap=0x8035                                            <br>pos=0x8a, filtered freq_cap=0x35                                                <br>pos=0xd2, unfiltered freq_cap=0x65                                              <br>pos=0xd2, filtered
 freq_cap=0x65                                                <br>freq_cap1=0x35, freq_cap2=0x65                                                  <br>dev1 old_freq=0x5, freq=0x5, needs_reset=0x0                                    <br>dev2 old_freq=0x5, freq=0x5,
 needs_reset=0x0                                    <br>width_cap1=0x11, width_cap2=0x11                                                <br>dev1 input ln_width1=0x4, ln_width2=0x4                                         <br>dev1 input
 width=0x1                                                            <br>dev1 output ln_width1=0x4, ln_width2=0x4                                        <br>dev1 input|output
 width=0x11                                                    <br>old dev1 input|output width=0x11                                                <br>dev2 input|output
 width=0x11                                                    <br>old dev2 input|output width=0x11                                                <br>after ht_optimize_link for link pair 0, reset_needed=0x0                        <br>after optimize_link_read_pointers_chain,
 reset_needed=0x0                       <br>rs690_htinit k8_ht_freq=5.                                                      <br>rs690_htinit NB_CFG_Q_F1000_800=0                                              
 <br>needs_reset=0x0                                                                 <br>sysinfo->nodes:  1  sysinfo->ctrl: cf188  spd_addr: ffffae98                   
 <br>Ram1.00                                                                         <br>setting up CPU00 northbridge registers                                         
 <br>done.                                                                           <br>Ram2.00                                                                         <br>Enable 64MuxMode &
 BurstLength32                                                <br>Unbuffered                                                                     
 <br>333Mhz                                                                          <br>333Mhz<br><br>Thanks,<br>Dan Lykowski<br><pre>Signed-off-by: Dan Lykowski <lykowdk@gmail.com><br></pre><br>--- On <b>Thu, 1/8/09, Marc Jones <i><marcj303@gmail.com></i></b> wrote:<br><blockquote style="border-left: 2px solid rgb(16, 16, 255); margin-left: 5px; padding-left: 5px;"><br>From: Marc Jones <marcj303@gmail.com><br>Subject: Re: [coreboot] FIDVID question<br>To: r.marek@assembler.cz<br>Cc: "Dan Lykowski" <engineerguy3737@yahoo.com>, "Coreboot"
 <coreboot@coreboot.org><br>Date: Thursday, January 8, 2009, 12:10 PM<br><br><br>-----Inline Attachment Follows-----<br><br><div class="plainMail">On Thu, Jan 8, 2009 at 1:45 AM,  <<a ymailto="mailto:r.marek@assembler.cz" href="/mc/compose?to=r.marek@assembler.cz">r.marek@assembler.cz</a>> wrote:<br>> Hi,<br>><br>> if you check your CPUID, does it support FIDVID?<br>><br>> If yes, then there is another problem. Perhaps you are hit by<br>> some errata which says first is needed not HT reset (LDTSTOP) but PCI reset.<br>> I don't have a code at my hand right now, but is HT reset stuff done<br>> _before_ the fidvid?<br>><br><br>I think that all the revf/g processors support fidvid even if it can't<br>be changed. The S1G1 socket means revf and above and checking for<br>support really isn't needed. I think it is safe for a platform to make<br>some assumptions like that.<br><br>Have you narrowed the reset to the
 fidvid code?  After fidvid setup<br>there should be a ht reset as Rudolf noted. You can skip fidvid setup<br>for now. It just means that the processor will run at min frequency.<br><br><br>Marc<br><br>--<br>coreboot mailing list: <a ymailto="mailto:coreboot@coreboot.org" href="/mc/compose?to=coreboot@coreboot.org">coreboot@coreboot.org</a><br><a href="http://www.coreboot.org/mailman/listinfo/coreboot" target="_blank">http://www.coreboot.org/mailman/listinfo/coreboot</a><br></div></blockquote></td></tr></table><br>