Index: p6.c
===================================================================
--- p6.c	(revision 0)
+++ p6.c	(revision 0)
@@ -0,0 +1,133 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (c) 2009 Holger Hesselbarth <popkonserve@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * references:
+ * http://www.vortex.prodigynet.co.uk/x86test/platform_id.html
+ */
+ 
+#include "msrtool.h"
+
+int p6_probe(const struct targetdef *target) {
+    struct cpuid_t *id = cpuid();
+    return ((06 == id->family) && (0 == id->ext_family));
+}
+
+const struct msrdef p6_msrs[] = {
+	{ 0x00000017, MSRTYPE_RO, MSR2(0, 0), "IA32_PLATFORM_ID", "Platform ID", {
+		{ 63, 3, RESERVED },
+		{ 60, 1, "CLKRATIO", "Clock Frequency Ratio", PRESENT_DEC, {
+			{ MSR1(0), "" },
+			{ MSR1(1), "" },
+			{ BITVAL_EOT }
+		}},
+		{ 59, 3, RESERVED },
+		{ 56, 3, "L2DIS", "L2 cache latency", PRESENT_DEC, NOBITS },
+		{ 52, 3, "PID", "Platform ID", PRESENT_DEC, {
+			{ MSR1(0), "Processor Flag 0" },
+			{ MSR1(1), "Processor Flag 1" },
+			{ MSR1(2), "Processor Flag 2" },
+			{ MSR1(3), "Processor Flag 3" },
+			{ MSR1(4), "Processor Flag 4" },
+			{ MSR1(5), "Processor Flag 5" },
+			{ MSR1(6), "Processor Flag 6" },
+			{ MSR1(7), "Processor Flag 7" },
+			{ BITVAL_EOT }
+		}},
+		{ 49, 50, RESERVED },
+        { BITS_EOT }
+	}},
+
+	{ 0x0000011E, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "Control register 3", {
+		{ 63, 38, RESERVED },
+		{ 25, 1, "CBF", "Cache Bus Fraction", PRESENT_DEC, {
+			{ MSR1(0), "same as core speed" },
+			{ MSR1(1), "half of core speed" },
+			{ BITVAL_EOT }
+		}},
+		{ 24, 1, RESERVED },
+		{ 23, 1, "L2DIS", "L2 cache hardware", PRESENT_DEC, {
+			{ MSR1(0), "enabled" },
+			{ MSR1(1), "disabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 22, 3, "L2ADR", "L2 physical address range", PRESENT_DEC, {
+			{ MSR1(0), "512 Mbytes" },
+			{ MSR1(1), "1 Gbytes" },
+			{ MSR1(2), "2 Gbytes" },
+			{ MSR1(3), "4 Gbytes" },
+			{ MSR1(4), "8 Gbytes" },
+			{ MSR1(5), "16 Gbytes" },
+			{ MSR1(6), "32 Gbytes" },
+			{ MSR1(7), "64 Gbytes" },
+			{ BITVAL_EOT }
+		}},
+		{ 19, 1, RESERVED },
+		{ 18, 1, "L2SCHK", "L2 state error checking", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 17, 5, "L2PBS", "L2 size per bank", PRESENT_DEC, {
+			{ MSR1(0), "128 kbytes" },
+			{ MSR1(1), "256 kbytes" },
+			{ MSR1(2), "512 kbytes" },
+			{ MSR1(4), "1 Mbytes" },
+			{ MSR1(8), "2 Mbytes" },
+			{ MSR1(16), "4 Mbytes" },
+			{ BITVAL_EOT }
+		}},
+        { 12, 2, "L2BAN", "Number of L2 banks", PRESENT_DEC, NOBITS },
+		{ 10, 2, "L2WAY", "L2 Associativity", PRESENT_DEC, {
+			{ MSR1(0), "Direct Mapped" },
+			{ MSR1(1), "2 Way" },
+			{ MSR1(2), "4 Way" },
+			{ MSR1(3), "reserved" },
+			{ BITVAL_EOT }
+		}},
+		{ 8, 1, "L2EN", "L2 status", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 7, 1, "L2CRTN", "CRTN Parity Check", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 6, 1, "L2ADDR", "Address Parity Check", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+		{ 5, 1, "L2ECC", "ECC Check", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+        { 4, 4, "L2LAT", "L2 latency", PRESENT_DEC, NOBITS },
+		{ 0, 1, "L2CONF", "L2 configured", PRESENT_DEC, {
+			{ MSR1(0), "disabled" },
+			{ MSR1(1), "enabled" },
+			{ BITVAL_EOT }
+		}},
+        { BITS_EOT }
+	}},
+    { MSR_EOT }
+};
