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We used pci_cf8_conf1.{read,write}{8,16,32} because the pci_read_config32 doesnt<BR>
work in mainboard stage according to our test result. I dont know the current status.<BR>
We havent merge the code from comunity in weeks. And I havent test the patch. But <BR>
I think, I just think it will not work.<BR>
<BR>
Zheng<BR><BR>> Date: Fri, 13 Feb 2009 11:54:57 +0100<BR>> From: c-d.hailfinger.devel.2006@gmx.net<BR>> To: coreboot@coreboot.org<BR>> Subject: [coreboot] [PATCH] Clean up DBM690T and Pistachio<BR>> <BR>> Clean up DBM690T and Pistachio targets:<BR>> - Use MAINBOARD_VENDOR and MAINBOARD_PART_NUMBER wherever possible<BR>> instead of filling out the strings by hand.<BR>> - Avoid using the mainboard name in function names unless explicitly<BR>> required by the build system.<BR>> - Use pci_{read,write}_config{8,16,32} instead of<BR>> pci_cf8_conf1.{read,write}{8,16,32} in mainboard.c.<BR>> - Remove unused variables.<BR>> - Improve accuracy of some thermal comments.<BR>> - Improve formatting and formatting consistency.<BR>> <BR>> With this patch, porting to a new AMD 690/SB600 board becomes even<BR>> easier because there is less stuff to replace. A nice side effect is<BR>> that the mainboard directories of DBM690T and Pistachio are now almost<BR>> identical.<BR>> <BR>> No functional changes. Compile tested. (You have to revert r3942 to get<BR>> any 690/SB600 target to compile. Simply run "svn diff -c 3942|patch -p0<BR>> -R" in the main source directory.)<BR>> <BR>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net><BR>> <BR>> Index: corebootv2/src/mainboard/amd/pistachio/resourcemap.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/pistachio/resourcemap.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/pistachio/resourcemap.c (working copy)<BR>> @@ -17,7 +17,7 @@<BR>> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<BR>> */<BR>> <BR>> -static void setup_pistachio_resource_map(void)<BR>> +static void setup_mb_resource_map(void)<BR>> {<BR>> static const unsigned int register_values[] = {<BR>> /* Careful set limit registers before base registers which contain the enables */<BR>> Index: corebootv2/src/mainboard/amd/pistachio/chip.h<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/pistachio/chip.h (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/pistachio/chip.h (working copy)<BR>> @@ -21,6 +21,6 @@<BR>> <BR>> struct mainboard_amd_pistachio_config<BR>> {<BR>> - unsigned long uma_size; /* How many UMA should be used in memory for TOP. */<BR>> + u32 uma_size; /* How many UMA should be used in memory for TOP. */<BR>> };<BR>> <BR>> Index: corebootv2/src/mainboard/amd/pistachio/mainboard.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/pistachio/mainboard.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/pistachio/mainboard.c (working copy)<BR>> @@ -83,7 +83,6 @@<BR>> u16 word;<BR>> u32 dword;<BR>> device_t sm_dev;<BR>> - struct bus pbus;<BR>> <BR>> /* set adt7475 */<BR>> ADT7475_write_byte(0x40, 0x04);<BR>> @@ -116,11 +115,11 @@<BR>> /* remote 2 therm temp limit (95C) */<BR>> ADT7475_write_byte(0x6c, 0x9f);<BR>> <BR>> - /* PWM 1 minimum duty cycle (37%) */<BR>> + /* PWM 1 minimum duty cycle (37.6%) */<BR>> ADT7475_write_byte(0x64, 0x60);<BR>> /* PWM 1 Maximum duty cycle (100%) */<BR>> ADT7475_write_byte(0x38, 0xff);<BR>> - /* PWM 3 minimum duty cycle (37%) */<BR>> + /* PWM 3 minimum duty cycle (37.6%) */<BR>> ADT7475_write_byte(0x66, 0x60);<BR>> /* PWM 3 Maximum Duty Cycle (100%) */<BR>> ADT7475_write_byte(0x3a, 0xff);<BR>> @@ -167,28 +166,19 @@<BR>> <BR>> /* GPM5 as GPIO not USB OC */<BR>> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));<BR>> - dword =<BR>> - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x64);<BR>> + dword = pci_read_config32(sm_dev, 0x64);<BR>> dword |= 1 << 19;<BR>> - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x64, dword);<BR>> + pci_write_config32(sm_dev, 0x64, dword);<BR>> <BR>> /* Enable Client Management Index/Data registers */<BR>> - dword =<BR>> - pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x78);<BR>> + dword = pci_read_config32(sm_dev, 0x78);<BR>> dword |= 1 << 11; /* Cms_enable */<BR>> - pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x78, dword);<BR>> + pci_write_config32(sm_dev, 0x78, dword);<BR>> <BR>> /* MiscfuncEnable */<BR>> - byte =<BR>> - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x41);<BR>> + byte = pci_read_config8(sm_dev, 0x41);<BR>> byte |= (1 << 5);<BR>> - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x41, byte);<BR>> + pci_write_config8(sm_dev, 0x41, byte);<BR>> <BR>> /* set GPM5 as input */<BR>> /* set index register 0C50h to 13h (miscellaneous control) */<BR>> @@ -228,12 +218,9 @@<BR>> pm2_iowrite(0x42, byte);<BR>> <BR>> /* set GPIO 64 to input */<BR>> - word =<BR>> - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x56);<BR>> + word = pci_read_config16(sm_dev, 0x56);<BR>> word |= 1 << 7;<BR>> - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x56, word);<BR>> + pci_write_config16(sm_dev, 0x56, word);<BR>> <BR>> /* set GPIO 64 internal pull-up */<BR>> byte = pm2_ioread(0xf0);<BR>> @@ -269,12 +256,12 @@<BR>> * enable the dedicated function in pistachio board.<BR>> * This function called early than rs690_enable.<BR>> *************************************************/<BR>> -void pistachio_enable(device_t dev)<BR>> +void mb_enable(device_t dev)<BR>> {<BR>> struct mainboard_amd_pistachio_config *mainboard =<BR>> (struct mainboard_amd_pistachio_config *)dev->chip_info;<BR>> <BR>> - printk_info("Mainboard Pistachio Enable. dev=0x%x\n", dev);<BR>> + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=0x%x\n", dev);<BR>> <BR>> #if (CONFIG_GFXUMA == 1)<BR>> msr_t msr, msr2;<BR>> @@ -339,6 +326,6 @@<BR>> * CONFIG_CHIP_NAME defined in Option.lb.<BR>> */<BR>> struct chip_operations mainboard_amd_pistachio_ops = {<BR>> - CHIP_NAME("AMD Pistachio Mainboard")<BR>> - .enable_dev = pistachio_enable,<BR>> + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")<BR>> + .enable_dev = mb_enable,<BR>> };<BR>> Index: corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/pistachio/cache_as_ram_auto.c (working copy)<BR>> @@ -156,9 +156,8 @@<BR>> u32 bsp_apicid = 0;<BR>> msr_t msr;<BR>> struct cpuid_result cpuid1;<BR>> - struct sys_info *sysinfo =<BR>> - (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE -<BR>> - DCACHE_RAM_GLOBAL_VAR_SIZE);<BR>> + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +<BR>> + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);<BR>> <BR>> if (bist == 0) {<BR>> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<BR>> @@ -178,7 +177,7 @@<BR>> report_bist_failure(bist);<BR>> printk_debug("bsp_apicid=0x%x\n", bsp_apicid);<BR>> <BR>> - setup_pistachio_resource_map();<BR>> + setup_mb_resource_map();<BR>> <BR>> setup_coherent_ht_domain();<BR>> <BR>> Index: corebootv2/src/mainboard/amd/dbm690t/irq_tables.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/dbm690t/irq_tables.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/dbm690t/irq_tables.c (working copy)<BR>> @@ -54,7 +54,7 @@<BR>> extern u8 bus_isa;<BR>> extern u8 bus_rs690[8];<BR>> extern u8 bus_sb600[2];<BR>> -extern unsigned long sbdn_sb600;<BR>> +extern u32 sbdn_sb600;<BR>> <BR>> unsigned long write_pirq_routing_table(unsigned long addr)<BR>> {<BR>> Index: corebootv2/src/mainboard/amd/dbm690t/resourcemap.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/dbm690t/resourcemap.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/dbm690t/resourcemap.c (working copy)<BR>> @@ -17,7 +17,7 @@<BR>> * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA<BR>> */<BR>> <BR>> -static void setup_dbm690t_resource_map(void)<BR>> +static void setup_mb_resource_map(void)<BR>> {<BR>> static const unsigned int register_values[] = {<BR>> /* Careful set limit registers before base registers which contain the enables */<BR>> Index: corebootv2/src/mainboard/amd/dbm690t/mainboard.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/dbm690t/mainboard.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/dbm690t/mainboard.c (working copy)<BR>> @@ -99,30 +99,21 @@<BR>> u8 byte;<BR>> /*u32 sm_dev, ide_dev; */<BR>> device_t sm_dev, ide_dev;<BR>> - struct bus pbus;<BR>> <BR>> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));<BR>> <BR>> - byte =<BR>> - pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0xA9);<BR>> + byte = pci_read_config8(sm_dev, 0xA9);<BR>> byte |= (1 << 5); /* Set Gpio9 as input */<BR>> - pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0xA9, byte);<BR>> + pci_write_config8(sm_dev, 0xA9, byte);<BR>> <BR>> ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));<BR>> - byte =<BR>> - pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,<BR>> - ide_dev->path.u.pci.devfn, 0x56);<BR>> + byte = pci_read_config8(ide_dev, 0x56);<BR>> byte &= ~(7 << 0);<BR>> - if ((1 << 5) & pci_cf8_conf1.<BR>> - read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,<BR>> - 0xAA))<BR>> + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))<BR>> byte |= 2 << 0; /* mode 2 */<BR>> else<BR>> byte |= 5 << 0; /* mode 5 */<BR>> - pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,<BR>> - ide_dev->path.u.pci.devfn, 0x56, byte);<BR>> + pci_write_config8(ide_dev, 0x56, byte);<BR>> }<BR>> <BR>> /*<BR>> @@ -133,7 +124,6 @@<BR>> u8 byte;<BR>> u16 word;<BR>> device_t sm_dev;<BR>> - struct bus pbus;<BR>> <BR>> /* set ADT 7461 */<BR>> ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */<BR>> @@ -156,12 +146,9 @@<BR>> <BR>> /* set GPIO 64 to input */<BR>> sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));<BR>> - word =<BR>> - pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x56);<BR>> + word = pci_read_config16(sm_dev, 0x56);<BR>> word |= 1 << 7;<BR>> - pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,<BR>> - sm_dev->path.u.pci.devfn, 0x56, word);<BR>> + pci_write_config16(sm_dev, 0x56, word);<BR>> <BR>> /* set GPIO 64 internal pull-up */<BR>> byte = pm2_ioread(0xf0);<BR>> @@ -197,12 +184,12 @@<BR>> * enable the dedicated function in dbm690t board.<BR>> * This function called early than rs690_enable.<BR>> *************************************************/<BR>> -void dbm690t_enable(device_t dev)<BR>> +void mb_enable(device_t dev)<BR>> {<BR>> struct mainboard_amd_dbm690t_config *mainboard =<BR>> (struct mainboard_amd_dbm690t_config *)dev->chip_info;<BR>> <BR>> - printk_info("Mainboard DBM690T Enable. dev=0x%x\n", dev);<BR>> + printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=0x%x\n", dev);<BR>> <BR>> #if (CONFIG_GFXUMA == 1)<BR>> msr_t msr, msr2;<BR>> @@ -267,6 +254,6 @@<BR>> * CONFIG_CHIP_NAME defined in Option.lb.<BR>> */<BR>> struct chip_operations mainboard_amd_dbm690t_ops = {<BR>> - CHIP_NAME("AMD DBM690T Mainboard")<BR>> - .enable_dev = dbm690t_enable,<BR>> + CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")<BR>> + .enable_dev = mb_enable,<BR>> };<BR>> Index: corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c<BR>> ===================================================================<BR>> --- corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (revision 3943)<BR>> +++ corebootv2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c (working copy)<BR>> @@ -137,7 +137,7 @@<BR>> normal_image:<BR>> post_code(0x23);<BR>> __asm__ volatile ("jmp __normal_image": /* outputs */<BR>> - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);<BR>> + :"a" (bist), "b"(cpu_init_detectedx)); /* inputs */<BR>> <BR>> fallback_image:<BR>> post_code(0x25);<BR>> @@ -162,9 +162,9 @@<BR>> u32 bsp_apicid = 0;<BR>> msr_t msr;<BR>> struct cpuid_result cpuid1;<BR>> - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);<BR>> + struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +<BR>> + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);<BR>> <BR>> -<BR>> if (bist == 0) {<BR>> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<BR>> }<BR>> @@ -181,7 +181,7 @@<BR>> report_bist_failure(bist);<BR>> printk_debug("bsp_apicid=0x%x\n", bsp_apicid);<BR>> <BR>> - setup_dbm690t_resource_map();<BR>> + setup_mb_resource_map();<BR>> <BR>> setup_coherent_ht_domain();<BR>> <BR>> <BR>> <BR>> -- <BR>> http://www.hailfinger.org/<BR>> <BR><BR><br /><hr />Invite your mail contacts to join your friends list with Windows Live Spaces. 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